mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-23 18:35:47 +00:00
563 lines
17 KiB
C#
563 lines
17 KiB
C#
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using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics.X86;
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using static ChocolArm64.Instructions.InstEmitSimdHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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public static void Dup_Gp(ILEmitterCtx context)
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{
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OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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context.EmitLdintzr(op.Rn);
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switch (op.Size)
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{
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case 0: context.Emit(OpCodes.Conv_U1); break;
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case 1: context.Emit(OpCodes.Conv_U2); break;
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case 2: context.Emit(OpCodes.Conv_U4); break;
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}
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Type[] types = new Type[] { UIntTypesPerSizeLog2[op.Size] };
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), types));
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EmitStvecWithUnsignedCast(context, op.Rd, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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int bytes = op.GetBitsCount() >> 3;
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int elems = bytes >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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context.EmitLdintzr(op.Rn);
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EmitVectorInsert(context, op.Rd, index, op.Size);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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}
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public static void Dup_S(ILEmitterCtx context)
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{
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OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
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EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
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EmitScalarSet(context, op.Rd, op.Size);
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}
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public static void Dup_V(ILEmitterCtx context)
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{
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OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
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int bytes = op.GetBitsCount() >> 3;
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int elems = bytes >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
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EmitVectorInsert(context, op.Rd, index, op.Size);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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public static void Ext_V(ILEmitterCtx context)
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{
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OpCodeSimdExt64 op = (OpCodeSimdExt64)context.CurrOp;
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context.EmitLdvec(op.Rd);
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context.EmitStvectmp();
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int bytes = op.GetBitsCount() >> 3;
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int position = op.Imm4;
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for (int index = 0; index < bytes; index++)
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{
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int reg = op.Imm4 + index < bytes ? op.Rn : op.Rm;
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if (position == bytes)
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{
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position = 0;
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}
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EmitVectorExtractZx(context, reg, position++, 0);
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EmitVectorInsertTmp(context, index, 0);
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}
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context.EmitLdvectmp();
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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public static void Fcsel_S(ILEmitterCtx context)
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{
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OpCodeSimdFcond64 op = (OpCodeSimdFcond64)context.CurrOp;
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ILLabel lblTrue = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.EmitCondBranch(lblTrue, op.Cond);
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EmitVectorExtractF(context, op.Rm, 0, op.Size);
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context.Emit(OpCodes.Br_S, lblEnd);
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context.MarkLabel(lblTrue);
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EmitVectorExtractF(context, op.Rn, 0, op.Size);
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context.MarkLabel(lblEnd);
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EmitScalarSetF(context, op.Rd, op.Size);
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}
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public static void Fmov_Ftoi(ILEmitterCtx context)
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{
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OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
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EmitVectorExtractZx(context, op.Rn, 0, 3);
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EmitIntZeroUpperIfNeeded(context);
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context.EmitStintzr(op.Rd);
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}
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public static void Fmov_Ftoi1(ILEmitterCtx context)
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{
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OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
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EmitVectorExtractZx(context, op.Rn, 1, 3);
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EmitIntZeroUpperIfNeeded(context);
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context.EmitStintzr(op.Rd);
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}
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public static void Fmov_Itof(ILEmitterCtx context)
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{
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OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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EmitIntZeroUpperIfNeeded(context);
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EmitScalarSet(context, op.Rd, 3);
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}
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public static void Fmov_Itof1(ILEmitterCtx context)
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{
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OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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EmitIntZeroUpperIfNeeded(context);
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EmitVectorInsert(context, op.Rd, 1, 3);
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}
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public static void Fmov_S(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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EmitVectorExtractF(context, op.Rn, 0, op.Size);
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EmitScalarSetF(context, op.Rd, op.Size);
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}
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public static void Fmov_Si(ILEmitterCtx context)
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{
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OpCodeSimdFmov64 op = (OpCodeSimdFmov64)context.CurrOp;
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context.EmitLdc_I8(op.Imm);
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EmitScalarSet(context, op.Rd, op.Size + 2);
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}
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public static void Fmov_V(ILEmitterCtx context)
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{
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OpCodeSimdImm64 op = (OpCodeSimdImm64)context.CurrOp;
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int elems = op.RegisterSize == RegisterSize.Simd128 ? 4 : 2;
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for (int index = 0; index < (elems >> op.Size); index++)
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{
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context.EmitLdc_I8(op.Imm);
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EmitVectorInsert(context, op.Rd, index, op.Size + 2);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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public static void Ins_Gp(ILEmitterCtx context)
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{
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OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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EmitVectorInsert(context, op.Rd, op.DstIndex, op.Size);
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}
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public static void Ins_V(ILEmitterCtx context)
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{
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OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
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EmitVectorExtractZx(context, op.Rn, op.SrcIndex, op.Size);
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EmitVectorInsert(context, op.Rd, op.DstIndex, op.Size);
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}
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public static void Movi_V(ILEmitterCtx context)
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{
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EmitVectorImmUnaryOp(context, () => { });
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}
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public static void Mvni_V(ILEmitterCtx context)
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{
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EmitVectorImmUnaryOp(context, () => context.Emit(OpCodes.Not));
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}
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public static void Smov_S(ILEmitterCtx context)
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{
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OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
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EmitVectorExtractSx(context, op.Rn, op.DstIndex, op.Size);
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EmitIntZeroUpperIfNeeded(context);
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context.EmitStintzr(op.Rd);
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}
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public static void Tbl_V(ILEmitterCtx context)
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{
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OpCodeSimdTbl64 op = (OpCodeSimdTbl64)context.CurrOp;
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context.EmitLdvec(op.Rm);
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for (int index = 0; index < op.Size; index++)
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{
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context.EmitLdvec((op.Rn + index) & 0x1f);
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}
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switch (op.Size)
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{
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case 1: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl1_V64),
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nameof(VectorHelper.Tbl1_V128)); break;
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case 2: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl2_V64),
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nameof(VectorHelper.Tbl2_V128)); break;
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case 3: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl3_V64),
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nameof(VectorHelper.Tbl3_V128)); break;
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case 4: VectorHelper.EmitCall(context,
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nameof(VectorHelper.Tbl4_V64),
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nameof(VectorHelper.Tbl4_V128)); break;
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default: throw new InvalidOperationException();
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}
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context.EmitStvec(op.Rd);
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}
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public static void Trn1_V(ILEmitterCtx context)
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{
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EmitVectorTranspose(context, part: 0);
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}
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public static void Trn2_V(ILEmitterCtx context)
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{
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EmitVectorTranspose(context, part: 1);
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}
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public static void Umov_S(ILEmitterCtx context)
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{
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OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
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EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
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context.EmitStintzr(op.Rd);
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}
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public static void Uzp1_V(ILEmitterCtx context)
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{
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EmitVectorUnzip(context, part: 0);
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}
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public static void Uzp2_V(ILEmitterCtx context)
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{
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EmitVectorUnzip(context, part: 1);
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}
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public static void Xtn_V(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int elems = 8 >> op.Size;
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int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
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if (Optimizations.UseSse41 && op.Size < 2)
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{
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void EmitZeroVector()
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{
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switch (op.Size)
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{
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case 0: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInt16Zero)); break;
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case 1: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInt32Zero)); break;
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}
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}
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//For XTN, first operand is source, second operand is 0.
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//For XTN2, first operand is 0, second operand is source.
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if (part != 0)
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{
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EmitZeroVector();
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}
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EmitLdvecWithSignedCast(context, op.Rn, op.Size + 1);
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//Set mask to discard the upper half of the wide elements.
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switch (op.Size)
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{
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case 0: context.EmitLdc_I4(0x00ff); break;
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case 1: context.EmitLdc_I4(0x0000ffff); break;
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}
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Type wideType = IntTypesPerSizeLog2[op.Size + 1];
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), new Type[] { wideType }));
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wideType = VectorIntTypesPerSizeLog2[op.Size + 1];
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Type[] wideTypes = new Type[] { wideType, wideType };
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.And), wideTypes));
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if (part == 0)
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{
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EmitZeroVector();
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}
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//Pack values with signed saturation, the signed saturation shouldn't
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//saturate anything since the upper bits were masked off.
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Type sseType = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
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context.EmitCall(sseType.GetMethod(nameof(Sse2.PackUnsignedSaturate), wideTypes));
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if (part != 0)
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{
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//For XTN2, we additionally need to discard the upper bits
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//of the target register and OR the result with it.
|
||
|
|
EmitVectorZeroUpper(context, op.Rd);
|
||
|
|
|
||
|
|
EmitLdvecWithUnsignedCast(context, op.Rd, op.Size);
|
||
|
|
|
||
|
|
Type narrowType = VectorUIntTypesPerSizeLog2[op.Size];
|
||
|
|
|
||
|
|
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), new Type[] { narrowType, narrowType }));
|
||
|
|
}
|
||
|
|
|
||
|
|
EmitStvecWithUnsignedCast(context, op.Rd, op.Size);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if (part != 0)
|
||
|
|
{
|
||
|
|
context.EmitLdvec(op.Rd);
|
||
|
|
context.EmitStvectmp();
|
||
|
|
}
|
||
|
|
|
||
|
|
for (int index = 0; index < elems; index++)
|
||
|
|
{
|
||
|
|
EmitVectorExtractZx(context, op.Rn, index, op.Size + 1);
|
||
|
|
|
||
|
|
EmitVectorInsertTmp(context, part + index, op.Size);
|
||
|
|
}
|
||
|
|
|
||
|
|
context.EmitLdvectmp();
|
||
|
|
context.EmitStvec(op.Rd);
|
||
|
|
|
||
|
|
if (part == 0)
|
||
|
|
{
|
||
|
|
EmitVectorZeroUpper(context, op.Rd);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void Zip1_V(ILEmitterCtx context)
|
||
|
|
{
|
||
|
|
EmitVectorZip(context, part: 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void Zip2_V(ILEmitterCtx context)
|
||
|
|
{
|
||
|
|
EmitVectorZip(context, part: 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
private static void EmitIntZeroUpperIfNeeded(ILEmitterCtx context)
|
||
|
|
{
|
||
|
|
if (context.CurrOp.RegisterSize == RegisterSize.Int32 ||
|
||
|
|
context.CurrOp.RegisterSize == RegisterSize.Simd64)
|
||
|
|
{
|
||
|
|
context.Emit(OpCodes.Conv_U4);
|
||
|
|
context.Emit(OpCodes.Conv_U8);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
private static void EmitVectorTranspose(ILEmitterCtx context, int part)
|
||
|
|
{
|
||
|
|
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||
|
|
|
||
|
|
int words = op.GetBitsCount() >> 4;
|
||
|
|
int pairs = words >> op.Size;
|
||
|
|
|
||
|
|
for (int index = 0; index < pairs; index++)
|
||
|
|
{
|
||
|
|
int idx = index << 1;
|
||
|
|
|
||
|
|
EmitVectorExtractZx(context, op.Rn, idx + part, op.Size);
|
||
|
|
EmitVectorExtractZx(context, op.Rm, idx + part, op.Size);
|
||
|
|
|
||
|
|
EmitVectorInsertTmp(context, idx + 1, op.Size);
|
||
|
|
EmitVectorInsertTmp(context, idx, op.Size);
|
||
|
|
}
|
||
|
|
|
||
|
|
context.EmitLdvectmp();
|
||
|
|
context.EmitStvec(op.Rd);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
||
|
|
{
|
||
|
|
EmitVectorZeroUpper(context, op.Rd);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
private static void EmitVectorUnzip(ILEmitterCtx context, int part)
|
||
|
|
{
|
||
|
|
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||
|
|
|
||
|
|
int words = op.GetBitsCount() >> 4;
|
||
|
|
int pairs = words >> op.Size;
|
||
|
|
|
||
|
|
for (int index = 0; index < pairs; index++)
|
||
|
|
{
|
||
|
|
int idx = index << 1;
|
||
|
|
|
||
|
|
EmitVectorExtractZx(context, op.Rn, idx + part, op.Size);
|
||
|
|
EmitVectorExtractZx(context, op.Rm, idx + part, op.Size);
|
||
|
|
|
||
|
|
EmitVectorInsertTmp(context, pairs + index, op.Size);
|
||
|
|
EmitVectorInsertTmp(context, index, op.Size);
|
||
|
|
}
|
||
|
|
|
||
|
|
context.EmitLdvectmp();
|
||
|
|
context.EmitStvec(op.Rd);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
||
|
|
{
|
||
|
|
EmitVectorZeroUpper(context, op.Rd);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
private static void EmitVectorZip(ILEmitterCtx context, int part)
|
||
|
|
{
|
||
|
|
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||
|
|
|
||
|
|
if (Optimizations.UseSse2)
|
||
|
|
{
|
||
|
|
EmitLdvecWithUnsignedCast(context, op.Rn, op.Size);
|
||
|
|
EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
|
||
|
|
|
||
|
|
Type[] types = new Type[]
|
||
|
|
{
|
||
|
|
VectorUIntTypesPerSizeLog2[op.Size],
|
||
|
|
VectorUIntTypesPerSizeLog2[op.Size]
|
||
|
|
};
|
||
|
|
|
||
|
|
string name = part == 0 || (part != 0 && op.RegisterSize == RegisterSize.Simd64)
|
||
|
|
? nameof(Sse2.UnpackLow)
|
||
|
|
: nameof(Sse2.UnpackHigh);
|
||
|
|
|
||
|
|
context.EmitCall(typeof(Sse2).GetMethod(name, types));
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd64 && part != 0)
|
||
|
|
{
|
||
|
|
context.EmitLdc_I4(8);
|
||
|
|
|
||
|
|
Type[] shTypes = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) };
|
||
|
|
|
||
|
|
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), shTypes));
|
||
|
|
}
|
||
|
|
|
||
|
|
EmitStvecWithUnsignedCast(context, op.Rd, op.Size);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd64 && part == 0)
|
||
|
|
{
|
||
|
|
EmitVectorZeroUpper(context, op.Rd);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
int words = op.GetBitsCount() >> 4;
|
||
|
|
int pairs = words >> op.Size;
|
||
|
|
|
||
|
|
int Base = part != 0 ? pairs : 0;
|
||
|
|
|
||
|
|
for (int index = 0; index < pairs; index++)
|
||
|
|
{
|
||
|
|
int idx = index << 1;
|
||
|
|
|
||
|
|
EmitVectorExtractZx(context, op.Rn, Base + index, op.Size);
|
||
|
|
EmitVectorExtractZx(context, op.Rm, Base + index, op.Size);
|
||
|
|
|
||
|
|
EmitVectorInsertTmp(context, idx + 1, op.Size);
|
||
|
|
EmitVectorInsertTmp(context, idx, op.Size);
|
||
|
|
}
|
||
|
|
|
||
|
|
context.EmitLdvectmp();
|
||
|
|
context.EmitStvec(op.Rd);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
||
|
|
{
|
||
|
|
EmitVectorZeroUpper(context, op.Rd);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|