mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-23 09:15:46 +00:00
433 lines
20 KiB
C#
433 lines
20 KiB
C#
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#define SimdReg
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("SimdReg")]
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public sealed class CpuTestSimdReg : CpuTest
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{
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#if SimdReg
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[SetUp]
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public void SetupTester()
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{
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AArch64.TakeReset(false);
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}
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#region "ValueSource"
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private static ulong[] _D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B4H2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _16B8H4S2D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8H4S2D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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[Test, Description("ADD <V><d>, <V><n>, <V><m>")]
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public void Add_S_D([ValueSource("_D_")] [Random(1)] ulong A,
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[ValueSource("_D_")] [Random(1)] ulong B)
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{
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uint Opcode = 0x5EE28420; // ADD D0, D1, D2
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AVec V2 = new AVec { X0 = B };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.V(1, new Bits(A));
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AArch64.V(2, new Bits(B));
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SimdFp.Add_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Description("ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Add_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A,
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[ValueSource("_8B4H2S_")] [Random(1)] ulong B,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
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{
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uint Opcode = 0x0E228420; // ADD V0.8B, V1.8B, V2.8B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AVec V2 = new AVec { X0 = B };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.V(1, new Bits(A));
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AArch64.V(2, new Bits(B));
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SimdFp.Add_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Add_V_16B_8H_4S_2D([ValueSource("_16B8H4S2D_")] [Random(1)] ulong A0,
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[ValueSource("_16B8H4S2D_")] [Random(1)] ulong A1,
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[ValueSource("_16B8H4S2D_")] [Random(1)] ulong B0,
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[ValueSource("_16B8H4S2D_")] [Random(1)] ulong B1,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
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{
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uint Opcode = 0x4E228420; // ADD V0.16B, V1.16B, V2.16B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Add_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Pairwise, Description("ADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
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public void Addhn_V_8H8B_4S4H_2D2S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong A1,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
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{
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uint Opcode = 0x0E224020; // ADDHN V0.8B, V1.8H, V2.8H
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Addhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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});
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}
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[Test, Pairwise, Description("ADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
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public void Addhn_V_8H16B_4S8H_2D4S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong A1,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
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{
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uint Opcode = 0x4E224020; // ADDHN2 V0.16B, V1.8H, V2.8H
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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ulong _X0 = TestContext.CurrentContext.Random.NextULong();
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AVec V0 = new AVec { X0 = _X0 };
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Addhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(_X0));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Pairwise, Description("RADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
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public void Raddhn_V_8H8B_4S4H_2D2S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong A1,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
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{
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uint Opcode = 0x2E224020; // RADDHN V0.8B, V1.8H, V2.8H
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Raddhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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});
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}
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[Test, Pairwise, Description("RADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
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public void Raddhn_V_8H16B_4S8H_2D4S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong A1,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
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{
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uint Opcode = 0x6E224020; // RADDHN2 V0.16B, V1.8H, V2.8H
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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ulong _X0 = TestContext.CurrentContext.Random.NextULong();
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AVec V0 = new AVec { X0 = _X0 };
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Raddhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(_X0));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Pairwise, Description("RSUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
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public void Rsubhn_V_8H8B_4S4H_2D2S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong A1,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
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{
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uint Opcode = 0x2E226020; // RSUBHN V0.8B, V1.8H, V2.8H
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Rsubhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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});
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}
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[Test, Pairwise, Description("RSUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
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public void Rsubhn_V_8H16B_4S8H_2D4S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong A1,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B0,
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[ValueSource("_8H4S2D_")] [Random(1)] ulong B1,
|
||
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
|
||
|
|
{
|
||
|
|
uint Opcode = 0x6E226020; // RSUBHN2 V0.16B, V1.8H, V2.8H
|
||
|
|
Opcode |= ((size & 3) << 22);
|
||
|
|
Bits Op = new Bits(Opcode);
|
||
|
|
|
||
|
|
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
|
||
|
|
AVec V0 = new AVec { X0 = _X0 };
|
||
|
|
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||
|
|
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||
|
|
|
||
|
|
AArch64.Vpart(1, 0, new Bits(A0));
|
||
|
|
AArch64.Vpart(1, 1, new Bits(A1));
|
||
|
|
AArch64.Vpart(2, 0, new Bits(B0));
|
||
|
|
AArch64.Vpart(2, 1, new Bits(B1));
|
||
|
|
SimdFp.Rsubhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||
|
|
|
||
|
|
Assert.Multiple(() =>
|
||
|
|
{
|
||
|
|
Assert.That(ThreadState.V0.X0, Is.EqualTo(_X0));
|
||
|
|
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||
|
|
});
|
||
|
|
}
|
||
|
|
|
||
|
|
[Test, Description("SUB <V><d>, <V><n>, <V><m>")]
|
||
|
|
public void Sub_S_D([ValueSource("_D_")] [Random(1)] ulong A,
|
||
|
|
[ValueSource("_D_")] [Random(1)] ulong B)
|
||
|
|
{
|
||
|
|
uint Opcode = 0x7EE28420; // SUB D0, D1, D2
|
||
|
|
Bits Op = new Bits(Opcode);
|
||
|
|
|
||
|
|
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||
|
|
AVec V1 = new AVec { X0 = A };
|
||
|
|
AVec V2 = new AVec { X0 = B };
|
||
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||
|
|
|
||
|
|
AArch64.V(1, new Bits(A));
|
||
|
|
AArch64.V(2, new Bits(B));
|
||
|
|
SimdFp.Sub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||
|
|
|
||
|
|
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||
|
|
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||
|
|
}
|
||
|
|
|
||
|
|
[Test, Description("SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||
|
|
public void Sub_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A,
|
||
|
|
[ValueSource("_8B4H2S_")] [Random(1)] ulong B,
|
||
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||
|
|
{
|
||
|
|
uint Opcode = 0x2E228420; // SUB V0.8B, V1.8B, V2.8B
|
||
|
|
Opcode |= ((size & 3) << 22);
|
||
|
|
Bits Op = new Bits(Opcode);
|
||
|
|
|
||
|
|
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||
|
|
AVec V1 = new AVec { X0 = A };
|
||
|
|
AVec V2 = new AVec { X0 = B };
|
||
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||
|
|
|
||
|
|
AArch64.V(1, new Bits(A));
|
||
|
|
AArch64.V(2, new Bits(B));
|
||
|
|
SimdFp.Sub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||
|
|
|
||
|
|
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||
|
|
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||
|
|
}
|
||
|
|
|
||
|
|
[Test, Pairwise, Description("SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||
|
|
public void Sub_V_16B_8H_4S_2D([ValueSource("_16B8H4S2D_")] [Random(1)] ulong A0,
|
||
|
|
[ValueSource("_16B8H4S2D_")] [Random(1)] ulong A1,
|
||
|
|
[ValueSource("_16B8H4S2D_")] [Random(1)] ulong B0,
|
||
|
|
[ValueSource("_16B8H4S2D_")] [Random(1)] ulong B1,
|
||
|
|
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
||
|
|
{
|
||
|
|
uint Opcode = 0x6E228420; // SUB V0.16B, V1.16B, V2.16B
|
||
|
|
Opcode |= ((size & 3) << 22);
|
||
|
|
Bits Op = new Bits(Opcode);
|
||
|
|
|
||
|
|
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||
|
|
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||
|
|
|
||
|
|
AArch64.Vpart(1, 0, new Bits(A0));
|
||
|
|
AArch64.Vpart(1, 1, new Bits(A1));
|
||
|
|
AArch64.Vpart(2, 0, new Bits(B0));
|
||
|
|
AArch64.Vpart(2, 1, new Bits(B1));
|
||
|
|
SimdFp.Sub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||
|
|
|
||
|
|
Assert.Multiple(() =>
|
||
|
|
{
|
||
|
|
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||
|
|
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||
|
|
});
|
||
|
|
}
|
||
|
|
|
||
|
|
[Test, Pairwise, Description("SUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
|
||
|
|
public void Subhn_V_8H8B_4S4H_2D2S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0,
|
||
|
|
[ValueSource("_8H4S2D_")] [Random(1)] ulong A1,
|
||
|
|
[ValueSource("_8H4S2D_")] [Random(1)] ulong B0,
|
||
|
|
[ValueSource("_8H4S2D_")] [Random(1)] ulong B1,
|
||
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
|
||
|
|
{
|
||
|
|
uint Opcode = 0x0E226020; // SUBHN V0.8B, V1.8H, V2.8H
|
||
|
|
Opcode |= ((size & 3) << 22);
|
||
|
|
Bits Op = new Bits(Opcode);
|
||
|
|
|
||
|
|
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||
|
|
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||
|
|
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||
|
|
|
||
|
|
AArch64.Vpart(1, 0, new Bits(A0));
|
||
|
|
AArch64.Vpart(1, 1, new Bits(A1));
|
||
|
|
AArch64.Vpart(2, 0, new Bits(B0));
|
||
|
|
AArch64.Vpart(2, 1, new Bits(B1));
|
||
|
|
SimdFp.Subhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||
|
|
|
||
|
|
Assert.Multiple(() =>
|
||
|
|
{
|
||
|
|
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||
|
|
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||
|
|
});
|
||
|
|
}
|
||
|
|
|
||
|
|
[Test, Pairwise, Description("SUBHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
|
||
|
|
public void Subhn_V_8H16B_4S8H_2D4S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0,
|
||
|
|
[ValueSource("_8H4S2D_")] [Random(1)] ulong A1,
|
||
|
|
[ValueSource("_8H4S2D_")] [Random(1)] ulong B0,
|
||
|
|
[ValueSource("_8H4S2D_")] [Random(1)] ulong B1,
|
||
|
|
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
|
||
|
|
{
|
||
|
|
uint Opcode = 0x4E226020; // SUBHN2 V0.16B, V1.8H, V2.8H
|
||
|
|
Opcode |= ((size & 3) << 22);
|
||
|
|
Bits Op = new Bits(Opcode);
|
||
|
|
|
||
|
|
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
|
||
|
|
AVec V0 = new AVec { X0 = _X0 };
|
||
|
|
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||
|
|
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||
|
|
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||
|
|
|
||
|
|
AArch64.Vpart(1, 0, new Bits(A0));
|
||
|
|
AArch64.Vpart(1, 1, new Bits(A1));
|
||
|
|
AArch64.Vpart(2, 0, new Bits(B0));
|
||
|
|
AArch64.Vpart(2, 1, new Bits(B1));
|
||
|
|
SimdFp.Subhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||
|
|
|
||
|
|
Assert.Multiple(() =>
|
||
|
|
{
|
||
|
|
Assert.That(ThreadState.V0.X0, Is.EqualTo(_X0));
|
||
|
|
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||
|
|
});
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|