mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-23 17:25:48 +00:00
527 lines
15 KiB
C#
527 lines
15 KiB
C#
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using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics.X86;
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using static ChocolArm64.Instructions.InstEmitAluHelper;
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using static ChocolArm64.Instructions.InstEmitSimdHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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public static void Cmeq_S(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Beq_S, scalar: true);
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}
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public static void Cmeq_V(ILEmitterCtx context)
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{
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if (context.CurrOp is OpCodeSimdReg64 op)
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{
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if (op.Size < 3 && Optimizations.UseSse2)
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{
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EmitSse2Op(context, nameof(Sse2.CompareEqual));
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}
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else if (op.Size == 3 && Optimizations.UseSse41)
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{
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EmitSse41Op(context, nameof(Sse41.CompareEqual));
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}
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else
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{
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EmitCmp(context, OpCodes.Beq_S, scalar: false);
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}
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}
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else
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{
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EmitCmp(context, OpCodes.Beq_S, scalar: false);
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}
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}
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public static void Cmge_S(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Bge_S, scalar: true);
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}
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public static void Cmge_V(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Bge_S, scalar: false);
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}
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public static void Cmgt_S(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Bgt_S, scalar: true);
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}
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public static void Cmgt_V(ILEmitterCtx context)
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{
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if (context.CurrOp is OpCodeSimdReg64 op)
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{
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if (op.Size < 3 && Optimizations.UseSse2)
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{
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EmitSse2Op(context, nameof(Sse2.CompareGreaterThan));
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}
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else if (op.Size == 3 && Optimizations.UseSse42)
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{
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EmitSse42Op(context, nameof(Sse42.CompareGreaterThan));
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}
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else
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{
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EmitCmp(context, OpCodes.Bgt_S, scalar: false);
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}
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}
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else
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{
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EmitCmp(context, OpCodes.Bgt_S, scalar: false);
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}
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}
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public static void Cmhi_S(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Bgt_Un_S, scalar: true);
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}
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public static void Cmhi_V(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Bgt_Un_S, scalar: false);
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}
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public static void Cmhs_S(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Bge_Un_S, scalar: true);
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}
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public static void Cmhs_V(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Bge_Un_S, scalar: false);
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}
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public static void Cmle_S(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Ble_S, scalar: true);
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}
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public static void Cmle_V(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Ble_S, scalar: false);
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}
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public static void Cmlt_S(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Blt_S, scalar: true);
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}
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public static void Cmlt_V(ILEmitterCtx context)
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{
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EmitCmp(context, OpCodes.Blt_S, scalar: false);
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}
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public static void Cmtst_S(ILEmitterCtx context)
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{
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EmitCmtst(context, scalar: true);
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}
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public static void Cmtst_V(ILEmitterCtx context)
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{
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EmitCmtst(context, scalar: false);
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}
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public static void Fccmp_S(ILEmitterCtx context)
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{
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OpCodeSimdFcond64 op = (OpCodeSimdFcond64)context.CurrOp;
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ILLabel lblTrue = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.EmitCondBranch(lblTrue, op.Cond);
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EmitSetNzcv(context, op.Nzcv);
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context.Emit(OpCodes.Br, lblEnd);
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context.MarkLabel(lblTrue);
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Fcmp_S(context);
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context.MarkLabel(lblEnd);
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}
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public static void Fccmpe_S(ILEmitterCtx context)
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{
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Fccmp_S(context);
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}
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public static void Fcmeq_S(ILEmitterCtx context)
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{
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if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
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&& Optimizations.UseSse2)
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{
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EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareEqualScalar));
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}
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else
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{
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EmitScalarFcmp(context, OpCodes.Beq_S);
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}
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}
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public static void Fcmeq_V(ILEmitterCtx context)
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{
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if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
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&& Optimizations.UseSse2)
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{
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EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareEqual));
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}
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else
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{
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EmitVectorFcmp(context, OpCodes.Beq_S);
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}
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}
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public static void Fcmge_S(ILEmitterCtx context)
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{
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if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
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&& Optimizations.UseSse2)
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{
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EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanOrEqualScalar));
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}
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else
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{
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EmitScalarFcmp(context, OpCodes.Bge_S);
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}
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}
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public static void Fcmge_V(ILEmitterCtx context)
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{
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if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
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&& Optimizations.UseSse2)
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{
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EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanOrEqual));
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}
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else
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{
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EmitVectorFcmp(context, OpCodes.Bge_S);
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}
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}
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public static void Fcmgt_S(ILEmitterCtx context)
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{
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if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
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&& Optimizations.UseSse2)
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{
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EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanScalar));
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}
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else
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{
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EmitScalarFcmp(context, OpCodes.Bgt_S);
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}
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}
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public static void Fcmgt_V(ILEmitterCtx context)
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{
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if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
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&& Optimizations.UseSse2)
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{
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EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareGreaterThan));
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}
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else
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{
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EmitVectorFcmp(context, OpCodes.Bgt_S);
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}
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}
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public static void Fcmle_S(ILEmitterCtx context)
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{
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EmitScalarFcmp(context, OpCodes.Ble_S);
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}
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public static void Fcmle_V(ILEmitterCtx context)
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{
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EmitVectorFcmp(context, OpCodes.Ble_S);
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}
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public static void Fcmlt_S(ILEmitterCtx context)
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{
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EmitScalarFcmp(context, OpCodes.Blt_S);
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}
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public static void Fcmlt_V(ILEmitterCtx context)
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{
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EmitVectorFcmp(context, OpCodes.Blt_S);
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}
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public static void Fcmp_S(ILEmitterCtx context)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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bool cmpWithZero = !(op is OpCodeSimdFcond64) ? op.Bit3 : false;
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//Handle NaN case.
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//If any number is NaN, then NZCV = 0011.
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if (cmpWithZero)
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{
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EmitNaNCheck(context, op.Rn);
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}
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else
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{
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EmitNaNCheck(context, op.Rn);
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EmitNaNCheck(context, op.Rm);
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context.Emit(OpCodes.Or);
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}
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ILLabel lblNaN = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.Emit(OpCodes.Brtrue_S, lblNaN);
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void EmitLoadOpers()
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{
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EmitVectorExtractF(context, op.Rn, 0, op.Size);
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if (cmpWithZero)
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{
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if (op.Size == 0)
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{
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context.EmitLdc_R4(0f);
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}
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else /* if (Op.Size == 1) */
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{
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context.EmitLdc_R8(0d);
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}
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}
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else
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{
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EmitVectorExtractF(context, op.Rm, 0, op.Size);
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}
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}
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//Z = Rn == Rm
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EmitLoadOpers();
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context.Emit(OpCodes.Ceq);
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context.Emit(OpCodes.Dup);
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context.EmitStflg((int)PState.ZBit);
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//C = Rn >= Rm
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EmitLoadOpers();
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context.Emit(OpCodes.Cgt);
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context.Emit(OpCodes.Or);
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context.EmitStflg((int)PState.CBit);
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//N = Rn < Rm
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EmitLoadOpers();
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context.Emit(OpCodes.Clt);
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context.EmitStflg((int)PState.NBit);
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//V = 0
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context.EmitLdc_I4(0);
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context.EmitStflg((int)PState.VBit);
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context.Emit(OpCodes.Br_S, lblEnd);
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context.MarkLabel(lblNaN);
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EmitSetNzcv(context, 0b0011);
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context.MarkLabel(lblEnd);
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}
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public static void Fcmpe_S(ILEmitterCtx context)
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{
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Fcmp_S(context);
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}
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private static void EmitNaNCheck(ILEmitterCtx context, int reg)
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{
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IOpCodeSimd64 op = (IOpCodeSimd64)context.CurrOp;
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EmitVectorExtractF(context, reg, 0, op.Size);
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if (op.Size == 0)
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{
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context.EmitCall(typeof(float), nameof(float.IsNaN));
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}
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else if (op.Size == 1)
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{
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context.EmitCall(typeof(double), nameof(double.IsNaN));
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}
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else
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{
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throw new InvalidOperationException();
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}
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}
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private static void EmitCmp(ILEmitterCtx context, OpCode ilOp, bool scalar)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int bytes = op.GetBitsCount() >> 3;
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int elems = !scalar ? bytes >> op.Size : 1;
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ulong szMask = ulong.MaxValue >> (64 - (8 << op.Size));
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for (int index = 0; index < elems; index++)
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{
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EmitVectorExtractSx(context, op.Rn, index, op.Size);
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if (op is OpCodeSimdReg64 binOp)
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{
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EmitVectorExtractSx(context, binOp.Rm, index, op.Size);
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}
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else
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{
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context.EmitLdc_I8(0L);
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}
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ILLabel lblTrue = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.Emit(ilOp, lblTrue);
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EmitVectorInsert(context, op.Rd, index, op.Size, 0);
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context.Emit(OpCodes.Br_S, lblEnd);
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context.MarkLabel(lblTrue);
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EmitVectorInsert(context, op.Rd, index, op.Size, (long)szMask);
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|
|
||
|
|
context.MarkLabel(lblEnd);
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
|
||
|
|
{
|
||
|
|
EmitVectorZeroUpper(context, op.Rd);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
private static void EmitCmtst(ILEmitterCtx context, bool scalar)
|
||
|
|
{
|
||
|
|
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||
|
|
|
||
|
|
int bytes = op.GetBitsCount() >> 3;
|
||
|
|
int elems = !scalar ? bytes >> op.Size : 1;
|
||
|
|
|
||
|
|
ulong szMask = ulong.MaxValue >> (64 - (8 << op.Size));
|
||
|
|
|
||
|
|
for (int index = 0; index < elems; index++)
|
||
|
|
{
|
||
|
|
EmitVectorExtractZx(context, op.Rn, index, op.Size);
|
||
|
|
EmitVectorExtractZx(context, op.Rm, index, op.Size);
|
||
|
|
|
||
|
|
ILLabel lblTrue = new ILLabel();
|
||
|
|
ILLabel lblEnd = new ILLabel();
|
||
|
|
|
||
|
|
context.Emit(OpCodes.And);
|
||
|
|
|
||
|
|
context.EmitLdc_I8(0L);
|
||
|
|
|
||
|
|
context.Emit(OpCodes.Bne_Un_S, lblTrue);
|
||
|
|
|
||
|
|
EmitVectorInsert(context, op.Rd, index, op.Size, 0);
|
||
|
|
|
||
|
|
context.Emit(OpCodes.Br_S, lblEnd);
|
||
|
|
|
||
|
|
context.MarkLabel(lblTrue);
|
||
|
|
|
||
|
|
EmitVectorInsert(context, op.Rd, index, op.Size, (long)szMask);
|
||
|
|
|
||
|
|
context.MarkLabel(lblEnd);
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
|
||
|
|
{
|
||
|
|
EmitVectorZeroUpper(context, op.Rd);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
private static void EmitScalarFcmp(ILEmitterCtx context, OpCode ilOp)
|
||
|
|
{
|
||
|
|
EmitFcmp(context, ilOp, 0, scalar: true);
|
||
|
|
}
|
||
|
|
|
||
|
|
private static void EmitVectorFcmp(ILEmitterCtx context, OpCode ilOp)
|
||
|
|
{
|
||
|
|
OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
|
||
|
|
|
||
|
|
int sizeF = op.Size & 1;
|
||
|
|
|
||
|
|
int bytes = op.GetBitsCount() >> 3;
|
||
|
|
int elems = bytes >> sizeF + 2;
|
||
|
|
|
||
|
|
for (int index = 0; index < elems; index++)
|
||
|
|
{
|
||
|
|
EmitFcmp(context, ilOp, index, scalar: false);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
||
|
|
{
|
||
|
|
EmitVectorZeroUpper(context, op.Rd);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
private static void EmitFcmp(ILEmitterCtx context, OpCode ilOp, int index, bool scalar)
|
||
|
|
{
|
||
|
|
OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
|
||
|
|
|
||
|
|
int sizeF = op.Size & 1;
|
||
|
|
|
||
|
|
ulong szMask = ulong.MaxValue >> (64 - (32 << sizeF));
|
||
|
|
|
||
|
|
EmitVectorExtractF(context, op.Rn, index, sizeF);
|
||
|
|
|
||
|
|
if (op is OpCodeSimdReg64 binOp)
|
||
|
|
{
|
||
|
|
EmitVectorExtractF(context, binOp.Rm, index, sizeF);
|
||
|
|
}
|
||
|
|
else if (sizeF == 0)
|
||
|
|
{
|
||
|
|
context.EmitLdc_R4(0f);
|
||
|
|
}
|
||
|
|
else /* if (SizeF == 1) */
|
||
|
|
{
|
||
|
|
context.EmitLdc_R8(0d);
|
||
|
|
}
|
||
|
|
|
||
|
|
ILLabel lblTrue = new ILLabel();
|
||
|
|
ILLabel lblEnd = new ILLabel();
|
||
|
|
|
||
|
|
context.Emit(ilOp, lblTrue);
|
||
|
|
|
||
|
|
if (scalar)
|
||
|
|
{
|
||
|
|
EmitVectorZeroAll(context, op.Rd);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
EmitVectorInsert(context, op.Rd, index, sizeF + 2, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Emit(OpCodes.Br_S, lblEnd);
|
||
|
|
|
||
|
|
context.MarkLabel(lblTrue);
|
||
|
|
|
||
|
|
if (scalar)
|
||
|
|
{
|
||
|
|
EmitVectorInsert(context, op.Rd, index, 3, (long)szMask);
|
||
|
|
|
||
|
|
EmitVectorZeroUpper(context, op.Rd);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
EmitVectorInsert(context, op.Rd, index, sizeF + 2, (long)szMask);
|
||
|
|
}
|
||
|
|
|
||
|
|
context.MarkLabel(lblEnd);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|