emu-mirrors/Ryujinx
0
0
Fork 0
mirror of https://github.com/GreemDev/Ryujinx.git synced 2024-12-23 17:25:48 +00:00
Code Wiki Activity
Ryujinx/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs

239 lines
10 KiB
C#
Raw Normal View History

Add a new JIT compiler for CPU code (#693) * Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 18:56:22 +00:00
#define AluBinary
using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
[Category("AluBinary")]
public sealed class CpuTestAluBinary : CpuTest
{
#if AluBinary
private const int RndCnt = 2;
[Test, Pairwise, Description("CRC32X <Wd>, <Wn>, <Xm>"), Ignore("Unicorn fails.")]
public void Crc32x([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values((ulong)0x00_00_00_00_00_00_00_00,
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
(ulong)0x80_00_00_00_00_00_00_00,
(ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
{
uint opcode = 0x9AC04C00; // CRC32X W0, W0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, x1: wn, x2: xm, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("CRC32W <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
public void Crc32w([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
(uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
{
uint opcode = 0x1AC04800; // CRC32W W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("CRC32H <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
public void Crc32h([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values((ushort)0x00_00, (ushort)0x7F_FF,
(ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
{
uint opcode = 0x1AC04400; // CRC32H W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("CRC32B <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
public void Crc32b([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values((byte)0x00, (byte)0x7F,
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
{
uint opcode = 0x1AC04000; // CRC32B W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("CRC32CX <Wd>, <Wn>, <Xm>")]
public void Crc32cx([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values((ulong)0x00_00_00_00_00_00_00_00,
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
(ulong)0x80_00_00_00_00_00_00_00,
(ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
{
uint opcode = 0x9AC05C00; // CRC32CX W0, W0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, x1: wn, x2: xm, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("CRC32CW <Wd>, <Wn>, <Wm>")]
public void Crc32cw([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
(uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
{
uint opcode = 0x1AC05800; // CRC32CW W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("CRC32CH <Wd>, <Wn>, <Wm>")]
public void Crc32ch([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values((ushort)0x00_00, (ushort)0x7F_FF,
(ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
{
uint opcode = 0x1AC05400; // CRC32CH W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("CRC32CB <Wd>, <Wn>, <Wm>")]
public void Crc32cb([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values((byte)0x00, (byte)0x7F,
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
{
uint opcode = 0x1AC05000; // CRC32CB W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SDIV <Xd>, <Xn>, <Xm>")]
public void Sdiv_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
{
uint opcode = 0x9AC00C00; // SDIV X0, X0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
SingleOpcode(opcode, x1: xn, x2: xm, x31: x31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SDIV <Wd>, <Wn>, <Wm>")]
public void Sdiv_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
{
uint opcode = 0x1AC00C00; // SDIV W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("UDIV <Xd>, <Xn>, <Xm>")]
public void Udiv_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
{
uint opcode = 0x9AC00800; // UDIV X0, X0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
SingleOpcode(opcode, x1: xn, x2: xm, x31: x31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("UDIV <Wd>, <Wn>, <Wm>")]
public void Udiv_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
{
uint opcode = 0x1AC00800; // UDIV W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
CompareAgainstUnicorn();
}
#endif
}
}
Copy permalink