mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-23 03:25:46 +00:00
Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. Now all saturating methods are on ASoftFallback. (#334)
* Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update CpuTestAlu.cs * Update CpuTestAluImm.cs * Update CpuTestAluRs.cs * Update CpuTestAluRx.cs * Update CpuTestBfm.cs * Update CpuTestCcmpImm.cs * Update CpuTestCcmpReg.cs * Update CpuTestCsel.cs * Update CpuTestMov.cs * Update CpuTestMul.cs * Update Ryujinx.Tests.csproj * Update Ryujinx.csproj * Update Luea.csproj * Update Ryujinx.ShaderTools.csproj * Address PR feedback (further tested). * Address PR feedback.
This commit is contained in:
parent
267af1f0f7
commit
02a6fdcd13
21 changed files with 834 additions and 314 deletions
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@ -380,8 +380,16 @@ namespace ChocolArm64
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SetA64("0>001110<<100000011110xxxxxxxxxx", AInstEmit.Sqabs_V, typeof(AOpCodeSimd));
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SetA64("01011110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_S, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_V, typeof(AOpCodeSimdReg));
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SetA64("01011110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_S, typeof(AOpCodeSimdReg));
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SetA64("01011110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_S, typeof(AOpCodeSimdReg));
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SetA64("0x001110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_V, typeof(AOpCodeSimdReg));
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SetA64("01111110xx100000011110xxxxxxxxxx", AInstEmit.Sqneg_S, typeof(AOpCodeSimd));
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SetA64("0>101110<<100000011110xxxxxxxxxx", AInstEmit.Sqneg_V, typeof(AOpCodeSimd));
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SetA64("01111110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg));
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SetA64("01111110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg));
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SetA64("0x101110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg));
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SetA64("0x00111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_V, typeof(AOpCodeSimdShImm));
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SetA64("01011110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_S, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_V, typeof(AOpCodeSimdReg));
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@ -158,6 +158,42 @@ namespace ChocolArm64.Instruction
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Context.MarkLabel(LblTrue);
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}
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private static void EmitDoublingMultiplyHighHalf(AILEmitterCtx Context, bool Round)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int ESize = 8 << Op.Size;
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Context.Emit(OpCodes.Mul);
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if (!Round)
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{
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Context.EmitAsr(ESize - 1);
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}
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else
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{
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long RoundConst = 1L << (ESize - 1);
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AILLabel LblTrue = new AILLabel();
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Context.EmitLsl(1);
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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Context.EmitAsr(ESize);
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I8((long)int.MinValue);
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Context.Emit(OpCodes.Bne_Un_S, LblTrue);
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Context.Emit(OpCodes.Neg);
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Context.MarkLabel(LblTrue);
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}
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}
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private static void EmitHighNarrow(AILEmitterCtx Context, Action Emit, bool Round)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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@ -1040,6 +1076,16 @@ namespace ChocolArm64.Instruction
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EmitVectorSaturatingBinaryOpSx(Context, SaturatingFlags.Add);
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}
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public static void Sqdmulh_S(AILEmitterCtx Context)
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{
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EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: false), SaturatingFlags.ScalarSx);
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}
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public static void Sqdmulh_V(AILEmitterCtx Context)
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{
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EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: false), SaturatingFlags.VectorSx);
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}
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public static void Sqneg_S(AILEmitterCtx Context)
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{
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EmitScalarSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
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@ -1050,6 +1096,16 @@ namespace ChocolArm64.Instruction
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EmitVectorSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
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}
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public static void Sqrdmulh_S(AILEmitterCtx Context)
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{
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EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: true), SaturatingFlags.ScalarSx);
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}
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public static void Sqrdmulh_V(AILEmitterCtx Context)
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{
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EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: true), SaturatingFlags.VectorSx);
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}
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public static void Sqsub_S(AILEmitterCtx Context)
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{
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EmitScalarSaturatingBinaryOpSx(Context, SaturatingFlags.Sub);
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@ -804,7 +804,7 @@ namespace ChocolArm64.Instruction
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ScalarZx = Scalar,
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VectorSx = Signed,
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VectorZx = 0,
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VectorZx = 0
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}
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public static void EmitScalarSaturatingUnaryOpSx(AILEmitterCtx Context, Action Emit)
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@ -837,7 +837,14 @@ namespace ChocolArm64.Instruction
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Emit();
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EmitUnarySignedSatQAbsOrNeg(Context, Op.Size);
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if (Op.Size <= 2)
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{
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EmitSatQ(Context, Op.Size, true, true);
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}
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else /* if (Op.Size == 3) */
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{
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EmitUnarySignedSatQAbsOrNeg(Context);
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}
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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@ -853,25 +860,25 @@ namespace ChocolArm64.Instruction
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public static void EmitScalarSaturatingBinaryOpSx(AILEmitterCtx Context, SaturatingFlags Flags)
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{
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EmitSaturatingBinaryOp(Context, SaturatingFlags.ScalarSx | Flags);
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EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.ScalarSx | Flags);
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}
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public static void EmitScalarSaturatingBinaryOpZx(AILEmitterCtx Context, SaturatingFlags Flags)
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{
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EmitSaturatingBinaryOp(Context, SaturatingFlags.ScalarZx | Flags);
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EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.ScalarZx | Flags);
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}
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public static void EmitVectorSaturatingBinaryOpSx(AILEmitterCtx Context, SaturatingFlags Flags)
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{
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EmitSaturatingBinaryOp(Context, SaturatingFlags.VectorSx | Flags);
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EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.VectorSx | Flags);
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}
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public static void EmitVectorSaturatingBinaryOpZx(AILEmitterCtx Context, SaturatingFlags Flags)
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{
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EmitSaturatingBinaryOp(Context, SaturatingFlags.VectorZx | Flags);
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EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.VectorZx | Flags);
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}
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public static void EmitSaturatingBinaryOp(AILEmitterCtx Context, SaturatingFlags Flags)
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public static void EmitSaturatingBinaryOp(AILEmitterCtx Context, Action Emit, SaturatingFlags Flags)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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@ -940,6 +947,20 @@ namespace ChocolArm64.Instruction
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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}
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else
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{
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size, Signed);
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Emit();
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EmitSatQ(Context, Op.Size, true, Signed);
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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@ -1080,29 +1101,17 @@ namespace ChocolArm64.Instruction
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}
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}
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// TSrc (8bit, 16bit, 32bit, 64bit) == TDst (8bit, 16bit, 32bit, 64bit); signed.
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public static void EmitUnarySignedSatQAbsOrNeg(AILEmitterCtx Context, int Size)
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// TSrc (64bit) == TDst (64bit); signed.
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public static void EmitUnarySignedSatQAbsOrNeg(AILEmitterCtx Context)
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{
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int ESize = 8 << Size;
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if (((AOpCodeSimd)Context.CurrOp).Size < 3)
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{
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throw new InvalidOperationException();
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}
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long TMaxValue = (1L << (ESize - 1)) - 1L;
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long TMinValue = -(1L << (ESize - 1));
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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AILLabel LblFalse = new AILLabel();
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Context.Emit(OpCodes.Dup);
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Context.Emit(OpCodes.Neg);
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Context.EmitLdc_I8(TMinValue);
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Context.Emit(OpCodes.Ceq);
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Context.Emit(OpCodes.Brfalse_S, LblFalse);
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Context.Emit(OpCodes.Pop);
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EmitSetFpsrQCFlag(Context);
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Context.EmitLdc_I8(TMaxValue);
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Context.MarkLabel(LblFalse);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.UnarySignedSatQAbsOrNeg));
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}
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// TSrcs (64bit) == TDst (64bit); signed, unsigned.
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@ -1150,22 +1159,6 @@ namespace ChocolArm64.Instruction
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: nameof(ASoftFallback.BinaryUnsignedSatQAcc));
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}
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public static void EmitSetFpsrQCFlag(AILEmitterCtx Context)
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{
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const int QCFlagBit = 27;
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpsr));
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Context.EmitLdc_I4(1 << QCFlagBit);
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Context.Emit(OpCodes.Or);
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Context.EmitCallPropSet(typeof(AThreadState), nameof(AThreadState.Fpsr));
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}
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public static void EmitScalarSet(AILEmitterCtx Context, int Reg, int Size)
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{
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EmitVectorZeroAll(Context, Reg);
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@ -11,6 +11,107 @@ namespace ChocolArm64.Instruction
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Context.EmitCall(typeof(ASoftFallback), MthdName);
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}
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#region "Saturating"
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public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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long TMaxValue = (1L << (ESize - 1)) - 1L;
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long TMinValue = -(1L << (ESize - 1));
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if (op > TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else if (op < TMinValue)
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{
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SetFpsrQCFlag(State);
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return TMinValue;
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}
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else
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{
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return op;
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}
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}
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public static ulong SignedSrcUnsignedDstSatQ(long op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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ulong TMaxValue = (1UL << ESize) - 1UL;
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ulong TMinValue = 0UL;
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if (op > (long)TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else if (op < (long)TMinValue)
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{
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SetFpsrQCFlag(State);
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return TMinValue;
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}
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else
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{
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return (ulong)op;
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}
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}
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public static long UnsignedSrcSignedDstSatQ(ulong op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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long TMaxValue = (1L << (ESize - 1)) - 1L;
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if (op > (ulong)TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else
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{
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return (long)op;
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}
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}
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public static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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ulong TMaxValue = (1UL << ESize) - 1UL;
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if (op > TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else
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{
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return op;
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}
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}
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public static long UnarySignedSatQAbsOrNeg(long op, AThreadState State)
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{
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if (op == long.MinValue)
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{
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SetFpsrQCFlag(State);
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return long.MaxValue;
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}
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else
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{
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return op;
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}
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}
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public static long BinarySignedSatQAdd(long op1, long op2, AThreadState State)
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{
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long Add = op1 + op2;
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@ -185,99 +286,15 @@ namespace ChocolArm64.Instruction
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}
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}
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public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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long TMaxValue = (1L << (ESize - 1)) - 1L;
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long TMinValue = -(1L << (ESize - 1));
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if (op > TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else if (op < TMinValue)
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{
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SetFpsrQCFlag(State);
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return TMinValue;
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}
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else
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{
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return op;
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}
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}
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public static ulong SignedSrcUnsignedDstSatQ(long op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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ulong TMaxValue = (1UL << ESize) - 1UL;
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ulong TMinValue = 0UL;
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if (op > (long)TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else if (op < (long)TMinValue)
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{
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SetFpsrQCFlag(State);
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return TMinValue;
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}
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else
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{
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return (ulong)op;
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}
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}
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public static long UnsignedSrcSignedDstSatQ(ulong op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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long TMaxValue = (1L << (ESize - 1)) - 1L;
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if (op > (ulong)TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else
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{
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return (long)op;
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}
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}
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public static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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ulong TMaxValue = (1UL << ESize) - 1UL;
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if (op > TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else
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{
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return op;
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}
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}
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private static void SetFpsrQCFlag(AThreadState State)
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{
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const int QCFlagBit = 27;
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State.Fpsr |= 1 << QCFlagBit;
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}
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#endregion
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#region "Count"
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public static ulong CountLeadingSigns(ulong Value, int Size)
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{
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Value ^= Value >> 1;
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@ -325,7 +342,9 @@ namespace ChocolArm64.Instruction
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|
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return (Value >> 4) + (Value & 0x0f);
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}
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#endregion
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#region "Crc32"
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private const uint Crc32RevPoly = 0xedb88320;
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private const uint Crc32cRevPoly = 0x82f63b78;
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|
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|
@ -384,7 +403,9 @@ namespace ChocolArm64.Instruction
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|
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return Crc;
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}
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#endregion
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#region "Reverse"
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public static uint ReverseBits8(uint Value)
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{
|
||||
Value = ((Value & 0xaa) >> 1) | ((Value & 0x55) << 1);
|
||||
|
@ -453,7 +474,9 @@ namespace ChocolArm64.Instruction
|
|||
|
||||
throw new ArgumentException(nameof(Size));
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "MultiplyHigh"
|
||||
public static long SMulHi128(long LHS, long RHS)
|
||||
{
|
||||
long Result = (long)UMulHi128((ulong)LHS, (ulong)RHS);
|
||||
|
@ -479,5 +502,6 @@ namespace ChocolArm64.Instruction
|
|||
|
||||
return LHigh * RHigh + Z0 + (Z1 >> 32);
|
||||
}
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
<Project Sdk="Microsoft.NET.Sdk">
|
||||
|
||||
<PropertyGroup>
|
||||
<OutputType>Exe</OutputType>
|
||||
<TargetFramework>netcoreapp2.1</TargetFramework>
|
||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||
<OutputType>Exe</OutputType>
|
||||
</PropertyGroup>
|
||||
|
||||
</Project>
|
||||
|
|
|
@ -1,13 +1,13 @@
|
|||
<Project Sdk="Microsoft.NET.Sdk">
|
||||
|
||||
<PropertyGroup>
|
||||
<TargetFramework>netcoreapp2.1</TargetFramework>
|
||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||
<OutputType>Exe</OutputType>
|
||||
</PropertyGroup>
|
||||
|
||||
<ItemGroup>
|
||||
<ProjectReference Include="..\Ryujinx.Graphics\Ryujinx.Graphics.csproj" />
|
||||
</ItemGroup>
|
||||
|
||||
<PropertyGroup>
|
||||
<OutputType>Exe</OutputType>
|
||||
<TargetFramework>netcoreapp2.1</TargetFramework>
|
||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||
</PropertyGroup>
|
||||
|
||||
</Project>
|
||||
|
|
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
using Tester;
|
||||
using Tester.Types;
|
||||
|
||||
[Category("Alu"), Ignore("Tested: first half of 2018.")]
|
||||
[Category("Alu"), Ignore("Tested: second half of 2018.")]
|
||||
public sealed class CpuTestAlu : CpuTest
|
||||
{
|
||||
#if Alu
|
||||
|
|
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
using Tester;
|
||||
using Tester.Types;
|
||||
|
||||
[Category("AluImm"), Ignore("Tested: first half of 2018.")]
|
||||
[Category("AluImm"), Ignore("Tested: second half of 2018.")]
|
||||
public sealed class CpuTestAluImm : CpuTest
|
||||
{
|
||||
#if AluImm
|
||||
|
|
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
using Tester;
|
||||
using Tester.Types;
|
||||
|
||||
[Category("AluRs"), Ignore("Tested: first half of 2018.")]
|
||||
[Category("AluRs"), Ignore("Tested: second half of 2018.")]
|
||||
public sealed class CpuTestAluRs : CpuTest
|
||||
{
|
||||
#if AluRs
|
||||
|
|
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
using Tester;
|
||||
using Tester.Types;
|
||||
|
||||
[Category("AluRx"), Ignore("Tested: first half of 2018.")]
|
||||
[Category("AluRx"), Ignore("Tested: second half of 2018.")]
|
||||
public sealed class CpuTestAluRx : CpuTest
|
||||
{
|
||||
#if AluRx
|
||||
|
|
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
using Tester;
|
||||
using Tester.Types;
|
||||
|
||||
[Category("Bfm"), Ignore("Tested: first half of 2018.")]
|
||||
[Category("Bfm"), Ignore("Tested: second half of 2018.")]
|
||||
public sealed class CpuTestBfm : CpuTest
|
||||
{
|
||||
#if Bfm
|
||||
|
|
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
using Tester;
|
||||
using Tester.Types;
|
||||
|
||||
[Category("CcmpImm"), Ignore("Tested: first half of 2018.")]
|
||||
[Category("CcmpImm"), Ignore("Tested: second half of 2018.")]
|
||||
public sealed class CpuTestCcmpImm : CpuTest
|
||||
{
|
||||
#if CcmpImm
|
||||
|
|
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
using Tester;
|
||||
using Tester.Types;
|
||||
|
||||
[Category("CcmpReg"), Ignore("Tested: first half of 2018.")]
|
||||
[Category("CcmpReg"), Ignore("Tested: second half of 2018.")]
|
||||
public sealed class CpuTestCcmpReg : CpuTest
|
||||
{
|
||||
#if CcmpReg
|
||||
|
|
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
using Tester;
|
||||
using Tester.Types;
|
||||
|
||||
[Category("Csel"), Ignore("Tested: first half of 2018.")]
|
||||
[Category("Csel"), Ignore("Tested: second half of 2018.")]
|
||||
public sealed class CpuTestCsel : CpuTest
|
||||
{
|
||||
#if Csel
|
||||
|
|
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
using Tester;
|
||||
using Tester.Types;
|
||||
|
||||
[Category("Mov"), Ignore("Tested: first half of 2018.")]
|
||||
[Category("Mov"), Ignore("Tested: second half of 2018.")]
|
||||
public sealed class CpuTestMov : CpuTest
|
||||
{
|
||||
#if Mov
|
||||
|
|
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
using Tester;
|
||||
using Tester.Types;
|
||||
|
||||
[Category("Mul"), Ignore("Tested: first half of 2018.")]
|
||||
[Category("Mul"), Ignore("Tested: second half of 2018.")]
|
||||
public sealed class CpuTestMul : CpuTest
|
||||
{
|
||||
#if Mul
|
||||
|
|
|
@ -39,6 +39,21 @@ namespace Ryujinx.Tests.Cpu
|
|||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _1H1S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x0000000000007FFFul,
|
||||
0x0000000000008000ul, 0x000000000000FFFFul,
|
||||
0x000000007FFFFFFFul, 0x0000000080000000ul,
|
||||
0x00000000FFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _4H2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _4H2S1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
|
@ -1837,6 +1852,216 @@ namespace Ryujinx.Tests.Cpu
|
|||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQDMULH <V><d>, <V><n>, <V><m>")]
|
||||
public void Sqdmulh_S_H_S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_1H1S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1H1S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_1H1S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b01u, 0b10u)] uint size) // <H, S>
|
||||
{
|
||||
uint Opcode = 0x5E20B400; // SQDMULH B0, B0, B0 (RESERVED)
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqdmulh_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Sqdmulh_V_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b01u, 0b10u)] uint size) // <4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x0E20B400; // SQDMULH V0.8B, V0.8B, V0.8B (RESERVED)
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Sqdmulh_V_8H_4S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b01u, 0b10u)] uint size) // <8H, 4S>
|
||||
{
|
||||
uint Opcode = 0x4E20B400; // SQDMULH V0.16B, V0.16B, V0.16B (RESERVED)
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQRDMULH <V><d>, <V><n>, <V><m>")]
|
||||
public void Sqrdmulh_S_H_S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_1H1S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1H1S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_1H1S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b01u, 0b10u)] uint size) // <H, S>
|
||||
{
|
||||
uint Opcode = 0x7E20B400; // SQRDMULH B0, B0, B0 (RESERVED)
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqrdmulh_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Sqrdmulh_V_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b01u, 0b10u)] uint size) // <4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x2E20B400; // SQRDMULH V0.8B, V0.8B, V0.8B (RESERVED)
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqrdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Sqrdmulh_V_8H_4S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b01u, 0b10u)] uint size) // <8H, 4S>
|
||||
{
|
||||
uint Opcode = 0x6E20B400; // SQRDMULH V0.16B, V0.16B, V0.16B (RESERVED)
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqrdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQSUB <V><d>, <V><n>, <V><m>")]
|
||||
public void Sqsub_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
|
|
|
@ -5075,6 +5075,210 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// sqdmulh_advsimd_vec.html#SQDMULH_asisdsame_only
|
||||
public static void Sqdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode Scalar */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' || size == '00' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = esize;
|
||||
int elements = 1;
|
||||
|
||||
bool rounding = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger product;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = SInt(Elem(operand1, e, esize));
|
||||
element2 = SInt(Elem(operand2, e, esize));
|
||||
|
||||
product = (2 * element1 * element2) + round_const;
|
||||
|
||||
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqdmulh_advsimd_vec.html#SQDMULH_asimdsame_only
|
||||
public static void Sqdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' || size == '00' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool rounding = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger product;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = SInt(Elem(operand1, e, esize));
|
||||
element2 = SInt(Elem(operand2, e, esize));
|
||||
|
||||
product = (2 * element1 * element2) + round_const;
|
||||
|
||||
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqrdmulh_advsimd_vec.html#SQRDMULH_asisdsame_only
|
||||
public static void Sqrdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode Scalar */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' || size == '00' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = esize;
|
||||
int elements = 1;
|
||||
|
||||
bool rounding = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger product;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = SInt(Elem(operand1, e, esize));
|
||||
element2 = SInt(Elem(operand2, e, esize));
|
||||
|
||||
product = (2 * element1 * element2) + round_const;
|
||||
|
||||
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqrdmulh_advsimd_vec.html#SQRDMULH_asimdsame_only
|
||||
public static void Sqrdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' || size == '00' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool rounding = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger product;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = SInt(Elem(operand1, e, esize));
|
||||
element2 = SInt(Elem(operand2, e, esize));
|
||||
|
||||
product = (2 * element1 * element2) + round_const;
|
||||
|
||||
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqsub_advsimd.html#SQSUB_asisdsame_only
|
||||
public static void Sqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
|
@ -1,20 +1,25 @@
|
|||
<Project Sdk="Microsoft.NET.Sdk">
|
||||
<Project Sdk="Microsoft.NET.Sdk">
|
||||
|
||||
<PropertyGroup>
|
||||
<TargetFramework>netcoreapp2.1</TargetFramework>
|
||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||
<OutputType>Exe</OutputType>
|
||||
<IsPackable>false</IsPackable>
|
||||
</PropertyGroup>
|
||||
|
||||
<PropertyGroup>
|
||||
<GenerateAssemblyInfo>false</GenerateAssemblyInfo>
|
||||
</PropertyGroup>
|
||||
|
||||
<ItemGroup>
|
||||
<PackageReference Include="Microsoft.NET.Test.Sdk" Version="15.7.0" />
|
||||
<PackageReference Include="Microsoft.NET.Test.Sdk" Version="15.8.0" />
|
||||
<PackageReference Include="NUnit" Version="3.10.1" />
|
||||
<PackageReference Include="NUnit3TestAdapter" Version="3.10.0" />
|
||||
<PackageReference Include="System.Runtime.Intrinsics.Experimental" Version="4.5.0-rc1" />
|
||||
</ItemGroup>
|
||||
|
||||
<ItemGroup>
|
||||
<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
|
||||
</ItemGroup>
|
||||
|
||||
</Project>
|
||||
|
|
|
@ -1,23 +1,28 @@
|
|||
<Project Sdk="Microsoft.NET.Sdk">
|
||||
<Project Sdk="Microsoft.NET.Sdk">
|
||||
|
||||
<PropertyGroup>
|
||||
<OutputType>Exe</OutputType>
|
||||
<TargetFramework>netcoreapp2.1</TargetFramework>
|
||||
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
|
||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||
<OutputType>Exe</OutputType>
|
||||
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
|
||||
</PropertyGroup>
|
||||
|
||||
<ItemGroup>
|
||||
<PackageReference Include="OpenTK.NetStandard" Version="1.0.4" />
|
||||
<PackageReference Include="System.Runtime.CompilerServices.Unsafe" Version="4.4.0" />
|
||||
</ItemGroup>
|
||||
|
||||
<ItemGroup>
|
||||
<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
|
||||
<ProjectReference Include="..\Ryujinx.Audio\Ryujinx.Audio.csproj" />
|
||||
<ProjectReference Include="..\Ryujinx.HLE\Ryujinx.HLE.csproj" />
|
||||
<ProjectReference Include="..\Ryujinx.Graphics\Ryujinx.Graphics.csproj" />
|
||||
<ProjectReference Include="..\Ryujinx.HLE\Ryujinx.HLE.csproj" />
|
||||
</ItemGroup>
|
||||
|
||||
<ItemGroup>
|
||||
<None Update="Ryujinx.conf">
|
||||
<CopyToOutputDirectory>PreserveNewest</CopyToOutputDirectory>
|
||||
</None>
|
||||
</ItemGroup>
|
||||
|
||||
</Project>
|
Loading…
Reference in a new issue