mirror of
https://github.com/GreemDev/Ryujinx.git
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Implement SQSHL (immediate) CPU instruction (#6155)
* Implement SQSHL (immediate) CPU instruction * Fix test
This commit is contained in:
parent
6575952432
commit
2ca70eb9a0
4 changed files with 260 additions and 1 deletions
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@ -517,7 +517,10 @@ namespace ARMeilleure.Decoders
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SetA64("0x00111100>>>xxx100111xxxxxxxxxx", InstName.Sqrshrn_V, InstEmit.Sqrshrn_V, OpCodeSimdShImm.Create);
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SetA64("0x00111100>>>xxx100111xxxxxxxxxx", InstName.Sqrshrn_V, InstEmit.Sqrshrn_V, OpCodeSimdShImm.Create);
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SetA64("0111111100>>>xxx100011xxxxxxxxxx", InstName.Sqrshrun_S, InstEmit.Sqrshrun_S, OpCodeSimdShImm.Create);
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SetA64("0111111100>>>xxx100011xxxxxxxxxx", InstName.Sqrshrun_S, InstEmit.Sqrshrun_S, OpCodeSimdShImm.Create);
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SetA64("0x10111100>>>xxx100011xxxxxxxxxx", InstName.Sqrshrun_V, InstEmit.Sqrshrun_V, OpCodeSimdShImm.Create);
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SetA64("0x10111100>>>xxx100011xxxxxxxxxx", InstName.Sqrshrun_V, InstEmit.Sqrshrun_V, OpCodeSimdShImm.Create);
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SetA64("010111110>>>>xxx011101xxxxxxxxxx", InstName.Sqshl_Si, InstEmit.Sqshl_Si, OpCodeSimdShImm.Create);
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SetA64("0>001110<<1xxxxx010011xxxxxxxxxx", InstName.Sqshl_V, InstEmit.Sqshl_V, OpCodeSimdReg.Create);
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SetA64("0>001110<<1xxxxx010011xxxxxxxxxx", InstName.Sqshl_V, InstEmit.Sqshl_V, OpCodeSimdReg.Create);
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SetA64("0000111100>>>xxx011101xxxxxxxxxx", InstName.Sqshl_Vi, InstEmit.Sqshl_Vi, OpCodeSimdShImm.Create);
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SetA64("010011110>>>>xxx011101xxxxxxxxxx", InstName.Sqshl_Vi, InstEmit.Sqshl_Vi, OpCodeSimdShImm.Create);
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SetA64("0101111100>>>xxx100101xxxxxxxxxx", InstName.Sqshrn_S, InstEmit.Sqshrn_S, OpCodeSimdShImm.Create);
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SetA64("0101111100>>>xxx100101xxxxxxxxxx", InstName.Sqshrn_S, InstEmit.Sqshrn_S, OpCodeSimdShImm.Create);
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SetA64("0x00111100>>>xxx100101xxxxxxxxxx", InstName.Sqshrn_V, InstEmit.Sqshrn_V, OpCodeSimdShImm.Create);
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SetA64("0x00111100>>>xxx100101xxxxxxxxxx", InstName.Sqshrn_V, InstEmit.Sqshrn_V, OpCodeSimdShImm.Create);
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SetA64("0111111100>>>xxx100001xxxxxxxxxx", InstName.Sqshrun_S, InstEmit.Sqshrun_S, OpCodeSimdShImm.Create);
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SetA64("0111111100>>>xxx100001xxxxxxxxxx", InstName.Sqshrun_S, InstEmit.Sqshrun_S, OpCodeSimdShImm.Create);
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@ -116,7 +116,7 @@ namespace ARMeilleure.Instructions
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}
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}
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else if (shift >= eSize)
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else if (shift >= eSize)
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{
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{
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if ((op.RegisterSize == RegisterSize.Simd64))
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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{
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Operand res = context.VectorZeroUpper64(GetVec(op.Rd));
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Operand res = context.VectorZeroUpper64(GetVec(op.Rd));
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@ -359,6 +359,16 @@ namespace ARMeilleure.Instructions
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}
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}
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}
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}
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public static void Sqshl_Si(ArmEmitterContext context)
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{
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EmitShlImmOp(context, signedDst: true, ShlRegFlags.Signed | ShlRegFlags.Scalar | ShlRegFlags.Saturating);
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}
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public static void Sqshl_Vi(ArmEmitterContext context)
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{
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EmitShlImmOp(context, signedDst: true, ShlRegFlags.Signed | ShlRegFlags.Saturating);
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}
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public static void Sqshrn_S(ArmEmitterContext context)
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public static void Sqshrn_S(ArmEmitterContext context)
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{
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{
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if (Optimizations.UseAdvSimd)
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if (Optimizations.UseAdvSimd)
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@ -1593,6 +1603,99 @@ namespace ARMeilleure.Instructions
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Saturating = 1 << 3,
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Saturating = 1 << 3,
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}
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}
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private static void EmitShlImmOp(ArmEmitterContext context, bool signedDst, ShlRegFlags flags = ShlRegFlags.None)
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{
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bool scalar = flags.HasFlag(ShlRegFlags.Scalar);
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bool signed = flags.HasFlag(ShlRegFlags.Signed);
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bool saturating = flags.HasFlag(ShlRegFlags.Saturating);
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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Operand res = context.VectorZero();
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int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, signed);
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Operand e = !saturating
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? EmitShlImm(context, ne, GetImmShl(op), op.Size)
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: EmitShlImmSatQ(context, ne, GetImmShl(op), op.Size, signed, signedDst);
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res = EmitVectorInsert(context, res, e, index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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private static Operand EmitShlImm(ArmEmitterContext context, Operand op, int shiftLsB, int size)
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{
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int eSize = 8 << size;
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Debug.Assert(op.Type == OperandType.I64);
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Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
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Operand res = context.AllocateLocal(OperandType.I64);
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if (shiftLsB >= eSize)
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{
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Operand shl = context.ShiftLeft(op, Const(shiftLsB));
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context.Copy(res, shl);
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}
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else
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{
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Operand zeroL = Const(0L);
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context.Copy(res, zeroL);
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}
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return res;
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}
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private static Operand EmitShlImmSatQ(ArmEmitterContext context, Operand op, int shiftLsB, int size, bool signedSrc, bool signedDst)
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{
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int eSize = 8 << size;
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Debug.Assert(op.Type == OperandType.I64);
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Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
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Operand lblEnd = Label();
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Operand res = context.Copy(context.AllocateLocal(OperandType.I64), op);
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if (shiftLsB >= eSize)
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{
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context.Copy(res, signedSrc
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? EmitSignedSignSatQ(context, op, size)
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: EmitUnsignedSignSatQ(context, op, size));
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}
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else
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{
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Operand shl = context.ShiftLeft(op, Const(shiftLsB));
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if (eSize == 64)
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{
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Operand sarOrShr = signedSrc
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? context.ShiftRightSI(shl, Const(shiftLsB))
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: context.ShiftRightUI(shl, Const(shiftLsB));
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context.Copy(res, shl);
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context.BranchIf(lblEnd, sarOrShr, op, Comparison.Equal);
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context.Copy(res, signedSrc
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? EmitSignedSignSatQ(context, op, size)
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: EmitUnsignedSignSatQ(context, op, size));
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}
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else
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{
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context.Copy(res, signedSrc
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? EmitSignedSrcSatQ(context, shl, size, signedDst)
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: EmitUnsignedSrcSatQ(context, shl, size, signedDst));
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}
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}
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context.MarkLabel(lblEnd);
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return res;
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}
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private static void EmitShlRegOp(ArmEmitterContext context, ShlRegFlags flags = ShlRegFlags.None)
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private static void EmitShlRegOp(ArmEmitterContext context, ShlRegFlags flags = ShlRegFlags.None)
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{
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{
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bool scalar = flags.HasFlag(ShlRegFlags.Scalar);
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bool scalar = flags.HasFlag(ShlRegFlags.Scalar);
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@ -384,7 +384,9 @@ namespace ARMeilleure.Instructions
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Sqrshrn_V,
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Sqrshrn_V,
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Sqrshrun_S,
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Sqrshrun_S,
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Sqrshrun_V,
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Sqrshrun_V,
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Sqshl_Si,
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Sqshl_V,
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Sqshl_V,
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Sqshl_Vi,
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Sqshrn_S,
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Sqshrn_S,
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Sqshrn_V,
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Sqshrn_V,
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Sqshrun_S,
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Sqshrun_S,
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@ -311,6 +311,46 @@ namespace Ryujinx.Tests.Cpu
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};
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};
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}
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}
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private static uint[] _ShlImm_S_D_()
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{
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return new[]
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{
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0x5F407400u, // SQSHL D0, D0, #0
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};
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}
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private static uint[] _ShlImm_V_8B_16B_()
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{
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return new[]
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{
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0x0F087400u, // SQSHL V0.8B, V0.8B, #0
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};
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}
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private static uint[] _ShlImm_V_4H_8H_()
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{
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return new[]
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{
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0x0F107400u, // SQSHL V0.4H, V0.4H, #0
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};
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}
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private static uint[] _ShlImm_V_2S_4S_()
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{
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return new[]
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{
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0x0F207400u, // SQSHL V0.2S, V0.2S, #0
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};
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}
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private static uint[] _ShlImm_V_2D_()
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{
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return new[]
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{
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0x4F407400u, // SQSHL V0.2D, V0.2D, #0
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};
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}
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private static uint[] _ShrImm_Sri_S_D_()
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private static uint[] _ShrImm_Sri_S_D_()
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{
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{
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return new[]
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return new[]
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@ -813,6 +853,117 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Test, Pairwise]
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public void ShlImm_S_D([ValueSource(nameof(_ShlImm_S_D_))] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource(nameof(_1D_))] ulong z,
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[ValueSource(nameof(_1D_))] ulong a,
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[Values(1u, 64u)] uint shift)
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{
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uint immHb = (64 + shift) & 0x7F;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0(a);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void ShlImm_V_8B_16B([ValueSource(nameof(_ShlImm_V_8B_16B_))] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource(nameof(_8B_))] ulong z,
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[ValueSource(nameof(_8B_))] ulong a,
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[Values(1u, 8u)] uint shift,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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uint immHb = (8 + shift) & 0x7F;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a * q);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void ShlImm_V_4H_8H([ValueSource(nameof(_ShlImm_V_4H_8H_))] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource(nameof(_4H_))] ulong z,
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[ValueSource(nameof(_4H_))] ulong a,
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[Values(1u, 16u)] uint shift,
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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uint immHb = (16 + shift) & 0x7F;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a * q);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void ShlImm_V_2S_4S([ValueSource(nameof(_ShlImm_V_2S_4S_))] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource(nameof(_2S_))] ulong z,
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[ValueSource(nameof(_2S_))] ulong a,
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[Values(1u, 32u)] uint shift,
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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uint immHb = (32 + shift) & 0x7F;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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opcodes |= (((q | (immHb >> 6)) & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a * q);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void ShlImm_V_2D([ValueSource(nameof(_ShlImm_V_2D_))] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource(nameof(_1D_))] ulong z,
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[ValueSource(nameof(_1D_))] ulong a,
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[Values(1u, 64u)] uint shift)
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{
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uint immHb = (64 + shift) & 0x7F;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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[Test, Pairwise]
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public void ShrImm_Sri_S_D([ValueSource(nameof(_ShrImm_Sri_S_D_))] uint opcodes,
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public void ShrImm_Sri_S_D([ValueSource(nameof(_ShrImm_Sri_S_D_))] uint opcodes,
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[Values(0u)] uint rd,
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[Values(0u)] uint rd,
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