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SPIR-V: Change BitfieldExtract and BitfieldInsert for SPIRV-Cross (#4336)
* SPIR-V: Change BitfieldExtract and BitfieldInsert types to make Metal MSL compiler happy * Shader cache version bump
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2 changed files with 27 additions and 27 deletions
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@ -22,7 +22,7 @@ namespace Ryujinx.Graphics.Gpu.Shader.DiskCache
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private const ushort FileFormatVersionMajor = 1;
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private const ushort FileFormatVersionMinor = 2;
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private const uint FileFormatVersionPacked = ((uint)FileFormatVersionMajor << 16) | FileFormatVersionMinor;
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private const uint CodeGenVersion = 4318;
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private const uint CodeGenVersion = 4336;
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private const string SharedTocFileName = "shared.toc";
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private const string SharedDataFileName = "shared.data";
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@ -261,17 +261,17 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
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private static OperationResult GenerateBitfieldExtractS32(CodeGenContext context, AstOperation operation)
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{
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return GenerateTernaryS32(context, operation, context.Delegates.BitFieldSExtract);
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return GenerateBitfieldExtractS32(context, operation, context.Delegates.BitFieldSExtract);
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}
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private static OperationResult GenerateBitfieldExtractU32(CodeGenContext context, AstOperation operation)
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{
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return GenerateTernaryS32(context, operation, context.Delegates.BitFieldUExtract);
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return GenerateTernaryU32(context, operation, context.Delegates.BitFieldUExtract);
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}
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private static OperationResult GenerateBitfieldInsert(CodeGenContext context, AstOperation operation)
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{
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return GenerateQuaternaryS32(context, operation, context.Delegates.BitFieldInsert);
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return GenerateBitfieldInsert(context, operation, context.Delegates.BitFieldInsert);
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}
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private static OperationResult GenerateBitfieldReverse(CodeGenContext context, AstOperation operation)
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@ -2290,22 +2290,6 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
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}
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}
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private static OperationResult GenerateTernaryS32(
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CodeGenContext context,
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AstOperation operation,
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Func<SpvInstruction, SpvInstruction, SpvInstruction, SpvInstruction, SpvInstruction> emitS)
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{
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var src1 = operation.GetSource(0);
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var src2 = operation.GetSource(1);
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var src3 = operation.GetSource(2);
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return new OperationResult(AggregateType.S32, emitS(
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context.TypeS32(),
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context.GetS32(src1),
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context.GetS32(src2),
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context.GetS32(src3)));
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}
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private static OperationResult GenerateTernaryU32(
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CodeGenContext context,
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AstOperation operation,
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@ -2322,7 +2306,23 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
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context.GetU32(src3)));
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}
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private static OperationResult GenerateQuaternaryS32(
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private static OperationResult GenerateBitfieldExtractS32(
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CodeGenContext context,
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AstOperation operation,
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Func<SpvInstruction, SpvInstruction, SpvInstruction, SpvInstruction, SpvInstruction> emitS)
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{
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var src1 = operation.GetSource(0);
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var src2 = operation.GetSource(1);
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var src3 = operation.GetSource(2);
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return new OperationResult(AggregateType.S32, emitS(
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context.TypeS32(),
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context.GetS32(src1),
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context.GetU32(src2),
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context.GetU32(src3)));
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}
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private static OperationResult GenerateBitfieldInsert(
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CodeGenContext context,
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AstOperation operation,
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Func<SpvInstruction, SpvInstruction, SpvInstruction, SpvInstruction, SpvInstruction, SpvInstruction> emitS)
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@ -2332,12 +2332,12 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
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var src3 = operation.GetSource(2);
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var src4 = operation.GetSource(3);
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return new OperationResult(AggregateType.S32, emitS(
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context.TypeS32(),
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context.GetS32(src1),
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context.GetS32(src2),
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context.GetS32(src3),
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context.GetS32(src4)));
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return new OperationResult(AggregateType.U32, emitS(
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context.TypeU32(),
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context.GetU32(src1),
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context.GetU32(src2),
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context.GetU32(src3),
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context.GetU32(src4)));
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}
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}
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}
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