emu-mirrors/Ryujinx
0
0
Fork 0
mirror of https://github.com/GreemDev/Ryujinx.git synced 2024-12-23 06:55:48 +00:00
Code Wiki Activity

Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. (#88)

Browse source 
* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update AOpCodeTable.cs
This commit is contained in:
LDj3SNuD 2018-04-18 15:56:27 +02:00 committed by gdkchan
parent 7450b9d68a
commit 8b75080639
2 changed files with 40 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
ChocolArm64/AOpCodeTable.cs
View file

@ -133,6 +133,9 @@ namespace ChocolArm64
Set("10011011110xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Umulh, typeof(AOpCodeMul));
//Vector
Set("0101111011100000101110xxxxxxxxxx", AInstEmit.Abs_S, typeof(AOpCodeSimd));
Set("0>001110<<100000101110xxxxxxxxxx", AInstEmit.Abs_V, typeof(AOpCodeSimd));
Set("01011110111xxxxx100001xxxxxxxxxx", AInstEmit.Add_S, typeof(AOpCodeSimdReg));
Set("0>001110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Add_V, typeof(AOpCodeSimdReg));
Set("01011110xx110001101110xxxxxxxxxx", AInstEmit.Addp_S, typeof(AOpCodeSimd));
Set("0>001110<<1xxxxx101111xxxxxxxxxx", AInstEmit.Addp_V, typeof(AOpCodeSimdReg));
@ -280,7 +283,8 @@ namespace ChocolArm64
Set("0x10111100000xxx0xx001xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm));
Set("0x10111100000xxx10x001xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm));
Set("0x10111100000xxx110x01xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm));
Set("0>101110<<100000101110xxxxxxxxxx", AInstEmit.Neg_V, typeof(AOpCodeSimdReg));
Set("0111111011100000101110xxxxxxxxxx", AInstEmit.Neg_S, typeof(AOpCodeSimd));
Set("0>101110<<100000101110xxxxxxxxxx", AInstEmit.Neg_V, typeof(AOpCodeSimd));
Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd));
Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg));
Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm));
@ -313,7 +317,7 @@ namespace ChocolArm64
Set("xx111100x00xxxxxxxxx11xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm));
Set("xx111101x0xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm));
Set("xx111100x01xxxxxxxxx10xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemReg));
Set("01111110xx1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_S, typeof(AOpCodeSimdReg));
Set("01111110111xxxxx100001xxxxxxxxxx", AInstEmit.Sub_S, typeof(AOpCodeSimdReg));
Set("0>101110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_V, typeof(AOpCodeSimdReg));
Set("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl));
Set("0>001110<<0xxxxx001010xxxxxxxxxx", AInstEmit.Trn1_V, typeof(AOpCodeSimdReg));

34
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -11,6 +11,35 @@ namespace ChocolArm64.Instruction
{
static partial class AInstEmit
{
public static void Abs_S(AILEmitterCtx Context)
{
EmitScalarUnaryOpSx(Context, () => EmitAbs(Context));
}
public static void Abs_V(AILEmitterCtx Context)
{
EmitVectorUnaryOpSx(Context, () => EmitAbs(Context));
}
private static void EmitAbs(AILEmitterCtx Context)
{
AILLabel LblTrue = new AILLabel();
Context.Emit(OpCodes.Dup);
Context.Emit(OpCodes.Ldc_I4_0);
Context.Emit(OpCodes.Bge_S, LblTrue);
Context.Emit(OpCodes.Neg);
Context.MarkLabel(LblTrue);
}
public static void Add_S(AILEmitterCtx Context)
{
EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
}
public static void Add_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
@ -738,6 +767,11 @@ namespace ChocolArm64.Instruction
EmitVectorBinaryOpByElemZx(Context, () => Context.Emit(OpCodes.Mul));
}
public static void Neg_S(AILEmitterCtx Context)
{
EmitScalarUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
}
public static void Neg_V(AILEmitterCtx Context)
{
EmitVectorUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));