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https://github.com/GreemDev/Ryujinx.git
synced 2024-12-23 03:25:46 +00:00
Implement shader LEA instruction and improve bindless image load/store (#1355)
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parent
76e5af967a
commit
e13154c83d
7 changed files with 82 additions and 43 deletions
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@ -4,12 +4,12 @@ namespace Ryujinx.Graphics.Shader.Decoders
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{
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public static bool Extract(this int value, int lsb)
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{
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return ((int)(value >> lsb) & 1) != 0;
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return ((value >> lsb) & 1) != 0;
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}
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public static int Extract(this int value, int lsb, int length)
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{
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return (int)(value >> lsb) & (int)(uint.MaxValue >> (32 - length));
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return (value >> lsb) & (int)(uint.MaxValue >> (32 - length));
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}
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public static bool Extract(this long value, int lsb)
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@ -176,6 +176,9 @@ namespace Ryujinx.Graphics.Shader.Decoders
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Set("1110111110010x", InstEmit.Ldc, typeof(OpCodeLdc));
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Set("1110111011010x", InstEmit.Ldg, typeof(OpCodeMemory));
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Set("1110111101001x", InstEmit.Lds, typeof(OpCodeMemory));
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Set("010010111101xx", InstEmit.Lea, typeof(OpCodeAluCbuf));
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Set("0011011x11010x", InstEmit.Lea, typeof(OpCodeAluImm));
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Set("0101101111010x", InstEmit.Lea, typeof(OpCodeAluReg));
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Set("0100110001000x", InstEmit.Lop, typeof(OpCodeLopCbuf));
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Set("0011100001000x", InstEmit.Lop, typeof(OpCodeLopImm));
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Set("000001xxxxxxxx", InstEmit.Lop, typeof(OpCodeLopImm32));
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@ -384,6 +384,27 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Copy(Register(op.Predicate0), p1Res);
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}
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public static void Lea(EmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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bool negateA = op.RawOpCode.Extract(45);
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int shift = op.RawOpCode.Extract(39, 5);
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Operand srcA = GetSrcA(context);
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Operand srcB = GetSrcB(context);
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srcA = context.ShiftLeft(srcA, Const(shift));
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srcA = context.INegate(srcA, negateA);
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Operand res = context.IAdd(srcA, srcB);
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context.Copy(GetDest(context), res);
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// TODO: CC, X
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}
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public static void Lop(EmitterContext context)
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{
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IOpCodeLop op = (IOpCodeLop)context.CurrOp;
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@ -99,7 +99,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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if (!op.IsBindless)
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{
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operation.Format = GetTextureFormat(context, handle);
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operation.Format = context.Config.GetTextureFormat(handle);
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}
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context.Add(operation);
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@ -228,7 +228,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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if (!op.IsBindless)
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{
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format = GetTextureFormat(context, op.Immediate);
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format = context.Config.GetTextureFormat(op.Immediate);
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}
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}
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else
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@ -1223,27 +1223,6 @@ namespace Ryujinx.Graphics.Shader.Instructions
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};
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}
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private static TextureFormat GetTextureFormat(EmitterContext context, int handle)
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{
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// When the formatted load extension is supported, we don't need to
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// specify a format, we can just declare it without a format and the GPU will handle it.
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if (context.Config.GpuAccessor.QuerySupportsImageLoadFormatted())
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{
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return TextureFormat.Unknown;
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}
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var format = context.Config.GpuAccessor.QueryTextureFormat(handle);
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if (format == TextureFormat.Unknown)
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{
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context.Config.GpuAccessor.Log($"Unknown format for texture {handle}.");
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format = TextureFormat.R8G8B8A8Unorm;
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}
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return format;
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}
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private static TextureFormat GetTextureFormat(IntegerSize size)
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{
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return size switch
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@ -5,7 +5,9 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
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{
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class BindlessElimination
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{
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public static void RunPass(BasicBlock block)
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private const int NvnTextureBufferSlot = 2;
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public static void RunPass(BasicBlock block, ShaderConfig config)
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{
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// We can turn a bindless into regular access by recognizing the pattern
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// produced by the compiler for separate texture and sampler.
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@ -24,26 +26,39 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
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continue;
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}
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if (!(texOp.GetSource(0).AsgOp is Operation handleCombineOp))
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if (texOp.Inst == Instruction.TextureSample)
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{
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continue;
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}
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if (!(texOp.GetSource(0).AsgOp is Operation handleCombineOp))
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{
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continue;
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}
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if (handleCombineOp.Inst != Instruction.BitwiseOr)
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if (handleCombineOp.Inst != Instruction.BitwiseOr)
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{
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continue;
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}
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Operand src0 = handleCombineOp.GetSource(0);
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Operand src1 = handleCombineOp.GetSource(1);
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if (src0.Type != OperandType.ConstantBuffer || src0.GetCbufSlot() != NvnTextureBufferSlot ||
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src1.Type != OperandType.ConstantBuffer || src1.GetCbufSlot() != NvnTextureBufferSlot)
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{
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continue;
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}
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texOp.SetHandle(src0.GetCbufOffset() | (src1.GetCbufOffset() << 16));
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}
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else if (texOp.Inst == Instruction.ImageLoad || texOp.Inst == Instruction.ImageStore)
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{
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continue;
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Operand src0 = texOp.GetSource(0);
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if (src0.Type == OperandType.ConstantBuffer && src0.GetCbufSlot() == NvnTextureBufferSlot)
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{
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texOp.SetHandle(src0.GetCbufOffset());
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texOp.Format = config.GetTextureFormat(texOp.Handle);
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}
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}
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Operand src0 = handleCombineOp.GetSource(0);
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Operand src1 = handleCombineOp.GetSource(1);
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if (src0.Type != OperandType.ConstantBuffer || src0.GetCbufSlot() != 2 ||
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src1.Type != OperandType.ConstantBuffer || src1.GetCbufSlot() != 2)
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{
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continue;
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}
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texOp.SetHandle(src0.GetCbufOffset() | (src1.GetCbufOffset() << 16));
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}
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}
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}
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@ -89,7 +89,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
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for (int blkIndex = 0; blkIndex < blocks.Length; blkIndex++)
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{
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BindlessToIndexed.RunPass(blocks[blkIndex]);
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BindlessElimination.RunPass(blocks[blkIndex]);
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BindlessElimination.RunPass(blocks[blkIndex], config);
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// Try to eliminate any operations that are now unused.
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LinkedListNode<INode> node = blocks[blkIndex].Operations.First;
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@ -68,5 +68,26 @@ namespace Ryujinx.Graphics.Shader.Translation
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// The depth register is always two registers after the last color output.
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return count + 1;
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}
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public TextureFormat GetTextureFormat(int handle)
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{
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// When the formatted load extension is supported, we don't need to
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// specify a format, we can just declare it without a format and the GPU will handle it.
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if (GpuAccessor.QuerySupportsImageLoadFormatted())
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{
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return TextureFormat.Unknown;
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}
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var format = GpuAccessor.QueryTextureFormat(handle);
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if (format == TextureFormat.Unknown)
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{
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GpuAccessor.Log($"Unknown format for texture {handle}.");
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format = TextureFormat.R8G8B8A8Unorm;
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}
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return format;
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}
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}
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}
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