Alex Barney
9cb57fb4bb
Adjust naming conventions for Ryujinx and ChocolArm64 projects ( #484 )
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* Change naming convention for Ryujinx project
* Change naming convention for ChocolArm64 project
* Fix NaN
* Remove unneeded this. from Ryujinx project
* Adjust naming from new PRs
* Name changes based on feedback
* How did this get removed?
* Rebasing fix
* Change FP enum case
* Remove prefix from ChocolArm64 classes - Part 1
* Remove prefix from ChocolArm64 classes - Part 2
* Fix alignment from last commit's renaming
* Rename namespaces
* Rename stragglers
* Fix alignment
* Rename OpCode class
* Missed a few
* Adjust alignment
2018-10-30 22:43:02 -03:00
LDj3SNuD
e674b37710
Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. ( #468 )
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* Update CpuTest.cs
* Update CpuTestSimd.cs
* Superseded.
* Update AInstEmitSimdCvt.cs
* Update ASoftFloat.cs
* Nit.
* Update PackageReferences.
* Update AInstEmitSimdArithmetic.cs
* Update AVectorHelper.cs
* Update ASoftFloat.cs
* Update ASoftFallback.cs
* Update AThreadState.cs
* Create FPType.cs
* Create FPExc.cs
* Create FPCR.cs
* Create FPSR.cs
* Update ARoundMode.cs
* Update APState.cs
* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.
* Nits.
2018-10-23 11:12:45 -03:00
gdkchan
0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics ( #405 )
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* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements
* Remove useless space
* Address PR feedback
* Revert EmitVectorZero32_128 changes
2018-09-26 23:30:21 -03:00
gdkchan
55374ebba0
Zero out bits 63:32 of scalar float operations with SSE intrinsics ( #273 )
2018-08-14 23:54:12 -03:00
gdkchan
221270db90
More accurate impl of FMINNM/FMAXNM, add vector variants ( #296 )
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* More accurate impl of FMINNM/FMAXNM, add vector variants
* Optimize for the 0 case when op1 != op2
* Address PR feedback
2018-08-05 02:54:21 -03:00
LDj3SNuD
c228cf320d
Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. ( #212 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdLogical.cs
* Update AVectorHelper.cs
* Update ASoftFallback.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Improve CountSetBits8() algorithm.
* Improve CountSetBits8() algorithm.
2018-07-03 03:31:16 -03:00
gdkchan
4c7c21634e
Add Sse2 fallback to Vector{Extract|Insert}Single methods on the CPU ( #193 )
2018-06-28 20:52:32 -03:00
gdkchan
f9f111bc85
Add intrinsics support ( #121 )
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* Initial intrinsics support
* Update tests to work with the new Vector128 type and intrinsics
* Drop SSE4.1 requirement
* Fix copy-paste mistake
2018-05-11 20:10:27 -03:00
