mirror of
https://github.com/GreemDev/Ryujinx.git
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36e8e074c9
* Fix and simplify TranslatorCache * Fix some assignment alignments, remove some unused usings * Changes to ILEmitter, separate it from ILEmitterCtx * Rename ILEmitter to ILMethodBuilder * Rename LdrLit and *_Fix opcodes * Revert TranslatorCache impl to the more performant one, fix a few issues with it * Allow EmitOpCode to be called even after everything has been emitted * Make Emit and AdvanceOpCode private, simplify it a bit now that it starts emiting from the entry point * Remove unneeded temp use * Add missing exit call on TestExclusive * Use better hash * Implement the == and != operators
48 lines
No EOL
1.4 KiB
C#
48 lines
No EOL
1.4 KiB
C#
using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCodeSimdMemMs64 : OpCodeMemReg64, IOpCodeSimd64
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{
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public int Reps { get; private set; }
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public int SElems { get; private set; }
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public int Elems { get; private set; }
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public bool WBack { get; private set; }
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public OpCodeSimdMemMs64(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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switch ((opCode >> 12) & 0xf)
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{
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case 0b0000: Reps = 1; SElems = 4; break;
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case 0b0010: Reps = 4; SElems = 1; break;
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case 0b0100: Reps = 1; SElems = 3; break;
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case 0b0110: Reps = 3; SElems = 1; break;
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case 0b0111: Reps = 1; SElems = 1; break;
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case 0b1000: Reps = 1; SElems = 2; break;
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case 0b1010: Reps = 2; SElems = 1; break;
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default: inst = Inst.Undefined; return;
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}
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Size = (opCode >> 10) & 3;
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WBack = ((opCode >> 23) & 1) != 0;
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bool q = ((opCode >> 30) & 1) != 0;
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if (!q && Size == 3 && SElems != 1)
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{
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inst = Inst.Undefined;
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return;
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}
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Extend64 = false;
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RegisterSize = q
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? State.RegisterSize.Simd128
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: State.RegisterSize.Simd64;
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Elems = (GetBitsCount() >> 3) >> Size;
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}
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}
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} |