mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-24 17:55:49 +00:00
5e724cf24e
* Delete DelegateTypes.cs * Delete DelegateCache.cs * Add files via upload * Update Horizon.cs * Update Program.cs * Update MainWindow.cs * Update Aot.cs * Update RelocEntry.cs * Update Translator.cs * Update MemoryManager.cs * Update InstEmitMemoryHelper.cs * Update Delegates.cs * Nit. * Nit. * Nit. * 10 fewer MSIL bytes for us * Add comment. Nits. * Update Translator.cs * Update Aot.cs * Nits. * Opt.. * Opt.. * Opt.. * Opt.. * Allow to change compression level. * Update MemoryManager.cs * Update Translator.cs * Manage corner cases during the save phase. Nits. * Update Aot.cs * Translator response tweak for Aot disabled. Nit. * Nit. * Nits. * Create DelegateHelpers.cs * Update Delegates.cs * Nit. * Nit. * Nits. * Fix due to #784. * Fixes due to #757 & #841. * Fix due to #846. * Fix due to #847. * Use MethodInfo for managed method calls. Use IR methods instead of managed methods about Max/Min (S/U). Follow-ups & Nits. * Add missing exception messages. Reintroduce slow path for Fmov_Vi. Implement slow path for Fmov_Si. * Switch to the new folder structure. Nits. * Impl. index-based relocation information. Impl. cache file version field. * Nit. * Address gdkchan comments. Mainly: - fixed cache file corruption issue on exit; - exposed a way to disable AOT on the GUI. * Address AcK77 comment. * Address Thealexbarney, jduncanator & emmauss comments. Header magic, CpuId (FI) & Aot -> Ptc. * Adaptation to the new application reloading system. Improvements to the call system of managed methods. Follow-ups. Nits. * Get the same boot times as on master when PTC is disabled. * Profiled Aot. * A32 support (#897). * #975 support (1 of 2). * #975 support (2 of 2). * Rebase fix & nits. * Some fixes and nits (still one bug left). * One fix & nits. * Tests fix (by gdk) & nits. * Support translations not only in high quality and rejit. Nits. * Added possibility to skip translations and continue execution, using `ESC` key. * Update SettingsWindow.cs * Update GLRenderer.cs * Update Ptc.cs * Disabled Profiled PTC by default as requested in the past by gdk. * Fix rejit bug. Increased number of parallel translations. Add stack unwinding stuffs support (1 of 2). Nits. * Add stack unwinding stuffs support (2 of 2). Tuned number of parallel translations. * Restored the ability to assemble jumps with 8-bit offset when Profiled PTC is disabled or during profiling. Modifications due to rebase. Nits. * Limited profiling of the functions to be translated to the addresses belonging to the range of static objects only. * Nits. * Nits. * Update Delegates.cs * Nit. * Update InstEmitSimdArithmetic.cs * Address riperiperi comments. * Fixed the issue of unjustifiably longer boot times at the second boot than at the first boot, measured at the same time or reference point and with the same number of translated functions. * Implemented a simple redundant load/save mechanism. Halved the value of Decoder.MaxInstsPerFunction more appropriate for the current performance of the Translator. Replaced by Logger.PrintError to Logger.PrintDebug in TexturePool.cs about the supposed invalid texture format to avoid the spawn of the log. Nits. * Nit. Improved Logger.PrintError in TexturePool.cs to avoid log spawn. Added missing code for FZ handling (in output) for fp max/min instructions (slow paths). * Add configuration migration for PTC Co-authored-by: Thog <me@thog.eu>
412 lines
14 KiB
C#
412 lines
14 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using System.Reflection;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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using Func2I = Func<Operand, Operand, Operand>;
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static partial class InstEmit32
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{
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public static void Vceq_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.Equal, false);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareEQFpscr), false);
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}
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}
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public static void Vceq_I(ArmEmitterContext context)
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{
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EmitCmpOpI32(context, context.ICompareEqual, context.ICompareEqual, false, false);
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}
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public static void Vceq_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.Equal, true);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareEQFpscr), true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareEqual, context.ICompareEqual, true, false);
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}
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}
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public static void Vcge_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.GreaterThanOrEqual, false);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareGEFpscr), false);
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}
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}
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public static void Vcge_I(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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EmitCmpOpI32(context, context.ICompareGreaterOrEqual, context.ICompareGreaterOrEqualUI, false, !op.U);
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}
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public static void Vcge_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.GreaterThanOrEqual, true);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareGEFpscr), true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareGreaterOrEqual, context.ICompareGreaterOrEqualUI, true, true);
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}
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}
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public static void Vcgt_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.GreaterThan, false);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareGTFpscr), false);
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}
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}
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public static void Vcgt_I(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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EmitCmpOpI32(context, context.ICompareGreater, context.ICompareGreaterUI, false, !op.U);
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}
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public static void Vcgt_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.GreaterThan, true);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareGTFpscr), true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareGreater, context.ICompareGreaterUI, true, true);
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}
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}
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public static void Vcle_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.LessThanOrEqual, true);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareLEFpscr), true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareLessOrEqual, context.ICompareLessOrEqualUI, true, true);
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}
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}
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public static void Vclt_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.LessThan, true);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareLTFpscr), true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareLess, context.ICompareLessUI, true, true);
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}
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}
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private static void EmitCmpOpF32(ArmEmitterContext context, string name, bool zero)
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{
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Operand one = Const(1);
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if (zero)
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{
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EmitVectorUnaryOpF32(context, (m) =>
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{
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OperandType type = m.Type;
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if (type == OperandType.FP64)
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{
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return context.Call(typeof(SoftFloat64).GetMethod(name), m, ConstF(0.0d), one);
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}
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else
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{
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return context.Call(typeof(SoftFloat32).GetMethod(name), m, ConstF(0.0f), one);
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}
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});
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}
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else
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{
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EmitVectorBinaryOpF32(context, (n, m) =>
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{
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OperandType type = n.Type;
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if (type == OperandType.FP64)
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{
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return context.Call(typeof(SoftFloat64).GetMethod(name), n, m, one);
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}
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else
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{
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return context.Call(typeof(SoftFloat32).GetMethod(name), n, m, one);
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}
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});
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}
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}
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private static Operand ZerosOrOnes(ArmEmitterContext context, Operand fromBool, OperandType baseType)
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{
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var ones = (baseType == OperandType.I64) ? Const(-1L) : Const(-1);
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return context.ConditionalSelect(fromBool, ones, Const(baseType, 0L));
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}
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private static void EmitCmpOpI32(
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ArmEmitterContext context,
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Func2I signedOp,
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Func2I unsignedOp,
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bool zero,
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bool signed)
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{
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if (zero)
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{
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if (signed)
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{
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EmitVectorUnaryOpSx32(context, (m) =>
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{
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OperandType type = m.Type;
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Operand zeroV = (type == OperandType.I64) ? Const(0L) : Const(0);
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return ZerosOrOnes(context, signedOp(m, zeroV), type);
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});
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}
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else
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{
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EmitVectorUnaryOpZx32(context, (m) =>
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{
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OperandType type = m.Type;
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Operand zeroV = (type == OperandType.I64) ? Const(0L) : Const(0);
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return ZerosOrOnes(context, unsignedOp(m, zeroV), type);
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});
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}
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}
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else
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{
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if (signed)
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{
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EmitVectorBinaryOpSx32(context, (n, m) => ZerosOrOnes(context, signedOp(n, m), n.Type));
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (n, m) => ZerosOrOnes(context, unsignedOp(n, m), n.Type));
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}
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}
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}
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public static void Vcmp(ArmEmitterContext context)
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{
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EmitVcmpOrVcmpe(context, false);
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}
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public static void Vcmpe(ArmEmitterContext context)
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{
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EmitVcmpOrVcmpe(context, true);
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}
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private static void EmitVcmpOrVcmpe(ArmEmitterContext context, bool signalNaNs)
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{
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OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
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bool cmpWithZero = (op.Opc & 2) != 0;
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int sizeF = op.Size & 1;
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if (Optimizations.FastFP && (signalNaNs ? Optimizations.UseAvx : Optimizations.UseSse2))
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{
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CmpCondition cmpOrdered = signalNaNs ? CmpCondition.OrderedS : CmpCondition.OrderedQ;
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bool doubleSize = sizeF != 0;
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int shift = doubleSize ? 1 : 2;
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Operand m = GetVecA32(op.Vm >> shift);
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Operand n = GetVecA32(op.Vd >> shift);
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n = EmitSwapScalar(context, n, op.Vd, doubleSize);
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m = cmpWithZero ? context.VectorZero() : EmitSwapScalar(context, m, op.Vm, doubleSize);
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Operand lblNaN = Label();
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Operand lblEnd = Label();
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if (!doubleSize)
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{
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Operand ordMask = context.AddIntrinsic(Intrinsic.X86Cmpss, n, m, Const((int)cmpOrdered));
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Operand isOrdered = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, ordMask);
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context.BranchIfFalse(lblNaN, isOrdered);
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Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comissge, n, m);
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Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisseq, n, m);
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Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisslt, n, m);
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EmitSetFPSCRFlags(context, nf, zf, cf, Const(0));
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}
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else
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{
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Operand ordMask = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, m, Const((int)cmpOrdered));
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Operand isOrdered = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, ordMask);
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context.BranchIfFalse(lblNaN, isOrdered);
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Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comisdge, n, m);
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Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisdeq, n, m);
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Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisdlt, n, m);
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EmitSetFPSCRFlags(context, nf, zf, cf, Const(0));
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}
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context.Branch(lblEnd);
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context.MarkLabel(lblNaN);
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EmitSetFPSCRFlags(context, Const(3));
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context.MarkLabel(lblEnd);
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}
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else
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{
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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Operand ne = ExtractScalar(context, type, op.Vd);
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Operand me;
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if (cmpWithZero)
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{
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me = sizeF == 0 ? ConstF(0f) : ConstF(0d);
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}
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else
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{
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me = ExtractScalar(context, type, op.Vm);
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}
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MethodInfo info = sizeF != 0
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? typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompare))
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: typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompare));
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Operand nzcv = context.Call(info, ne, me, Const(signalNaNs));
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EmitSetFPSCRFlags(context, nzcv);
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}
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}
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private static void EmitSetFPSCRFlags(ArmEmitterContext context, Operand nzcv)
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{
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Operand Extract(Operand value, int bit)
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{
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if (bit != 0)
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{
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value = context.ShiftRightUI(value, Const(bit));
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}
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value = context.BitwiseAnd(value, Const(1));
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return value;
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}
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SetFpFlag(context, FPState.VFlag, Extract(nzcv, 0));
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SetFpFlag(context, FPState.CFlag, Extract(nzcv, 1));
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SetFpFlag(context, FPState.ZFlag, Extract(nzcv, 2));
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SetFpFlag(context, FPState.NFlag, Extract(nzcv, 3));
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}
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private static void EmitSetFPSCRFlags(ArmEmitterContext context, Operand n, Operand z, Operand c, Operand v)
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{
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SetFpFlag(context, FPState.VFlag, v);
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SetFpFlag(context, FPState.CFlag, c);
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SetFpFlag(context, FPState.ZFlag, z);
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SetFpFlag(context, FPState.NFlag, n);
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}
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private static void EmitSse2OrAvxCmpOpF32(ArmEmitterContext context, CmpCondition cond, bool zero)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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int sizeF = op.Size & 1;
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Intrinsic inst = (sizeF == 0) ? Intrinsic.X86Cmpps : Intrinsic.X86Cmppd;
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if (zero)
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{
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EmitVectorUnaryOpSimd32(context, (m) =>
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{
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return context.AddIntrinsic(inst, m, context.VectorZero(), Const((int)cond));
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});
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}
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else
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{
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EmitVectorBinaryOpSimd32(context, (n, m) =>
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{
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return context.AddIntrinsic(inst, n, m, Const((int)cond));
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});
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}
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}
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}
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}
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