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02a6fdcd13
* Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update CpuTestAlu.cs * Update CpuTestAluImm.cs * Update CpuTestAluRs.cs * Update CpuTestAluRx.cs * Update CpuTestBfm.cs * Update CpuTestCcmpImm.cs * Update CpuTestCcmpReg.cs * Update CpuTestCsel.cs * Update CpuTestMov.cs * Update CpuTestMul.cs * Update Ryujinx.Tests.csproj * Update Ryujinx.csproj * Update Luea.csproj * Update Ryujinx.ShaderTools.csproj * Address PR feedback (further tested). * Address PR feedback.
213 lines
8.6 KiB
C#
213 lines
8.6 KiB
C#
//#define Bfm
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("Bfm"), Ignore("Tested: second half of 2018.")]
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public sealed class CpuTestBfm : CpuTest
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{
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#if Bfm
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[SetUp]
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public void SetupTester()
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{
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AArch64.TakeReset(false);
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}
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[Test, Description("BFM <Xd>, <Xn>, #<immr>, #<imms>")]
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public void Bfm_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Random(2)] ulong _Xd,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms)
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{
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uint Opcode = 0xB3400000; // BFM X0, X0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rd, new Bits(_Xd));
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("BFM <Wd>, <Wn>, #<immr>, #<imms>")]
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public void Bfm_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Random(2)] uint _Wd,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms)
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{
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uint Opcode = 0x33000000; // BFM W0, W0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rd, new Bits(_Wd));
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("SBFM <Xd>, <Xn>, #<immr>, #<imms>")]
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public void Sbfm_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms)
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{
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uint Opcode = 0x93400000; // SBFM X0, X0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("SBFM <Wd>, <Wn>, #<immr>, #<imms>")]
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public void Sbfm_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms)
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{
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uint Opcode = 0x13000000; // SBFM W0, W0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("UBFM <Xd>, <Xn>, #<immr>, #<imms>")]
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public void Ubfm_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr,
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms)
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{
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uint Opcode = 0xD3400000; // UBFM X0, X0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("UBFM <Wd>, <Wn>, #<immr>, #<imms>")]
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public void Ubfm_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr,
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms)
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{
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uint Opcode = 0x53000000; // UBFM W0, W0, #0, #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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#endif
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}
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}
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