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https://github.com/GreemDev/Ryujinx.git
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2f16491712
* Get rid of Reflection.Emit dependency on CPU and Shader projects * Remove useless private sets * Missed those due to the alignment
107 lines
No EOL
3.5 KiB
C#
107 lines
No EOL
3.5 KiB
C#
namespace ARMeilleure.Decoders
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{
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class OpCodeSimdImm : OpCode, IOpCodeSimd
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{
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public int Rd { get; }
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public long Immediate { get; }
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public int Size { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode);
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public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Rd = opCode & 0x1f;
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int cMode = (opCode >> 12) & 0xf;
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int op = (opCode >> 29) & 0x1;
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int modeLow = cMode & 1;
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int modeHigh = cMode >> 1;
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long imm;
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imm = ((uint)opCode >> 5) & 0x1f;
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imm |= ((uint)opCode >> 11) & 0xe0;
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if (modeHigh == 0b111)
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{
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switch (op | (modeLow << 1))
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{
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case 0:
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// 64-bits Immediate.
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// Transform abcd efgh into abcd efgh abcd efgh ...
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Size = 3;
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imm = (long)((ulong)imm * 0x0101010101010101);
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break;
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case 1:
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// 64-bits Immediate.
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// Transform abcd efgh into aaaa aaaa bbbb bbbb ...
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Size = 3;
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imm = (imm & 0xf0) >> 4 | (imm & 0x0f) << 4;
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imm = (imm & 0xcc) >> 2 | (imm & 0x33) << 2;
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imm = (imm & 0xaa) >> 1 | (imm & 0x55) << 1;
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imm = (long)((ulong)imm * 0x8040201008040201);
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imm = (long)((ulong)imm & 0x8080808080808080);
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imm |= imm >> 4;
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imm |= imm >> 2;
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imm |= imm >> 1;
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break;
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case 2:
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// 2 x 32-bits floating point Immediate.
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Size = 0;
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imm = (long)DecoderHelper.Imm8ToFP32Table[(int)imm];
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imm |= imm << 32;
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break;
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case 3:
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// 64-bits floating point Immediate.
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Size = 1;
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imm = (long)DecoderHelper.Imm8ToFP64Table[(int)imm];
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break;
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}
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}
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else if ((modeHigh & 0b110) == 0b100)
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{
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// 16-bits shifted Immediate.
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Size = 1; imm <<= (modeHigh & 1) << 3;
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}
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else if ((modeHigh & 0b100) == 0b000)
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{
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// 32-bits shifted Immediate.
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Size = 2; imm <<= modeHigh << 3;
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}
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else if ((modeHigh & 0b111) == 0b110)
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{
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// 32-bits shifted Immediate (fill with ones).
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Size = 2; imm = ShlOnes(imm, 8 << modeLow);
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}
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else
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{
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// 8-bits without shift.
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Size = 0;
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}
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Immediate = imm;
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RegisterSize = ((opCode >> 30) & 1) != 0
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? RegisterSize.Simd128
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: RegisterSize.Simd64;
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}
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private static long ShlOnes(long value, int shift)
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{
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if (shift != 0)
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{
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return value << shift | (long)(ulong.MaxValue >> (64 - shift));
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}
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else
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{
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return value;
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}
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}
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}
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} |