mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-23 10:25:47 +00:00
9cb57fb4bb
* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
311 lines
9 KiB
C#
311 lines
9 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics.X86;
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using static ChocolArm64.Instructions.InstEmitSimdHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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public static void And_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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EmitSse2Op(context, nameof(Sse2.And));
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}
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else
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{
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EmitVectorBinaryOpZx(context, () => context.Emit(OpCodes.And));
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}
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}
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public static void Bic_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
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EmitLdvecWithUnsignedCast(context, op.Rn, op.Size);
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Type[] types = new Type[]
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{
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VectorUIntTypesPerSizeLog2[op.Size],
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VectorUIntTypesPerSizeLog2[op.Size]
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};
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), types));
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EmitStvecWithUnsignedCast(context, op.Rd, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitVectorBinaryOpZx(context, () =>
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{
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.And);
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});
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}
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}
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public static void Bic_Vi(ILEmitterCtx context)
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{
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EmitVectorImmBinaryOp(context, () =>
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{
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.And);
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});
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}
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public static void Bif_V(ILEmitterCtx context)
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{
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EmitBitBif(context, true);
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}
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public static void Bit_V(ILEmitterCtx context)
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{
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EmitBitBif(context, false);
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}
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private static void EmitBitBif(ILEmitterCtx context, bool notRm)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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Type[] types = new Type[]
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{
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VectorUIntTypesPerSizeLog2[op.Size],
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VectorUIntTypesPerSizeLog2[op.Size]
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};
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EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
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EmitLdvecWithUnsignedCast(context, op.Rd, op.Size);
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EmitLdvecWithUnsignedCast(context, op.Rn, op.Size);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), types));
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string name = notRm ? nameof(Sse2.AndNot) : nameof(Sse2.And);
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context.EmitCall(typeof(Sse2).GetMethod(name, types));
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EmitLdvecWithUnsignedCast(context, op.Rd, op.Size);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), types));
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EmitStvecWithUnsignedCast(context, op.Rd, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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int bytes = op.GetBitsCount() >> 3;
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int elems = bytes >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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EmitVectorExtractZx(context, op.Rd, index, op.Size);
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EmitVectorExtractZx(context, op.Rn, index, op.Size);
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context.Emit(OpCodes.Xor);
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EmitVectorExtractZx(context, op.Rm, index, op.Size);
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if (notRm)
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{
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context.Emit(OpCodes.Not);
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}
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context.Emit(OpCodes.And);
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EmitVectorExtractZx(context, op.Rd, index, op.Size);
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context.Emit(OpCodes.Xor);
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EmitVectorInsert(context, op.Rd, index, op.Size);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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}
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public static void Bsl_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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Type[] types = new Type[]
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{
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VectorUIntTypesPerSizeLog2[op.Size],
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VectorUIntTypesPerSizeLog2[op.Size]
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};
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EmitLdvecWithUnsignedCast(context, op.Rn, op.Size);
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EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), types));
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EmitLdvecWithUnsignedCast(context, op.Rd, op.Size);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.And), types));
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EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), types));
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EmitStvecWithUnsignedCast(context, op.Rd, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitVectorTernaryOpZx(context, () =>
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{
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context.EmitSttmp();
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context.EmitLdtmp();
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context.Emit(OpCodes.Xor);
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context.Emit(OpCodes.And);
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context.EmitLdtmp();
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context.Emit(OpCodes.Xor);
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});
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}
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}
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public static void Eor_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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EmitSse2Op(context, nameof(Sse2.Xor));
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}
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else
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{
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EmitVectorBinaryOpZx(context, () => context.Emit(OpCodes.Xor));
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}
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}
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public static void Not_V(ILEmitterCtx context)
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{
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EmitVectorUnaryOpZx(context, () => context.Emit(OpCodes.Not));
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}
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public static void Orn_V(ILEmitterCtx context)
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{
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EmitVectorBinaryOpZx(context, () =>
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{
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.Or);
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});
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}
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public static void Orr_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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EmitSse2Op(context, nameof(Sse2.Or));
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}
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else
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{
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EmitVectorBinaryOpZx(context, () => context.Emit(OpCodes.Or));
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}
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}
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public static void Orr_Vi(ILEmitterCtx context)
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{
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EmitVectorImmBinaryOp(context, () => context.Emit(OpCodes.Or));
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}
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public static void Rbit_V(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8;
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for (int index = 0; index < elems; index++)
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{
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EmitVectorExtractZx(context, op.Rn, index, 0);
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context.Emit(OpCodes.Conv_U4);
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SoftFallback.EmitCall(context, nameof(SoftFallback.ReverseBits8));
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context.Emit(OpCodes.Conv_U8);
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EmitVectorInsert(context, op.Rd, index, 0);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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public static void Rev16_V(ILEmitterCtx context)
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{
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EmitRev_V(context, containerSize: 1);
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}
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public static void Rev32_V(ILEmitterCtx context)
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{
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EmitRev_V(context, containerSize: 2);
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}
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public static void Rev64_V(ILEmitterCtx context)
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{
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EmitRev_V(context, containerSize: 3);
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}
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private static void EmitRev_V(ILEmitterCtx context, int containerSize)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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if (op.Size >= containerSize)
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{
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throw new InvalidOperationException();
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}
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int bytes = op.GetBitsCount() >> 3;
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int elems = bytes >> op.Size;
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int containerMask = (1 << (containerSize - op.Size)) - 1;
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for (int index = 0; index < elems; index++)
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{
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int revIndex = index ^ containerMask;
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EmitVectorExtractZx(context, op.Rn, revIndex, op.Size);
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EmitVectorInsertTmp(context, index, op.Size);
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}
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context.EmitLdvectmp();
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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}
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}
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