mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-23 23:15:47 +00:00
0b52ee6627
* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements * Remove useless space * Address PR feedback * Revert EmitVectorZero32_128 changes
550 lines
17 KiB
C#
550 lines
17 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics.X86;
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using static ChocolArm64.Instruction.AInstEmitSimdHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Dup_Gp(AILEmitterCtx Context)
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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if (AOptimizations.UseSse2)
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{
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Context.EmitLdintzr(Op.Rn);
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switch (Op.Size)
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{
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case 0: Context.Emit(OpCodes.Conv_U1); break;
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case 1: Context.Emit(OpCodes.Conv_U2); break;
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case 2: Context.Emit(OpCodes.Conv_U4); break;
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}
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Type[] Types = new Type[] { UIntTypesPerSizeLog2[Op.Size] };
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), Types));
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EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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else
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{
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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for (int Index = 0; Index < Elems; Index++)
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{
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Context.EmitLdintzr(Op.Rn);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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}
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public static void Dup_S(AILEmitterCtx Context)
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, Op.DstIndex, Op.Size);
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EmitScalarSet(Context, Op.Rd, Op.Size);
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}
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public static void Dup_V(AILEmitterCtx Context)
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Op.DstIndex, Op.Size);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Ext_V(AILEmitterCtx Context)
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{
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AOpCodeSimdExt Op = (AOpCodeSimdExt)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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int Bytes = Op.GetBitsCount() >> 3;
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int Position = Op.Imm4;
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for (int Index = 0; Index < Bytes; Index++)
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{
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int Reg = Op.Imm4 + Index < Bytes ? Op.Rn : Op.Rm;
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if (Position == Bytes)
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{
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Position = 0;
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}
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EmitVectorExtractZx(Context, Reg, Position++, 0);
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EmitVectorInsertTmp(Context, Index, 0);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Fcsel_S(AILEmitterCtx Context)
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{
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AOpCodeSimdFcond Op = (AOpCodeSimdFcond)Context.CurrOp;
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AILLabel LblTrue = new AILLabel();
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AILLabel LblEnd = new AILLabel();
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Context.EmitCondBranch(LblTrue, Op.Cond);
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EmitVectorExtractF(Context, Op.Rm, 0, Op.Size);
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Context.Emit(OpCodes.Br_S, LblEnd);
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Context.MarkLabel(LblTrue);
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EmitVectorExtractF(Context, Op.Rn, 0, Op.Size);
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Context.MarkLabel(LblEnd);
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EmitScalarSetF(Context, Op.Rd, Op.Size);
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}
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public static void Fmov_Ftoi(AILEmitterCtx Context)
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{
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AOpCodeSimdCvt Op = (AOpCodeSimdCvt)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, 0, 3);
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EmitIntZeroUpperIfNeeded(Context);
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Context.EmitStintzr(Op.Rd);
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}
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public static void Fmov_Ftoi1(AILEmitterCtx Context)
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{
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AOpCodeSimdCvt Op = (AOpCodeSimdCvt)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, 1, 3);
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EmitIntZeroUpperIfNeeded(Context);
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Context.EmitStintzr(Op.Rd);
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}
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public static void Fmov_Itof(AILEmitterCtx Context)
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{
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AOpCodeSimdCvt Op = (AOpCodeSimdCvt)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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EmitIntZeroUpperIfNeeded(Context);
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EmitScalarSet(Context, Op.Rd, 3);
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}
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public static void Fmov_Itof1(AILEmitterCtx Context)
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{
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AOpCodeSimdCvt Op = (AOpCodeSimdCvt)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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EmitIntZeroUpperIfNeeded(Context);
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EmitVectorInsert(Context, Op.Rd, 1, 3);
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}
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public static void Fmov_S(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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EmitVectorExtractF(Context, Op.Rn, 0, Op.Size);
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EmitScalarSetF(Context, Op.Rd, Op.Size);
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}
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public static void Fmov_Si(AILEmitterCtx Context)
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{
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AOpCodeSimdFmov Op = (AOpCodeSimdFmov)Context.CurrOp;
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Context.EmitLdc_I8(Op.Imm);
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EmitScalarSet(Context, Op.Rd, Op.Size + 2);
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}
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public static void Fmov_V(AILEmitterCtx Context)
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{
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AOpCodeSimdImm Op = (AOpCodeSimdImm)Context.CurrOp;
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int Elems = Op.RegisterSize == ARegisterSize.SIMD128 ? 4 : 2;
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for (int Index = 0; Index < (Elems >> Op.Size); Index++)
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{
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Context.EmitLdc_I8(Op.Imm);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size + 2);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Ins_Gp(AILEmitterCtx Context)
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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EmitVectorInsert(Context, Op.Rd, Op.DstIndex, Op.Size);
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}
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public static void Ins_V(AILEmitterCtx Context)
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, Op.SrcIndex, Op.Size);
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EmitVectorInsert(Context, Op.Rd, Op.DstIndex, Op.Size);
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}
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public static void Movi_V(AILEmitterCtx Context)
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{
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EmitVectorImmUnaryOp(Context, () => { });
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}
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public static void Mvni_V(AILEmitterCtx Context)
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{
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EmitVectorImmUnaryOp(Context, () => Context.Emit(OpCodes.Not));
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}
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public static void Tbl_V(AILEmitterCtx Context)
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{
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AOpCodeSimdTbl Op = (AOpCodeSimdTbl)Context.CurrOp;
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Context.EmitLdvec(Op.Rm);
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for (int Index = 0; Index < Op.Size; Index++)
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{
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Context.EmitLdvec((Op.Rn + Index) & 0x1f);
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}
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switch (Op.Size)
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{
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case 1: AVectorHelper.EmitCall(Context,
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nameof(AVectorHelper.Tbl1_V64),
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nameof(AVectorHelper.Tbl1_V128)); break;
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case 2: AVectorHelper.EmitCall(Context,
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nameof(AVectorHelper.Tbl2_V64),
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nameof(AVectorHelper.Tbl2_V128)); break;
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case 3: AVectorHelper.EmitCall(Context,
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nameof(AVectorHelper.Tbl3_V64),
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nameof(AVectorHelper.Tbl3_V128)); break;
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case 4: AVectorHelper.EmitCall(Context,
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nameof(AVectorHelper.Tbl4_V64),
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nameof(AVectorHelper.Tbl4_V128)); break;
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default: throw new InvalidOperationException();
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}
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Context.EmitStvec(Op.Rd);
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}
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public static void Trn1_V(AILEmitterCtx Context)
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{
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EmitVectorTranspose(Context, Part: 0);
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}
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public static void Trn2_V(AILEmitterCtx Context)
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{
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EmitVectorTranspose(Context, Part: 1);
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}
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public static void Umov_S(AILEmitterCtx Context)
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{
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AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, Op.DstIndex, Op.Size);
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Context.EmitStintzr(Op.Rd);
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}
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public static void Uzp1_V(AILEmitterCtx Context)
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{
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EmitVectorUnzip(Context, Part: 0);
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}
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public static void Uzp2_V(AILEmitterCtx Context)
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{
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EmitVectorUnzip(Context, Part: 1);
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}
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public static void Xtn_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Elems = 8 >> Op.Size;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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if (AOptimizations.UseSse41 && Op.Size < 2)
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{
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void EmitZeroVector()
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{
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switch (Op.Size)
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{
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case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt16Zero)); break;
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case 1: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt32Zero)); break;
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}
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}
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//For XTN, first operand is source, second operand is 0.
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//For XTN2, first operand is 0, second operand is source.
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if (Part != 0)
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{
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EmitZeroVector();
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}
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EmitLdvecWithSignedCast(Context, Op.Rn, Op.Size + 1);
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//Set mask to discard the upper half of the wide elements.
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switch (Op.Size)
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{
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case 0: Context.EmitLdc_I4(0x00ff); break;
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case 1: Context.EmitLdc_I4(0x0000ffff); break;
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}
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Type WideType = IntTypesPerSizeLog2[Op.Size + 1];
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), new Type[] { WideType }));
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WideType = VectorIntTypesPerSizeLog2[Op.Size + 1];
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Type[] WideTypes = new Type[] { WideType, WideType };
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.And), WideTypes));
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if (Part == 0)
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{
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EmitZeroVector();
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}
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//Pack values with signed saturation, the signed saturation shouldn't
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//saturate anything since the upper bits were masked off.
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Type SseType = Op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
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Context.EmitCall(SseType.GetMethod(nameof(Sse2.PackUnsignedSaturate), WideTypes));
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if (Part != 0)
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{
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//For XTN2, we additionally need to discard the upper bits
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//of the target register and OR the result with it.
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EmitVectorZeroUpper(Context, Op.Rd);
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EmitLdvecWithUnsignedCast(Context, Op.Rd, Op.Size);
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Type NarrowType = VectorUIntTypesPerSizeLog2[Op.Size];
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), new Type[] { NarrowType, NarrowType }));
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}
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EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
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}
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else
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{
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if (Part != 0)
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{
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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}
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
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EmitVectorInsertTmp(Context, Part + Index, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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}
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public static void Zip1_V(AILEmitterCtx Context)
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{
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EmitVectorZip(Context, Part: 0);
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}
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public static void Zip2_V(AILEmitterCtx Context)
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{
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EmitVectorZip(Context, Part: 1);
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}
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private static void EmitIntZeroUpperIfNeeded(AILEmitterCtx Context)
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{
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if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
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{
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Context.Emit(OpCodes.Conv_U4);
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Context.Emit(OpCodes.Conv_U8);
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}
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}
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private static void EmitVectorTranspose(AILEmitterCtx Context, int Part)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Words = Op.GetBitsCount() >> 4;
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int Pairs = Words >> Op.Size;
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for (int Index = 0; Index < Pairs; Index++)
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{
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int Idx = Index << 1;
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EmitVectorExtractZx(Context, Op.Rn, Idx + Part, Op.Size);
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EmitVectorExtractZx(Context, Op.Rm, Idx + Part, Op.Size);
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EmitVectorInsertTmp(Context, Idx + 1, Op.Size);
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EmitVectorInsertTmp(Context, Idx, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorUnzip(AILEmitterCtx Context, int Part)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Words = Op.GetBitsCount() >> 4;
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int Pairs = Words >> Op.Size;
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for (int Index = 0; Index < Pairs; Index++)
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{
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int Idx = Index << 1;
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EmitVectorExtractZx(Context, Op.Rn, Idx + Part, Op.Size);
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EmitVectorExtractZx(Context, Op.Rm, Idx + Part, Op.Size);
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EmitVectorInsertTmp(Context, Pairs + Index, Op.Size);
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorZip(AILEmitterCtx Context, int Part)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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if (AOptimizations.UseSse2)
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{
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EmitLdvecWithUnsignedCast(Context, Op.Rn, Op.Size);
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EmitLdvecWithUnsignedCast(Context, Op.Rm, Op.Size);
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Type[] Types = new Type[]
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{
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VectorUIntTypesPerSizeLog2[Op.Size],
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VectorUIntTypesPerSizeLog2[Op.Size]
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};
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string Name = Part == 0 || (Part != 0 && Op.RegisterSize == ARegisterSize.SIMD64)
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? nameof(Sse2.UnpackLow)
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: nameof(Sse2.UnpackHigh);
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Context.EmitCall(typeof(Sse2).GetMethod(Name, Types));
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if (Op.RegisterSize == ARegisterSize.SIMD64 && Part != 0)
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{
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Context.EmitLdc_I4(8);
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Type[] ShTypes = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], typeof(byte) };
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), ShTypes));
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}
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EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64 && Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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else
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{
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int Words = Op.GetBitsCount() >> 4;
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int Pairs = Words >> Op.Size;
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int Base = Part != 0 ? Pairs : 0;
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|
|
|
for (int Index = 0; Index < Pairs; Index++)
|
|
{
|
|
int Idx = Index << 1;
|
|
|
|
EmitVectorExtractZx(Context, Op.Rn, Base + Index, Op.Size);
|
|
EmitVectorExtractZx(Context, Op.Rm, Base + Index, Op.Size);
|
|
|
|
EmitVectorInsertTmp(Context, Idx + 1, Op.Size);
|
|
EmitVectorInsertTmp(Context, Idx, Op.Size);
|
|
}
|
|
|
|
Context.EmitLdvectmp();
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|