mirror of
https://github.com/GreemDev/Ryujinx.git
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e21ebbf666
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0 * Refactoring * Add a config entry to enable or disable the reg load/store opt. * Remove unnecessary register state stores for calls when the callee is know * Rename IoType to VarType * Enable tier 0 while fixing some perf issues related to tier 0 * Small tweak -- Compile before adding to the cache, to avoid lags * Add required config entry
67 lines
No EOL
1.8 KiB
C#
67 lines
No EOL
1.8 KiB
C#
using System.Reflection.Emit;
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using System.Runtime.InteropServices;
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namespace ChocolArm64.Translation
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{
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class ILOpCodeConst : IILEmit
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{
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[StructLayout(LayoutKind.Explicit, Size = 8)]
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private struct ImmVal
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{
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[FieldOffset(0)] public int I4;
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[FieldOffset(0)] public long I8;
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[FieldOffset(0)] public float R4;
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[FieldOffset(0)] public double R8;
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}
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private ImmVal _value;
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public long Value => _value.I8;
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private enum ConstType
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{
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Int32,
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Int64,
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Single,
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Double
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}
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private ConstType _type;
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private ILOpCodeConst(ConstType type)
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{
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_type = type;
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}
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public ILOpCodeConst(int value) : this(ConstType.Int32)
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{
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_value = new ImmVal { I4 = value };
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}
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public ILOpCodeConst(long value) : this(ConstType.Int64)
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{
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_value = new ImmVal { I8 = value };
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}
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public ILOpCodeConst(float value) : this(ConstType.Single)
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{
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_value = new ImmVal { R4 = value };
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}
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public ILOpCodeConst(double value) : this(ConstType.Double)
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{
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_value = new ImmVal { R8 = value };
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}
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public void Emit(ILMethodBuilder context)
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{
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switch (_type)
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{
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case ConstType.Int32: context.Generator.EmitLdc_I4(_value.I4); break;
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case ConstType.Int64: context.Generator.Emit(OpCodes.Ldc_I8, _value.I8); break;
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case ConstType.Single: context.Generator.Emit(OpCodes.Ldc_R4, _value.R4); break;
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case ConstType.Double: context.Generator.Emit(OpCodes.Ldc_R8, _value.R8); break;
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}
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}
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}
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} |