mirror of
https://github.com/GreemDev/Ryujinx.git
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8a33e884f8
* Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Add Vfma_S & Vfms_S Fma fast paths. Add Vfnma_S inst. with Fma/Sse fast paths and slow path. Add Vfnms_S Sse fast path. Add Tests for affected inst.s. Nits. * InternalVersion = 1775 * Nits. * Fix Vfma_V slow path not using StandardFPSCRValue(). * Nit: Fix Vfma_V order. * Add Vfms_V Sse fast path and slow path. * Add Vfma_V and Vfms_V Test.
264 lines
10 KiB
C#
264 lines
10 KiB
C#
#define SimdCvt32
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using ARMeilleure.State;
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using NUnit.Framework;
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using System;
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using System.Collections.Generic;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdCvt32")]
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public sealed class CpuTestSimdCvt32 : CpuTest32
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{
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#if SimdCvt32
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#region "ValueSource (Opcodes)"
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#endregion
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#region "ValueSource (Types)"
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private static uint[] _1S_()
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{
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return new uint[] { 0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu };
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}
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private static IEnumerable<ulong> _1S_F_()
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{
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yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x0000000080800000ul; // -Min Normal
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yield return 0x00000000807FFFFFul; // -Max Subnormal
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yield return 0x0000000080000001ul; // -Min Subnormal (-float.Epsilon)
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yield return 0x000000007F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x0000000000800000ul; // +Min Normal
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yield return 0x00000000007FFFFFul; // +Max Subnormal
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yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
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if (!NoZeros)
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{
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yield return 0x0000000080000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!NoInfs)
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{
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yield return 0x00000000FF800000ul; // -Infinity
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yield return 0x000000007F800000ul; // +Infinity
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}
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if (!NoNaNs)
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{
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yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
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yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x000000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
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yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
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}
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for (int cnt = 1; cnt <= RndCnt; cnt++)
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{
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ulong grbg = TestContext.CurrentContext.Random.NextUInt();
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ulong rnd1 = GenNormalS();
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ulong rnd2 = GenSubnormalS();
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yield return (grbg << 32) | rnd1;
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yield return (grbg << 32) | rnd2;
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}
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}
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private static IEnumerable<ulong> _1D_F_()
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{
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yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
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yield return 0x8010000000000000ul; // -Min Normal
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yield return 0x800FFFFFFFFFFFFFul; // -Max Subnormal
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yield return 0x8000000000000001ul; // -Min Subnormal (-double.Epsilon)
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yield return 0x7FEFFFFFFFFFFFFFul; // +Max Normal (double.MaxValue)
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yield return 0x0010000000000000ul; // +Min Normal
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yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal
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yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon)
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if (!NoZeros)
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{
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yield return 0x8000000000000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!NoInfs)
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{
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yield return 0xFFF0000000000000ul; // -Infinity
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yield return 0x7FF0000000000000ul; // +Infinity
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}
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if (!NoNaNs)
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{
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yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN)
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yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FF8000000000000ul; // +QNaN (all zeros payload) (-double.NaN) (DefaultNaN)
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yield return 0x7FF7FFFFFFFFFFFFul; // +SNaN (all ones payload)
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}
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for (int cnt = 1; cnt <= RndCnt; cnt++)
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{
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ulong rnd1 = GenNormalD();
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ulong rnd2 = GenSubnormalD();
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yield return rnd1;
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yield return rnd2;
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}
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}
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#endregion
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private const int RndCnt = 2;
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private static readonly bool NoZeros = false;
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private static readonly bool NoInfs = false;
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private static readonly bool NoNaNs = false;
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[Explicit]
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[Test, Pairwise, Description("VCVT.<dt>.F32 <Sd>, <Sm>")]
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public void Vcvt_F32_I32([Values(0u, 1u, 2u, 3u)] uint rd,
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[Values(0u, 1u, 2u, 3u)] uint rm,
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[ValueSource(nameof(_1S_F_))] ulong s0,
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[ValueSource(nameof(_1S_F_))] ulong s1,
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[ValueSource(nameof(_1S_F_))] ulong s2,
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[ValueSource(nameof(_1S_F_))] ulong s3,
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[Values] bool unsigned) // <U32, S32>
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{
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uint opcode = 0xeebc0ac0u; // VCVT.U32.F32 S0, S0
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if (!unsigned)
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{
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opcode |= 1 << 16; // opc2<0>
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}
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opcode |= ((rd & 0x1e) << 11) | ((rd & 0x1) << 22);
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opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5);
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V128 v0 = MakeVectorE0E1E2E3((uint)s0, (uint)s1, (uint)s2, (uint)s3);
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SingleOpcode(opcode, v0: v0);
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CompareAgainstUnicorn();
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}
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[Explicit]
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[Test, Pairwise, Description("VCVT.<dt>.F64 <Sd>, <Dm>")]
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public void Vcvt_F64_I32([Values(0u, 1u, 2u, 3u)] uint rd,
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[Values(0u, 1u)] uint rm,
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[ValueSource(nameof(_1D_F_))] ulong d0,
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[ValueSource(nameof(_1D_F_))] ulong d1,
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[Values] bool unsigned) // <U32, S32>
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{
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uint opcode = 0xeebc0bc0u; // VCVT.U32.F64 S0, D0
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if (!unsigned)
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{
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opcode |= 1 << 16; // opc2<0>
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}
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opcode |= ((rd & 0x1e) << 11) | ((rd & 0x1) << 22);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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V128 v0 = MakeVectorE0E1(d0, d1);
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SingleOpcode(opcode, v0: v0);
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CompareAgainstUnicorn();
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}
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[Explicit]
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[Test, Pairwise, Description("VCVT.F32.<dt> <Sd>, <Sm>")]
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public void Vcvt_I32_F32([Values(0u, 1u, 2u, 3u)] uint rd,
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[Values(0u, 1u, 2u, 3u)] uint rm,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s0,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s1,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s2,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s3,
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[Values] bool unsigned, // <U32, S32>
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[Values(RMode.Rn)] RMode rMode)
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{
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uint opcode = 0xeeb80a40u; // VCVT.F32.U32 S0, S0
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if (!unsigned)
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{
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opcode |= 1 << 7; // op
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}
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opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5);
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opcode |= ((rd & 0x1e) << 11) | ((rd & 0x1) << 22);
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V128 v0 = MakeVectorE0E1E2E3(s0, s1, s2, s3);
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int fpscr = (int)rMode << (int)Fpcr.RMode;
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SingleOpcode(opcode, v0: v0, fpscr: fpscr);
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CompareAgainstUnicorn();
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}
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[Explicit]
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[Test, Pairwise, Description("VCVT.F64.<dt> <Dd>, <Sm>")]
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public void Vcvt_I32_F64([Values(0u, 1u)] uint rd,
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[Values(0u, 1u, 2u, 3u)] uint rm,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s0,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s1,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s2,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s3,
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[Values] bool unsigned, // <U32, S32>
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[Values(RMode.Rn)] RMode rMode)
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{
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uint opcode = 0xeeb80b40u; // VCVT.F64.U32 D0, S0
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if (!unsigned)
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{
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opcode |= 1 << 7; // op
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}
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opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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V128 v0 = MakeVectorE0E1E2E3(s0, s1, s2, s3);
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int fpscr = (int)rMode << (int)Fpcr.RMode;
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SingleOpcode(opcode, v0: v0, fpscr: fpscr);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VRINTX.F<size> <Sd>, <Sm>")]
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public void Vrintx_S([Values(0u, 1u)] uint rd,
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[Values(0u, 1u)] uint rm,
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[Values(2u, 3u)] uint size,
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[ValueSource(nameof(_1D_F_))] ulong s0,
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[ValueSource(nameof(_1D_F_))] ulong s1,
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[ValueSource(nameof(_1D_F_))] ulong s2,
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[Values(RMode.Rn, RMode.Rm, RMode.Rp)] RMode rMode)
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{
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uint opcode = 0xEB70A40;
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V128 v0, v1, v2;
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if (size == 2)
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{
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opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5);
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opcode |= ((rd & 0x1e) >> 11) | ((rm & 0x1) << 22);
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v0 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s0), (uint)BitConverter.SingleToInt32Bits(s0));
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v1 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s1), (uint)BitConverter.SingleToInt32Bits(s0));
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v2 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s2), (uint)BitConverter.SingleToInt32Bits(s1));
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}
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else
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{
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opcode |= ((rm & 0xf) << 0) | ((rd & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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v0 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s0), (uint)BitConverter.DoubleToInt64Bits(s0));
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v1 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s1), (uint)BitConverter.DoubleToInt64Bits(s0));
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v2 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s2), (uint)BitConverter.DoubleToInt64Bits(s1));
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}
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opcode |= ((size & 3) << 8);
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int fpscr = (int)rMode << (int)Fpcr.RMode;
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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