mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-24 02:45:48 +00:00
d904706fc0
* Implement Jump Table for Native Calls NOTE: this slows down rejit considerably! Not recommended to be used without codegen optimisation or AOT. - Does not work on Linux - A32 needs an additional commit. * A32 Support (WIP) * Actually write Direct Call pointers to the table That would help. * Direct Calls: Rather than returning to the translator, attempt to keep within the native stack frame. A return to the translator can still happen, but only by exceptionally bubbling up to it. Also: - Always translate lowCq as a function. Faster interop with the direct jumps, and this will be useful in future if we want to do speculative translation. - Tail Call Detection: after the decoding stage, detect if we do a tail call, and avoid translating into it. Detected if a jump is made to an address outwith the contiguous sequence of blocks surrounding the entry point. The goal is to reduce code touched by jit and rejit. * A32 Support * Use smaller max function size for lowCq, fix exceptional returns When a return has an unexpected value and there is no code block following this one, we now return the value rather than continuing. * CompareAndSwap (buggy) * Ensure CompareAndSwap does not get optimized away. * Use CompareAndSwap to make the dynamic table thread safe. * Tail call for linux, throw on too many arguments. * Combine CompareAndSwap 128 and 32/64. They emit different IR instructions since their PreAllocator behaviour is different, but now they just have one function on EmitterContext. * Fix issues separating from optimisations. * Use a stub to find and execute missing functions. This allows us to skip doing many runtime comparisons and branches, and reduces the amount of code we need to emit significantly. For the indirect call table, this stub also does the work of moving in the highCq address to the table when one is found. * Make Jump Tables and Jit Cache dynmically resize Reserve virtual memory, commit as needed. * Move TailCallRemover to its own class. * Multithreaded Translation (based on heuristic) A poor one, at that. Need to get core count for a better one, which means a lot of OS specific garbage. * Better priority management for background threads. * Bound core limit a bit more Past a certain point the load is not paralellizable and starts stealing from the main thread. Likely due to GC, memory, heap allocation thread contention. Reduce by one core til optimisations come to improve the situation. * Fix memory management on linux. * Temporary solution to some sync problems. This will make sure threads exit correctly, most of the time. There is a potential race where setting the sync counter to 0 does nothing (counter stays at what it was before, thread could take too long to exit), but we need to find a better way to do this anyways. Synchronization frequency has been tightened as we never enter blockwise segments of code. Essentially this means, check every x functions or loop iterations, before lowcq blocks existed and were worth just as much. Ideally it should be done in a better way, since functions can be anywhere from 1 to 5000 instructions. (maybe based on host timer, or an interrupt flag from a scheduler thread) * Address feedback minus CompareAndSwap change. * Use default ReservedRegion granularity. * Merge CompareAndSwap with its V128 variant. * We already got the source, no need to do it again. * Make sure all background translation threads exit. * Fix CompareAndSwap128 Detection criteria was a bit scuffed. * Address Comments.
572 lines
No EOL
18 KiB
C#
572 lines
No EOL
18 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Memory;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitMemoryHelper
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{
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private enum Extension
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{
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Zx,
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Sx32,
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Sx64
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}
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public static void EmitLoadZx(ArmEmitterContext context, Operand address, int rt, int size)
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{
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EmitLoad(context, address, Extension.Zx, rt, size);
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}
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public static void EmitLoadSx32(ArmEmitterContext context, Operand address, int rt, int size)
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{
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EmitLoad(context, address, Extension.Sx32, rt, size);
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}
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public static void EmitLoadSx64(ArmEmitterContext context, Operand address, int rt, int size)
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{
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EmitLoad(context, address, Extension.Sx64, rt, size);
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}
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private static void EmitLoad(ArmEmitterContext context, Operand address, Extension ext, int rt, int size)
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{
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bool isSimd = IsSimd(context);
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if ((uint)size > (isSimd ? 4 : 3))
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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if (isSimd)
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{
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EmitReadVector(context, address, context.VectorZero(), rt, 0, size);
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}
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else
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{
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EmitReadInt(context, address, rt, size);
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}
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if (!isSimd && !(context.CurrOp is OpCode32 && rt == State.RegisterAlias.Aarch32Pc))
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{
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Operand value = GetInt(context, rt);
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if (ext == Extension.Sx32 || ext == Extension.Sx64)
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{
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OperandType destType = ext == Extension.Sx64 ? OperandType.I64 : OperandType.I32;
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switch (size)
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{
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case 0: value = context.SignExtend8 (destType, value); break;
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case 1: value = context.SignExtend16(destType, value); break;
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case 2: value = context.SignExtend32(destType, value); break;
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}
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}
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SetInt(context, rt, value);
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}
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}
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public static void EmitLoadSimd(
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ArmEmitterContext context,
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Operand address,
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Operand vector,
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int rt,
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int elem,
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int size)
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{
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EmitReadVector(context, address, vector, rt, elem, size);
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}
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public static void EmitStore(ArmEmitterContext context, Operand address, int rt, int size)
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{
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bool isSimd = IsSimd(context);
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if ((uint)size > (isSimd ? 4 : 3))
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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if (isSimd)
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{
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EmitWriteVector(context, address, rt, 0, size);
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}
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else
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{
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EmitWriteInt(context, address, rt, size);
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}
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}
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public static void EmitStoreSimd(
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ArmEmitterContext context,
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Operand address,
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int rt,
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int elem,
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int size)
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{
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EmitWriteVector(context, address, rt, elem, size);
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}
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private static bool IsSimd(ArmEmitterContext context)
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{
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return context.CurrOp is IOpCodeSimd &&
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!(context.CurrOp is OpCodeSimdMemMs ||
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context.CurrOp is OpCodeSimdMemSs);
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}
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private static void EmitReadInt(ArmEmitterContext context, Operand address, int rt, int size)
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{
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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context.MarkLabel(lblSlowPath);
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EmitReadIntFallback(context, address, rt, size);
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context.Branch(lblEnd);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand value = null;
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switch (size)
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{
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case 0:
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value = context.Load8(physAddr);
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break;
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case 1:
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value = context.Load16(physAddr);
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break;
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case 2:
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value = context.Load(OperandType.I32, physAddr);
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break;
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case 3:
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value = context.Load(OperandType.I64, physAddr);
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break;
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}
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SetInt(context, rt, value);
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context.MarkLabel(lblEnd);
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}
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private static void EmitReadVector(
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ArmEmitterContext context,
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Operand address,
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Operand vector,
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int rt,
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int elem,
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int size)
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{
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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context.MarkLabel(lblSlowPath);
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EmitReadVectorFallback(context, address, vector, rt, elem, size);
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context.Branch(lblEnd);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand value = null;
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switch (size)
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{
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case 0:
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value = context.VectorInsert8(vector, context.Load8(physAddr), elem);
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break;
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case 1:
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value = context.VectorInsert16(vector, context.Load16(physAddr), elem);
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break;
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case 2:
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value = context.VectorInsert(vector, context.Load(OperandType.I32, physAddr), elem);
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break;
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case 3:
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value = context.VectorInsert(vector, context.Load(OperandType.I64, physAddr), elem);
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break;
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case 4:
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value = context.Load(OperandType.V128, physAddr);
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break;
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}
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context.Copy(GetVec(rt), value);
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context.MarkLabel(lblEnd);
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}
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private static Operand VectorCreate(ArmEmitterContext context, Operand value)
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{
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return context.VectorInsert(context.VectorZero(), value, 0);
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}
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private static void EmitWriteInt(ArmEmitterContext context, Operand address, int rt, int size)
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{
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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context.MarkLabel(lblSlowPath);
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EmitWriteIntFallback(context, address, rt, size);
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context.Branch(lblEnd);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand value = GetInt(context, rt);
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if (size < 3 && value.Type == OperandType.I64)
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{
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value = context.ConvertI64ToI32(value);
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}
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switch (size)
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{
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case 0: context.Store8 (physAddr, value); break;
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case 1: context.Store16(physAddr, value); break;
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case 2: context.Store (physAddr, value); break;
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case 3: context.Store (physAddr, value); break;
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}
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context.MarkLabel(lblEnd);
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}
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private static void EmitWriteVector(
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ArmEmitterContext context,
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Operand address,
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int rt,
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int elem,
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int size)
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{
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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context.MarkLabel(lblSlowPath);
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EmitWriteVectorFallback(context, address, rt, elem, size);
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context.Branch(lblEnd);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand value = GetVec(rt);
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switch (size)
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{
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case 0:
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context.Store8(physAddr, context.VectorExtract8(value, elem));
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break;
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case 1:
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context.Store16(physAddr, context.VectorExtract16(value, elem));
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break;
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case 2:
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context.Store(physAddr, context.VectorExtract(OperandType.FP32, value, elem));
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break;
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case 3:
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context.Store(physAddr, context.VectorExtract(OperandType.FP64, value, elem));
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break;
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case 4:
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context.Store(physAddr, value);
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break;
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}
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context.MarkLabel(lblEnd);
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}
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private static Operand EmitAddressCheck(ArmEmitterContext context, Operand address, int size)
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{
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long addressCheckMask = ~(context.Memory.AddressSpaceSize - 1);
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addressCheckMask |= (1u << size) - 1;
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return context.BitwiseAnd(address, Const(address.Type, addressCheckMask));
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}
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private static Operand EmitPtPointerLoad(ArmEmitterContext context, Operand address, Operand lblFallbackPath)
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{
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Operand pte = Const(context.Memory.PageTable.ToInt64());
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int bit = MemoryManager.PageBits;
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do
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{
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Operand addrPart = context.ShiftRightUI(address, Const(bit));
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bit += context.Memory.PtLevelBits;
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if (bit < context.Memory.AddressSpaceBits)
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{
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addrPart = context.BitwiseAnd(addrPart, Const(addrPart.Type, context.Memory.PtLevelMask));
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}
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Operand pteOffset = context.ShiftLeft(addrPart, Const(3));
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if (pteOffset.Type == OperandType.I32)
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{
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pteOffset = context.ZeroExtend32(OperandType.I64, pteOffset);
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}
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Operand pteAddress = context.Add(pte, pteOffset);
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pte = context.Load(OperandType.I64, pteAddress);
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}
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while (bit < context.Memory.AddressSpaceBits);
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Operand hasFlagSet = context.BitwiseAnd(pte, Const((long)MemoryManager.PteFlagsMask));
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context.BranchIfTrue(lblFallbackPath, hasFlagSet);
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Operand pageOffset = context.BitwiseAnd(address, Const(address.Type, MemoryManager.PageMask));
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if (pageOffset.Type == OperandType.I32)
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{
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pageOffset = context.ZeroExtend32(OperandType.I64, pageOffset);
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}
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Operand physAddr = context.Add(pte, pageOffset);
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return physAddr;
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}
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private static void EmitReadIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
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{
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Delegate fallbackMethodDlg = null;
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switch (size)
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{
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case 0: fallbackMethodDlg = new _U8_U64 (NativeInterface.ReadByte); break;
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case 1: fallbackMethodDlg = new _U16_U64(NativeInterface.ReadUInt16); break;
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case 2: fallbackMethodDlg = new _U32_U64(NativeInterface.ReadUInt32); break;
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case 3: fallbackMethodDlg = new _U64_U64(NativeInterface.ReadUInt64); break;
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}
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SetInt(context, rt, context.Call(fallbackMethodDlg, address));
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}
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private static void EmitReadVectorFallback(
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ArmEmitterContext context,
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Operand address,
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Operand vector,
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int rt,
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int elem,
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int size)
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{
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Delegate fallbackMethodDlg = null;
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switch (size)
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{
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case 0: fallbackMethodDlg = new _U8_U64 (NativeInterface.ReadByte); break;
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case 1: fallbackMethodDlg = new _U16_U64 (NativeInterface.ReadUInt16); break;
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case 2: fallbackMethodDlg = new _U32_U64 (NativeInterface.ReadUInt32); break;
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case 3: fallbackMethodDlg = new _U64_U64 (NativeInterface.ReadUInt64); break;
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case 4: fallbackMethodDlg = new _V128_U64(NativeInterface.ReadVector128); break;
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}
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Operand value = context.Call(fallbackMethodDlg, address);
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switch (size)
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{
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case 0: value = context.VectorInsert8 (vector, value, elem); break;
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case 1: value = context.VectorInsert16(vector, value, elem); break;
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case 2: value = context.VectorInsert (vector, value, elem); break;
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case 3: value = context.VectorInsert (vector, value, elem); break;
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}
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context.Copy(GetVec(rt), value);
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}
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private static void EmitWriteIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
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{
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Delegate fallbackMethodDlg = null;
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switch (size)
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{
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case 0: fallbackMethodDlg = new _Void_U64_U8 (NativeInterface.WriteByte); break;
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case 1: fallbackMethodDlg = new _Void_U64_U16(NativeInterface.WriteUInt16); break;
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case 2: fallbackMethodDlg = new _Void_U64_U32(NativeInterface.WriteUInt32); break;
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case 3: fallbackMethodDlg = new _Void_U64_U64(NativeInterface.WriteUInt64); break;
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}
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Operand value = GetInt(context, rt);
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if (size < 3 && value.Type == OperandType.I64)
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{
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value = context.ConvertI64ToI32(value);
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}
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context.Call(fallbackMethodDlg, address, value);
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}
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private static void EmitWriteVectorFallback(
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ArmEmitterContext context,
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Operand address,
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int rt,
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int elem,
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int size)
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{
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Delegate fallbackMethodDlg = null;
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switch (size)
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{
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case 0: fallbackMethodDlg = new _Void_U64_U8 (NativeInterface.WriteByte); break;
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case 1: fallbackMethodDlg = new _Void_U64_U16 (NativeInterface.WriteUInt16); break;
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case 2: fallbackMethodDlg = new _Void_U64_U32 (NativeInterface.WriteUInt32); break;
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case 3: fallbackMethodDlg = new _Void_U64_U64 (NativeInterface.WriteUInt64); break;
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case 4: fallbackMethodDlg = new _Void_U64_V128(NativeInterface.WriteVector128); break;
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}
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Operand value = null;
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if (size < 4)
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{
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switch (size)
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{
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case 0:
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value = context.VectorExtract8(GetVec(rt), elem);
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break;
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case 1:
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value = context.VectorExtract16(GetVec(rt), elem);
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break;
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case 2:
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value = context.VectorExtract(OperandType.I32, GetVec(rt), elem);
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break;
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case 3:
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value = context.VectorExtract(OperandType.I64, GetVec(rt), elem);
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break;
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}
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}
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else
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{
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value = GetVec(rt);
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}
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context.Call(fallbackMethodDlg, address, value);
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}
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private static Operand GetInt(ArmEmitterContext context, int rt)
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{
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return context.CurrOp is OpCode32 ? GetIntA32(context, rt) : GetIntOrZR(context, rt);
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}
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private static void SetInt(ArmEmitterContext context, int rt, Operand value)
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{
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if (context.CurrOp is OpCode32)
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{
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SetIntA32(context, rt, value);
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}
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else
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{
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SetIntOrZR(context, rt, value);
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}
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}
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// ARM32 helpers.
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public static Operand GetMemM(ArmEmitterContext context, bool setCarry = true)
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|
{
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|
switch (context.CurrOp)
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|
{
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case OpCode32MemRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
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|
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case OpCode32MemReg op: return GetIntA32(context, op.Rm);
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|
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case OpCode32Mem op: return Const(op.Immediate);
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|
|
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case OpCode32SimdMemImm op: return Const(op.Immediate);
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|
|
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default: throw InvalidOpCodeType(context.CurrOp);
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|
}
|
|
}
|
|
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private static Exception InvalidOpCodeType(OpCode opCode)
|
|
{
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|
return new InvalidOperationException($"Invalid OpCode type \"{opCode?.GetType().Name ?? "null"}\".");
|
|
}
|
|
|
|
public static Operand GetMShiftedByImmediate(ArmEmitterContext context, OpCode32MemRsImm op, bool setCarry)
|
|
{
|
|
Operand m = GetIntA32(context, op.Rm);
|
|
|
|
int shift = op.Immediate;
|
|
|
|
if (shift == 0)
|
|
{
|
|
switch (op.ShiftType)
|
|
{
|
|
case ShiftType.Lsr: shift = 32; break;
|
|
case ShiftType.Asr: shift = 32; break;
|
|
case ShiftType.Ror: shift = 1; break;
|
|
}
|
|
}
|
|
|
|
if (shift != 0)
|
|
{
|
|
setCarry &= false;
|
|
|
|
switch (op.ShiftType)
|
|
{
|
|
case ShiftType.Lsl: m = InstEmitAluHelper.GetLslC(context, m, setCarry, shift); break;
|
|
case ShiftType.Lsr: m = InstEmitAluHelper.GetLsrC(context, m, setCarry, shift); break;
|
|
case ShiftType.Asr: m = InstEmitAluHelper.GetAsrC(context, m, setCarry, shift); break;
|
|
case ShiftType.Ror:
|
|
if (op.Immediate != 0)
|
|
{
|
|
m = InstEmitAluHelper.GetRorC(context, m, setCarry, shift);
|
|
}
|
|
else
|
|
{
|
|
m = InstEmitAluHelper.GetRrxC(context, m, setCarry);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
return m;
|
|
}
|
|
}
|
|
} |