mirror of
https://github.com/GreemDev/Ryujinx.git
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e674b37710
* Update CpuTest.cs * Update CpuTestSimd.cs * Superseded. * Update AInstEmitSimdCvt.cs * Update ASoftFloat.cs * Nit. * Update PackageReferences. * Update AInstEmitSimdArithmetic.cs * Update AVectorHelper.cs * Update ASoftFloat.cs * Update ASoftFallback.cs * Update AThreadState.cs * Create FPType.cs * Create FPExc.cs * Create FPCR.cs * Create FPSR.cs * Update ARoundMode.cs * Update APState.cs * Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover. * Nits.
164 lines
4.5 KiB
C#
164 lines
4.5 KiB
C#
using ChocolArm64.Events;
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using System;
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using System.Diagnostics;
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using System.Runtime.CompilerServices;
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using System.Runtime.Intrinsics;
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namespace ChocolArm64.State
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{
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public class AThreadState
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{
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internal const int LRIndex = 30;
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internal const int ZRIndex = 31;
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internal const int ErgSizeLog2 = 4;
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internal const int DczSizeLog2 = 4;
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private const int MinInstForCheck = 4000000;
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internal AExecutionMode ExecutionMode;
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//AArch32 state.
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public uint R0, R1, R2, R3,
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R4, R5, R6, R7,
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R8, R9, R10, R11,
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R12, R13, R14, R15;
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public bool Thumb;
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//AArch64 state.
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public ulong X0, X1, X2, X3, X4, X5, X6, X7,
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X8, X9, X10, X11, X12, X13, X14, X15,
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X16, X17, X18, X19, X20, X21, X22, X23,
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X24, X25, X26, X27, X28, X29, X30, X31;
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public Vector128<float> V0, V1, V2, V3, V4, V5, V6, V7,
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V8, V9, V10, V11, V12, V13, V14, V15,
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V16, V17, V18, V19, V20, V21, V22, V23,
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V24, V25, V26, V27, V28, V29, V30, V31;
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public bool Overflow;
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public bool Carry;
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public bool Zero;
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public bool Negative;
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public bool Running { get; set; }
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public int Core { get; set; }
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private bool Interrupted;
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private int SyncCount;
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public long TpidrEl0 { get; set; }
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public long Tpidr { get; set; }
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public int Fpcr { get; set; }
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public int Fpsr { get; set; }
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public int Psr
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{
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get
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{
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return (Negative ? (int)APState.N : 0) |
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(Zero ? (int)APState.Z : 0) |
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(Carry ? (int)APState.C : 0) |
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(Overflow ? (int)APState.V : 0);
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}
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}
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public uint CtrEl0 => 0x8444c004;
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public uint DczidEl0 => 0x00000004;
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public ulong CntfrqEl0 { get; set; }
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public ulong CntpctEl0
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{
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get
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{
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double Ticks = TickCounter.ElapsedTicks * HostTickFreq;
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return (ulong)(Ticks * CntfrqEl0);
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}
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}
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public event EventHandler<EventArgs> Interrupt;
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public event EventHandler<AInstExceptionEventArgs> Break;
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public event EventHandler<AInstExceptionEventArgs> SvcCall;
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public event EventHandler<AInstUndefinedEventArgs> Undefined;
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private static Stopwatch TickCounter;
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private static double HostTickFreq;
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static AThreadState()
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{
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HostTickFreq = 1.0 / Stopwatch.Frequency;
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TickCounter = new Stopwatch();
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TickCounter.Start();
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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internal bool Synchronize(int BbWeight)
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{
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//Firing a interrupt frequently is expensive, so we only
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//do it after a given number of instructions has executed.
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SyncCount += BbWeight;
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if (SyncCount >= MinInstForCheck)
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{
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CheckInterrupt();
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}
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return Running;
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}
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internal void RequestInterrupt()
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{
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Interrupted = true;
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}
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[MethodImpl(MethodImplOptions.NoInlining)]
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private void CheckInterrupt()
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{
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SyncCount = 0;
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if (Interrupted)
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{
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Interrupted = false;
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Interrupt?.Invoke(this, EventArgs.Empty);
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}
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}
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internal void OnBreak(long Position, int Imm)
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{
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Break?.Invoke(this, new AInstExceptionEventArgs(Position, Imm));
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}
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internal void OnSvcCall(long Position, int Imm)
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{
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SvcCall?.Invoke(this, new AInstExceptionEventArgs(Position, Imm));
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}
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internal void OnUndefined(long Position, int RawOpCode)
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{
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Undefined?.Invoke(this, new AInstUndefinedEventArgs(Position, RawOpCode));
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}
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internal bool GetFpcrFlag(FPCR Flag)
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{
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return (Fpcr & (1 << (int)Flag)) != 0;
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}
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internal void SetFpsrFlag(FPSR Flag)
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{
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Fpsr |= 1 << (int)Flag;
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}
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internal ARoundMode FPRoundingMode()
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{
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return (ARoundMode)((Fpcr >> (int)FPCR.RMode) & 3);
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}
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}
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}
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