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ryujinx-final/Ryujinx/Cpu/Decoder/AOpCodeSimdReg.cs

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using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeSimdReg : AOpCodeSimd
{
public bool Bit3 { get; private set; }
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public int Ra { get; private set; }
public int Rm { get; private set; }
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public AOpCodeSimdReg(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Bit3 = ((OpCode >> 3) & 0x1) != 0;
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Ra = (OpCode >> 10) & 0x1f;
Rm = (OpCode >> 16) & 0x1f;
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}
}
}