720 lines
22 KiB
C#
720 lines
22 KiB
C#
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using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitSimdHelperArm64
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{
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public static void EmitScalarUnaryOpF(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n));
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}
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public static void EmitScalarUnaryOpFFromGp(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n));
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}
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public static void EmitScalarUnaryOpFToGp(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
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Operand n = GetVec(op.Rn);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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SetIntOrZR(context, op.Rd, op.RegisterSize == RegisterSize.Int32
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? context.AddIntrinsicInt (inst, n)
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: context.AddIntrinsicLong(inst, n));
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}
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public static void EmitScalarBinaryOpF(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, m));
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}
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public static void EmitScalarBinaryOpFByElem(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, m, Const(op.Index)));
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}
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public static void EmitScalarTernaryOpF(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand a = GetVec(op.Ra);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, a, n, m));
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}
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public static void EmitScalarTernaryOpFRdByElem(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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context.Copy(d, context.AddIntrinsic(inst, d, n, m, Const(op.Index)));
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}
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public static void EmitScalarUnaryOp(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n));
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}
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public static void EmitScalarBinaryOp(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, m));
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}
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public static void EmitScalarBinaryOpRd(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, d, n));
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}
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public static void EmitScalarTernaryOpRd(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
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context.Copy(d, context.AddIntrinsic(inst, d, n, m));
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}
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public static void EmitScalarShiftBinaryOp(ArmEmitterContext context, Intrinsic inst, int shift)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, Const(shift)));
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}
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public static void EmitScalarShiftTernaryOpRd(ArmEmitterContext context, Intrinsic inst, int shift)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, d, n, Const(shift)));
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}
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public static void EmitScalarSaturatingShiftTernaryOpRd(ArmEmitterContext context, Intrinsic inst, int shift)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, d, n, Const(shift)));
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context.SetPendingQcFlagSync();
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}
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public static void EmitScalarSaturatingUnaryOp(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
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Operand result = context.AddIntrinsic(inst, n);
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context.Copy(GetVec(op.Rd), result);
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context.SetPendingQcFlagSync();
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}
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public static void EmitScalarSaturatingBinaryOp(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
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Operand result = context.AddIntrinsic(inst, n, m);
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context.Copy(GetVec(op.Rd), result);
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context.SetPendingQcFlagSync();
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}
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public static void EmitScalarSaturatingBinaryOpRd(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
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Operand result = context.AddIntrinsic(inst, d, n);
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context.Copy(GetVec(op.Rd), result);
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context.SetPendingQcFlagSync();
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}
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public static void EmitScalarConvertBinaryOpF(ArmEmitterContext context, Intrinsic inst, int fBits)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, Const(fBits)));
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}
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public static void EmitScalarConvertBinaryOpFFromGp(ArmEmitterContext context, Intrinsic inst, int fBits)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, Const(fBits)));
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}
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public static void EmitScalarConvertBinaryOpFToGp(ArmEmitterContext context, Intrinsic inst, int fBits)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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SetIntOrZR(context, op.Rd, op.RegisterSize == RegisterSize.Int32
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? context.AddIntrinsicInt (inst, n, Const(fBits))
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: context.AddIntrinsicLong(inst, n, Const(fBits)));
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}
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public static void EmitVectorUnaryOpF(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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if (op.RegisterSize == RegisterSize.Simd128)
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{
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inst |= Intrinsic.Arm64V128;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n));
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}
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public static void EmitVectorBinaryOpF(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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if (op.RegisterSize == RegisterSize.Simd128)
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{
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inst |= Intrinsic.Arm64V128;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, m));
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}
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public static void EmitVectorBinaryOpFRd(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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if (op.RegisterSize == RegisterSize.Simd128)
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{
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inst |= Intrinsic.Arm64V128;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, d, n));
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}
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public static void EmitVectorBinaryOpFByElem(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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if ((op.Size & 1) != 0)
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{
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inst |= Intrinsic.Arm64VDouble;
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}
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if (op.RegisterSize == RegisterSize.Simd128)
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{
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inst |= Intrinsic.Arm64V128;
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}
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, m, Const(op.Index)));
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}
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public static void EmitVectorTernaryOpFRd(ArmEmitterContext context, Intrinsic inst)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
|
||
|
|
Operand m = GetVec(op.Rm);
|
||
|
|
|
||
|
|
if ((op.Size & 1) != 0)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64VDouble;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(d, context.AddIntrinsic(inst, d, n, m));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorTernaryOpFRdByElem(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp;
|
||
|
|
|
||
|
|
Operand d = GetVec(op.Rd);
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
Operand m = GetVec(op.Rm);
|
||
|
|
|
||
|
|
if ((op.Size & 1) != 0)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64VDouble;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(d, context.AddIntrinsic(inst, d, n, m, Const(op.Index)));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorUnaryOp(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
||
|
|
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorBinaryOp(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
|
||
|
|
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
Operand m = GetVec(op.Rm);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, m));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorBinaryOpRd(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
||
|
|
|
||
|
|
Operand d = GetVec(op.Rd);
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, d, n));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorBinaryOpByElem(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
|
||
|
|
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
Operand m = GetVec(op.Rm);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, m, Const(op.Index)));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorTernaryOpRd(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
|
||
|
|
|
||
|
|
Operand d = GetVec(op.Rd);
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
Operand m = GetVec(op.Rm);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(d, context.AddIntrinsic(inst, d, n, m));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorTernaryOpRdByElem(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
|
||
|
|
|
||
|
|
Operand d = GetVec(op.Rd);
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
Operand m = GetVec(op.Rm);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(d, context.AddIntrinsic(inst, d, n, m, Const(op.Index)));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorShiftBinaryOp(ArmEmitterContext context, Intrinsic inst, int shift)
|
||
|
|
{
|
||
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
||
|
|
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, Const(shift)));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorShiftTernaryOpRd(ArmEmitterContext context, Intrinsic inst, int shift)
|
||
|
|
{
|
||
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
||
|
|
|
||
|
|
Operand d = GetVec(op.Rd);
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, d, n, Const(shift)));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorSaturatingShiftTernaryOpRd(ArmEmitterContext context, Intrinsic inst, int shift)
|
||
|
|
{
|
||
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
||
|
|
|
||
|
|
Operand d = GetVec(op.Rd);
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, d, n, Const(shift)));
|
||
|
|
|
||
|
|
context.SetPendingQcFlagSync();
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorSaturatingUnaryOp(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
||
|
|
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
Operand result = context.AddIntrinsic(inst, n);
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), result);
|
||
|
|
|
||
|
|
context.SetPendingQcFlagSync();
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorSaturatingBinaryOp(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
|
||
|
|
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
Operand m = GetVec(op.Rm);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
Operand result = context.AddIntrinsic(inst, n, m);
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), result);
|
||
|
|
|
||
|
|
context.SetPendingQcFlagSync();
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorSaturatingBinaryOpRd(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
||
|
|
|
||
|
|
Operand d = GetVec(op.Rd);
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
Operand result = context.AddIntrinsic(inst, d, n);
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), result);
|
||
|
|
|
||
|
|
context.SetPendingQcFlagSync();
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorSaturatingBinaryOpByElem(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp;
|
||
|
|
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
Operand m = GetVec(op.Rm);
|
||
|
|
|
||
|
|
inst |= (Intrinsic)(op.Size << (int)Intrinsic.Arm64VSizeShift);
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
Operand result = context.AddIntrinsic(inst, n, m, Const(op.Index));
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), result);
|
||
|
|
|
||
|
|
context.SetPendingQcFlagSync();
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorConvertBinaryOpF(ArmEmitterContext context, Intrinsic inst, int fBits)
|
||
|
|
{
|
||
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
||
|
|
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
|
||
|
|
if ((op.Size & 1) != 0)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64VDouble;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, n, Const(fBits)));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitVectorLookupTable(ArmEmitterContext context, Intrinsic inst)
|
||
|
|
{
|
||
|
|
OpCodeSimdTbl op = (OpCodeSimdTbl)context.CurrOp;
|
||
|
|
|
||
|
|
Operand[] operands = new Operand[op.Size + 1];
|
||
|
|
|
||
|
|
operands[op.Size] = GetVec(op.Rm);
|
||
|
|
|
||
|
|
for (int index = 0; index < op.Size; index++)
|
||
|
|
{
|
||
|
|
operands[index] = GetVec((op.Rn + index) & 0x1F);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64V128;
|
||
|
|
}
|
||
|
|
|
||
|
|
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst, operands));
|
||
|
|
}
|
||
|
|
|
||
|
|
public static void EmitFcmpOrFcmpe(ArmEmitterContext context, bool signalNaNs)
|
||
|
|
{
|
||
|
|
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
|
||
|
|
|
||
|
|
bool cmpWithZero = !(op is OpCodeSimdFcond) ? op.Bit3 : false;
|
||
|
|
|
||
|
|
Intrinsic inst = signalNaNs ? Intrinsic.Arm64FcmpeS : Intrinsic.Arm64FcmpS;
|
||
|
|
|
||
|
|
if ((op.Size & 1) != 0)
|
||
|
|
{
|
||
|
|
inst |= Intrinsic.Arm64VDouble;
|
||
|
|
}
|
||
|
|
|
||
|
|
Operand n = GetVec(op.Rn);
|
||
|
|
Operand m = cmpWithZero ? Const(0) : GetVec(op.Rm);
|
||
|
|
|
||
|
|
Operand nzcv = context.AddIntrinsicInt(inst, n, m);
|
||
|
|
|
||
|
|
Operand one = Const(1);
|
||
|
|
|
||
|
|
SetFlag(context, PState.VFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const(28)), one));
|
||
|
|
SetFlag(context, PState.CFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const(29)), one));
|
||
|
|
SetFlag(context, PState.ZFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const(30)), one));
|
||
|
|
SetFlag(context, PState.NFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const(31)), one));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|