From 0181068016bc9ca98ee71f1d7b6ab6010c4302f0 Mon Sep 17 00:00:00 2001
From: FICTURE7 <FICTURE7@gmail.com>
Date: Thu, 20 May 2021 16:09:17 +0400
Subject: [PATCH] Add `BIC/ORR Vd.T, #imm` fast path (#2279)

* Add fast path for BIC Vd.T, #imm

* Add fast path for ORR Vd.T, #imm

* Set PTC version

* Fixup Exception to InvalidOperationException
---
 .../Instructions/InstEmitSimdHelper.cs        |  9 +++
 .../Instructions/InstEmitSimdLogical.cs       | 59 +++++++++++++++++--
 ARMeilleure/Translation/PTC/Ptc.cs            |  2 +-
 3 files changed, 65 insertions(+), 5 deletions(-)

diff --git a/ARMeilleure/Instructions/InstEmitSimdHelper.cs b/ARMeilleure/Instructions/InstEmitSimdHelper.cs
index 576f4229..36602f25 100644
--- a/ARMeilleure/Instructions/InstEmitSimdHelper.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdHelper.cs
@@ -190,6 +190,15 @@ namespace ARMeilleure.Instructions
             return X86GetAllElements(context, BitConverter.DoubleToInt64Bits(value));
         }
 
+        public static Operand X86GetAllElements(ArmEmitterContext context, short value)
+        {
+            ulong value1 = (ushort)value;
+            ulong value2 = value1 << 16 | value1;
+            ulong value4 = value2 << 32 | value2;
+
+            return X86GetAllElements(context, (long)value4);
+        }
+
         public static Operand X86GetAllElements(ArmEmitterContext context, int value)
         {
             Operand vector = context.VectorCreateScalar(Const(value));
diff --git a/ARMeilleure/Instructions/InstEmitSimdLogical.cs b/ARMeilleure/Instructions/InstEmitSimdLogical.cs
index 362296f7..52a9a576 100644
--- a/ARMeilleure/Instructions/InstEmitSimdLogical.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdLogical.cs
@@ -1,6 +1,7 @@
 using ARMeilleure.Decoders;
 using ARMeilleure.IntermediateRepresentation;
 using ARMeilleure.Translation;
+using System;
 using System.Diagnostics;
 
 using static ARMeilleure.Instructions.InstEmitHelper;
@@ -64,10 +65,35 @@ namespace ARMeilleure.Instructions
 
         public static void Bic_Vi(ArmEmitterContext context)
         {
-            EmitVectorImmBinaryOp(context, (op1, op2) =>
+            if (Optimizations.UseSse2)
             {
-                return context.BitwiseAnd(op1, context.BitwiseNot(op2));
-            });
+                OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
+
+                int eSize = 8 << op.Size;
+
+                Operand d = GetVec(op.Rd);
+                Operand imm = eSize switch {
+                    16 => X86GetAllElements(context, (short)~op.Immediate),
+                    32 => X86GetAllElements(context, (int)~op.Immediate),
+                    _ => throw new InvalidOperationException($"Invalid element size {eSize}.")
+                };
+
+                Operand res = context.AddIntrinsic(Intrinsic.X86Pand, d, imm);
+
+                if (op.RegisterSize == RegisterSize.Simd64)
+                {
+                    res = context.VectorZeroUpper64(res);
+                }
+
+                context.Copy(GetVec(op.Rd), res);
+            }
+            else
+            {
+                EmitVectorImmBinaryOp(context, (op1, op2) =>
+                {
+                    return context.BitwiseAnd(op1, context.BitwiseNot(op2));
+                });
+            }
         }
 
         public static void Bif_V(ArmEmitterContext context)
@@ -278,7 +304,32 @@ namespace ARMeilleure.Instructions
 
         public static void Orr_Vi(ArmEmitterContext context)
         {
-            EmitVectorImmBinaryOp(context, (op1, op2) => context.BitwiseOr(op1, op2));
+            if (Optimizations.UseSse2)
+            {
+                OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
+
+                int eSize = 8 << op.Size;
+
+                Operand d = GetVec(op.Rd);
+                Operand imm = eSize switch {
+                    16 => X86GetAllElements(context, (short)op.Immediate),
+                    32 => X86GetAllElements(context, (int)op.Immediate),
+                    _ => throw new InvalidOperationException($"Invalid element size {eSize}.")
+                };
+
+                Operand res = context.AddIntrinsic(Intrinsic.X86Por, d, imm);
+
+                if (op.RegisterSize == RegisterSize.Simd64)
+                {
+                    res = context.VectorZeroUpper64(res);
+                }
+
+                context.Copy(GetVec(op.Rd), res);
+            }
+            else
+            {
+                EmitVectorImmBinaryOp(context, (op1, op2) => context.BitwiseOr(op1, op2));
+            }
         }
 
         public static void Rbit_V(ArmEmitterContext context)
diff --git a/ARMeilleure/Translation/PTC/Ptc.cs b/ARMeilleure/Translation/PTC/Ptc.cs
index 1bb8659c..a61cf5b7 100644
--- a/ARMeilleure/Translation/PTC/Ptc.cs
+++ b/ARMeilleure/Translation/PTC/Ptc.cs
@@ -28,7 +28,7 @@ namespace ARMeilleure.Translation.PTC
         private const string OuterHeaderMagicString = "PTCohd\0\0";
         private const string InnerHeaderMagicString = "PTCihd\0\0";
 
-        private const uint InternalVersion = 2285; //! To be incremented manually for each change to the ARMeilleure project.
+        private const uint InternalVersion = 2279; //! To be incremented manually for each change to the ARMeilleure project.
 
         private const string ActualDir = "0";
         private const string BackupDir = "1";