From 0ac4681fa06cac24b14bff45f334f453baf74934 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Fri, 30 Mar 2018 23:32:06 -0300
Subject: [PATCH] Fix 32-bits extended register instructions with 64-bits
 extensions

---
 ChocolArm64/Translation/AILEmitterCtx.cs | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/ChocolArm64/Translation/AILEmitterCtx.cs b/ChocolArm64/Translation/AILEmitterCtx.cs
index 46659469..03b06610 100644
--- a/ChocolArm64/Translation/AILEmitterCtx.cs
+++ b/ChocolArm64/Translation/AILEmitterCtx.cs
@@ -72,7 +72,7 @@ namespace ChocolArm64.Translation
 
             Emitter = new AILEmitter(Graph, Root, SubName);
 
-            ILBlock = Emitter.GetILBlock(0);          
+            ILBlock = Emitter.GetILBlock(0);
 
             OpcIndex = -1;
 
@@ -260,18 +260,24 @@ namespace ChocolArm64.Translation
                 case AIntType.Int64:  Emit(OpCodes.Conv_I8); break;
             }
 
-            if (IntType == AIntType.UInt64 ||
-                IntType == AIntType.Int64)
+            bool Sz64 = CurrOp.RegisterSize != ARegisterSize.Int32;
+
+            if (Sz64 == (IntType == AIntType.UInt64 ||
+                         IntType == AIntType.Int64))
             {
                 return;
             }
 
-            if (CurrOp.RegisterSize != ARegisterSize.Int32)
+            if (Sz64)
             {
                 Emit(IntType >= AIntType.Int8
                     ? OpCodes.Conv_I8
                     : OpCodes.Conv_U8);
             }
+            else
+            {
+                Emit(OpCodes.Conv_U4);
+            }
         }
 
         public void EmitLsl(int Amount) => EmitILShift(Amount, OpCodes.Shl);
@@ -298,7 +304,7 @@ namespace ChocolArm64.Translation
                 EmitLdc_I4(Amount);
 
                 Emit(OpCodes.Shr_Un);
-                
+
                 Ldloc(Tmp2Index, AIoType.Int);
 
                 EmitLdc_I4(CurrOp.GetBitsCount() - Amount);