From 0e343a748d9dcfe50b885b8c0c5e886bc44080ac Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Mon, 5 Mar 2018 12:58:19 -0300
Subject: [PATCH] Add FCVTL and FCVTN instruction (no Half support yet), stub
 SvcClearEvent

---
 ChocolArm64/AOpCodeTable.cs                 |  2 +
 ChocolArm64/Instruction/AInstEmitSimdCvt.cs | 60 +++++++++++++++++++++
 Ryujinx.Core/OsHle/Svc/SvcHandler.cs        |  1 +
 Ryujinx.Core/OsHle/Svc/SvcSystem.cs         |  9 ++++
 4 files changed, 72 insertions(+)

diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs
index e192f5ec..5db495af 100644
--- a/ChocolArm64/AOpCodeTable.cs
+++ b/ChocolArm64/AOpCodeTable.cs
@@ -161,8 +161,10 @@ namespace ChocolArm64
             Set("000111100x10001xx10000xxxxxxxxxx", AInstEmit.Fcvt_S,        typeof(AOpCodeSimd));
             Set("x00111100x100100000000xxxxxxxxxx", AInstEmit.Fcvtas_Gp,     typeof(AOpCodeSimdCvt));
             Set("x00111100x100101000000xxxxxxxxxx", AInstEmit.Fcvtau_Gp,     typeof(AOpCodeSimdCvt));
+            Set("0x0011100x100001011110xxxxxxxxxx", AInstEmit.Fcvtl_V,       typeof(AOpCodeSimd));
             Set("x00111100x110000000000xxxxxxxxxx", AInstEmit.Fcvtms_Gp,     typeof(AOpCodeSimdCvt));
             Set("x00111100x110001000000xxxxxxxxxx", AInstEmit.Fcvtmu_Gp,     typeof(AOpCodeSimdCvt));
+            Set("0x0011100x100001011010xxxxxxxxxx", AInstEmit.Fcvtn_V,       typeof(AOpCodeSimd));
             Set("x00111100x101000000000xxxxxxxxxx", AInstEmit.Fcvtps_Gp,     typeof(AOpCodeSimdCvt));
             Set("x00111100x101001000000xxxxxxxxxx", AInstEmit.Fcvtpu_Gp,     typeof(AOpCodeSimdCvt));
             Set("x00111100x111000000000xxxxxxxxxx", AInstEmit.Fcvtzs_Gp,     typeof(AOpCodeSimdCvt));
diff --git a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs
index 688f05a2..e9702777 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs
@@ -31,6 +31,36 @@ namespace ChocolArm64.Instruction
             EmitFcvt_u_Gp(Context, () => EmitRoundMathCall(Context, MidpointRounding.AwayFromZero));
         }
 
+        public static void Fcvtl_V(AILEmitterCtx Context)
+        {
+            AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
+
+            int SizeF = Op.Size & 1;
+
+            int Elems = 4 >> SizeF;
+
+            int Part = Context.CurrOp.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
+
+            for (int Index = 0; Index < Elems; Index++)
+            {
+                if (SizeF == 0)
+                {
+                    //TODO: This need the half precision floating point type,
+                    //that is not yet supported on .NET. We should probably
+                    //do our own implementation on the meantime.
+                    throw new NotImplementedException();
+                }
+                else /* if (SizeF == 1) */
+                {
+                    EmitVectorExtractF(Context, Op.Rn, Part + Index, 0);
+
+                    Context.Emit(OpCodes.Conv_R8);
+                }
+
+                EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
+            }
+        }
+
         public static void Fcvtms_Gp(AILEmitterCtx Context)
         {
             EmitFcvt_s_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Floor)));
@@ -41,6 +71,36 @@ namespace ChocolArm64.Instruction
             EmitFcvt_u_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Floor)));
         }
 
+        public static void Fcvtn_V(AILEmitterCtx Context)
+        {
+            AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
+
+            int SizeF = Op.Size & 1;
+
+            int Elems = 4 >> SizeF;
+
+            int Part = Context.CurrOp.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
+
+            for (int Index = 0; Index < Elems; Index++)
+            {
+                EmitVectorExtractF(Context, Op.Rd, Index, SizeF);
+
+                if (SizeF == 0)
+                {
+                    //TODO: This need the half precision floating point type,
+                    //that is not yet supported on .NET. We should probably
+                    //do our own implementation on the meantime.
+                    throw new NotImplementedException();
+                }
+                else /* if (SizeF == 1) */
+                {
+                    Context.Emit(OpCodes.Conv_R4);
+
+                    EmitVectorInsertF(Context, Op.Rd, Part + Index, 0);
+                }
+            }
+        }
+
         public static void Fcvtps_Gp(AILEmitterCtx Context)
         {
             EmitFcvt_s_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Ceiling)));
diff --git a/Ryujinx.Core/OsHle/Svc/SvcHandler.cs b/Ryujinx.Core/OsHle/Svc/SvcHandler.cs
index 212d30a6..b3e6262d 100644
--- a/Ryujinx.Core/OsHle/Svc/SvcHandler.cs
+++ b/Ryujinx.Core/OsHle/Svc/SvcHandler.cs
@@ -36,6 +36,7 @@ namespace Ryujinx.Core.OsHle.Svc
                 { 0x0c, SvcGetThreadPriority             },
                 { 0x0d, SvcSetThreadPriority             },
                 { 0x0f, SvcSetThreadCoreMask             },
+                { 0x12, SvcClearEvent                    },
                 { 0x13, SvcMapSharedMemory               },
                 { 0x14, SvcUnmapSharedMemory             },
                 { 0x15, SvcCreateTransferMemory          },
diff --git a/Ryujinx.Core/OsHle/Svc/SvcSystem.cs b/Ryujinx.Core/OsHle/Svc/SvcSystem.cs
index 51b2e26c..d0459f2f 100644
--- a/Ryujinx.Core/OsHle/Svc/SvcSystem.cs
+++ b/Ryujinx.Core/OsHle/Svc/SvcSystem.cs
@@ -20,6 +20,15 @@ namespace Ryujinx.Core.OsHle.Svc
             Ns.Os.ExitProcess(ThreadState.ProcessId);
         }
 
+        private void SvcClearEvent(AThreadState ThreadState)
+        {
+            int Handle = (int)ThreadState.X0;
+
+            //TODO: Implement events.
+
+            ThreadState.X0 = (int)SvcResult.Success;
+        }
+
         private void SvcCloseHandle(AThreadState ThreadState)
         {
             int Handle = (int)ThreadState.X0;