From 36d9130592c7d45d50d9748f816b282c05e45967 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Fri, 6 Apr 2018 01:41:54 -0300
Subject: [PATCH] Add FMLS (vector) instruction

---
 ChocolArm64/AOpCodeTable.cs                   |  2 ++
 .../Instruction/AInstEmitSimdArithmetic.cs    | 18 +++++++++++++++++
 ChocolArm64/Instruction/AInstEmitSimdCmp.cs   | 20 -------------------
 3 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs
index 483594e2..b323a112 100644
--- a/ChocolArm64/AOpCodeTable.cs
+++ b/ChocolArm64/AOpCodeTable.cs
@@ -213,6 +213,8 @@ namespace ChocolArm64
             Set("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S,      typeof(AOpCodeSimdReg));
             Set("0>0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V,        typeof(AOpCodeSimdReg));
             Set("0x0011111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Ve,       typeof(AOpCodeSimdRegElemF));
+            Set("0>0011101<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmls_V,        typeof(AOpCodeSimdReg));
+            Set("0x0011111<<xxxxx0101x0xxxxxxxxxx", AInstEmit.Fmls_Ve,       typeof(AOpCodeSimdRegElemF));
             Set("000111100x100000010000xxxxxxxxxx", AInstEmit.Fmov_S,        typeof(AOpCodeSimd));
             Set("00011110xx1xxxxxxxx100xxxxxxxxxx", AInstEmit.Fmov_Si,       typeof(AOpCodeSimdFmov));
             Set("0xx0111100000xxx111101xxxxxxxxxx", AInstEmit.Fmov_V,        typeof(AOpCodeSimdImm));
diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
index 9fb33878..772b7955 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
@@ -224,6 +224,24 @@ namespace ChocolArm64.Instruction
             });
         }
 
+        public static void Fmls_V(AILEmitterCtx Context)
+        {
+            EmitVectorTernaryOpF(Context, () =>
+            {
+                Context.Emit(OpCodes.Mul);
+                Context.Emit(OpCodes.Sub);
+            });
+        }
+
+        public static void Fmls_Ve(AILEmitterCtx Context)
+        {
+            EmitVectorTernaryOpByElemF(Context, () =>
+            {
+                Context.Emit(OpCodes.Mul);
+                Context.Emit(OpCodes.Sub);
+            });
+        }
+
         public static void Fmsub_S(AILEmitterCtx Context)
         {
             EmitScalarTernaryRaOpF(Context, () =>
diff --git a/ChocolArm64/Instruction/AInstEmitSimdCmp.cs b/ChocolArm64/Instruction/AInstEmitSimdCmp.cs
index 43e8e949..a71b6d42 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdCmp.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdCmp.cs
@@ -140,26 +140,6 @@ namespace ChocolArm64.Instruction
             EmitVectorFcmp(Context, OpCodes.Bgt_S);
         }
 
-        public static void Fcmhi_S(AILEmitterCtx Context)
-        {
-            EmitScalarFcmp(Context, OpCodes.Bgt_Un_S);
-        }
-
-        public static void Fcmhi_V(AILEmitterCtx Context)
-        {
-            EmitVectorFcmp(Context, OpCodes.Bgt_Un_S);
-        }
-
-        public static void Fcmhs_S(AILEmitterCtx Context)
-        {
-            EmitScalarFcmp(Context, OpCodes.Bge_Un_S);
-        }
-
-        public static void Fcmhs_V(AILEmitterCtx Context)
-        {
-            EmitVectorFcmp(Context, OpCodes.Bge_Un_S);
-        }
-
         public static void Fcmle_S(AILEmitterCtx Context)
         {
             EmitScalarFcmp(Context, OpCodes.Ble_S);