emu-mirrors/ryujinx-final
Archived
0
0
Fork 0
Code Activity

Optimization | Modify Add (Integer) Instruction to use LEA instead. (#1971)

Browse source 
* Optimization | Modify Add Instruction to use LEA instead.

Currently, the add instruction requires 4 registers to take place. By using LEA, we can effectively perform the same working using 3 registers, reducing memory spills and improving translation efficiency.

* Fix IsSameOperandDestSrc1 Check for Add

* Use LEA if Dest != SRC1

* Update IsSameOperandDestSrc1 to account for Cases where Dest and Src1 can be same for add

* Fix error in logic

* Typo

* Add paranthesis for clarity

* Compare registers as requested.

* Cleanup if statement, use same comparison method as generateCopy

* Make change as recommended by gdk

* Perform check only when Add calls are made

* use ensure sametype for lea, fix else

* Update comment

* Update version #
This commit is contained in:
sharmander 2021-02-07 18:49:46 -05:00 committed by GitHub
parent 4047477866
commit 40797a1283
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
3 changed files with 42 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

37
ARMeilleure/CodeGen/X86/CodeGenerator.cs
View file

@ -514,13 +514,43 @@ namespace ARMeilleure.CodeGen.X86
Operand src1 = operation.GetSource(0);
Operand src2 = operation.GetSource(1);
ValidateBinOp(dest, src1, src2);
if (dest.Type.IsInteger())
{
// If Destination and Source 1 Operands are the same, perform a standard add as there are no benefits to using LEA.
if (dest.Kind == src1.Kind && dest.Value == src1.Value)
{
ValidateBinOp(dest, src1, src2);
context.Assembler.Add(dest, src2, dest.Type);
}
else if (dest.Type == OperandType.FP32)
else
{
EnsureSameType(dest, src1, src2);
int offset;
Operand index;
if (src2.Kind == OperandKind.Constant)
{
offset = src2.AsInt32();
index = null;
}
else
{
offset = 0;
index = src2;
}
MemoryOperand memOp = MemoryOp(dest.Type, src1, index, Multiplier.x1, offset);
context.Assembler.Lea(dest, memOp, dest.Type);
}
}
else
{
ValidateBinOp(dest, src1, src2);
if (dest.Type == OperandType.FP32)
{
context.Assembler.Addss(dest, src1, src2);
}
@ -529,6 +559,7 @@ namespace ARMeilleure.CodeGen.X86
context.Assembler.Addsd(dest, src1, src2);
}
}
}
private static void GenerateBitwiseAnd(CodeGenContext context, Operation operation)
{

1
ARMeilleure/CodeGen/X86/PreAllocator.cs
View file

@ -1273,6 +1273,7 @@ namespace ARMeilleure.CodeGen.X86
switch (operation.Instruction)
{
case Instruction.Add:
return !HardwareCapabilities.SupportsVexEncoding && !operation.Destination.Type.IsInteger();
case Instruction.Multiply:
case Instruction.Subtract:
return !HardwareCapabilities.SupportsVexEncoding || operation.Destination.Type.IsInteger();

2
ARMeilleure/Translation/PTC/Ptc.cs
View file

@ -22,7 +22,7 @@ namespace ARMeilleure.Translation.PTC
{
private const string HeaderMagic = "PTChd";
private const int InternalVersion = 1943; //! To be incremented manually for each change to the ARMeilleure project.
private const int InternalVersion = 1971; //! To be incremented manually for each change to the ARMeilleure project.
private const string ActualDir = "0";
private const string BackupDir = "1";