emu-mirrors/ryujinx-final
Archived
0
0
Fork 0
Code Activity

Fix shader LOP3 predicate write condition (#1910)

Browse source 
* Fix LOP3 predicate write condition

* Bump shader cache version
This commit is contained in:
gdkchan 2021-01-13 21:07:50 -03:00 committed by GitHub
parent 996e6905ba
commit 5be6ec6364
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
3 changed files with 7 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
Ryujinx.Graphics.Gpu/Shader/ShaderCache.cs
View file

@ -34,7 +34,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
/// <summary>
/// Version of the codegen (to be changed when codegen or guest format change).
/// </summary>
private const ulong ShaderCodeGenVersion = 1901;
private const ulong ShaderCodeGenVersion = 1910;
/// <summary>
/// Creates a new instance of the shader cache.

4
Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs
View file

@ -9,8 +9,6 @@ namespace Ryujinx.Graphics.Shader.Decoders
public LogicalOperation LogicalOp { get; }
public ConditionalOperation CondOp { get; }
public Register Predicate48 { get; }
public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLop(emitter, address, opCode);
@ -22,8 +20,6 @@ namespace Ryujinx.Graphics.Shader.Decoders
LogicalOp = (LogicalOperation)opCode.Extract(41, 2);
CondOp = (ConditionalOperation)opCode.Extract(44, 2);
Predicate48 = new Register(opCode.Extract(48, 3), RegisterType.Predicate);
}
}

12
Ryujinx.Graphics.Shader/Instructions/InstEmitAlu.cs
View file

@ -459,7 +459,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
case LogicalOperation.ExclusiveOr: res = context.BitwiseExclusiveOr(srcA, srcB); break;
}
EmitLopPredWrite(context, op, res);
EmitLopPredWrite(context, op, res, (ConditionalOperation)context.CurrOp.RawOpCode.Extract(44, 2));
Operand dest = GetDest(context);
@ -486,7 +486,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
if (regVariant)
{
EmitLopPredWrite(context, op, res);
EmitLopPredWrite(context, op, res, (ConditionalOperation)context.CurrOp.RawOpCode.Extract(36, 2));
}
Operand dest = GetDest(context);
@ -917,21 +917,21 @@ namespace Ryujinx.Graphics.Shader.Instructions
return res;
}
private static void EmitLopPredWrite(EmitterContext context, IOpCodeLop op, Operand result)
private static void EmitLopPredWrite(EmitterContext context, IOpCodeLop op, Operand result, ConditionalOperation condOp)
{
if (op is OpCodeLop opLop && !opLop.Predicate48.IsPT)
{
Operand pRes;
if (opLop.CondOp == ConditionalOperation.False)
if (condOp == ConditionalOperation.False)
{
pRes = Const(IrConsts.False);
}
else if (opLop.CondOp == ConditionalOperation.True)
else if (condOp == ConditionalOperation.True)
{
pRes = Const(IrConsts.True);
}
else if (opLop.CondOp == ConditionalOperation.Zero)
else if (condOp == ConditionalOperation.Zero)
{
pRes = context.ICompareEqual(result, Const(0));
}