Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdCrypto.cs

ChocolArm64/AOpCodeTable.cs

@@ -374,10 +374,12 @@ namespace ChocolArm64
             SetA64("01011110000xxxxx010100xxxxxxxxxx", AInstEmit.Sha256h2_V,    typeof(AOpCodeSimdReg));
             SetA64("0101111000101000001010xxxxxxxxxx", AInstEmit.Sha256su0_V,   typeof(AOpCodeSimd));
             SetA64("01011110000xxxxx011000xxxxxxxxxx", AInstEmit.Sha256su1_V,   typeof(AOpCodeSimdReg));
+            SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Shadd_V,       typeof(AOpCodeSimdReg));
             SetA64("010111110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_S,         typeof(AOpCodeSimdShImm));
             SetA64("0x0011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V,         typeof(AOpCodeSimdShImm));
             SetA64("0x101110<<100001001110xxxxxxxxxx", AInstEmit.Shll_V,        typeof(AOpCodeSimd));
             SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V,        typeof(AOpCodeSimdShImm));
+            SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Shsub_V,       typeof(AOpCodeSimdReg));
             SetA64("0x1011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Sli_V,         typeof(AOpCodeSimdShImm));
             SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Smax_V,        typeof(AOpCodeSimdReg));
             SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Smaxp_V,       typeof(AOpCodeSimdReg));
@@ -407,6 +409,7 @@ namespace ChocolArm64
             SetA64("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V,       typeof(AOpCodeSimd));
             SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S,      typeof(AOpCodeSimd));
             SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V,      typeof(AOpCodeSimd));
+            SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Srhadd_V,      typeof(AOpCodeSimdReg));
             SetA64("0x00111100>>>xxx001001xxxxxxxxxx", AInstEmit.Srshr_V,       typeof(AOpCodeSimdShImm));
             SetA64("0100111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_V,       typeof(AOpCodeSimdShImm));
             SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V,        typeof(AOpCodeSimdReg));
@@ -449,6 +452,7 @@ namespace ChocolArm64
             SetA64("011111100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_S,       typeof(AOpCodeSimd));
             SetA64("0x1011100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_V,       typeof(AOpCodeSimd));
             SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Uhadd_V,       typeof(AOpCodeSimdReg));
+            SetA64("0x101110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Uhsub_V,       typeof(AOpCodeSimdReg));
             SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Umax_V,        typeof(AOpCodeSimdReg));
             SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Umaxp_V,       typeof(AOpCodeSimdReg));
             SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Umin_V,        typeof(AOpCodeSimdReg));
@@ -461,6 +465,7 @@ namespace ChocolArm64
             SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_V,       typeof(AOpCodeSimdReg));
             SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S,       typeof(AOpCodeSimd));
             SetA64("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V,       typeof(AOpCodeSimd));
+            SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Urhadd_V,      typeof(AOpCodeSimdReg));
             SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V,        typeof(AOpCodeSimdReg));
             SetA64("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V,       typeof(AOpCodeSimdShImm));
             SetA64("0111111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_S,        typeof(AOpCodeSimdShImm));

ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs

@@ -1042,6 +1042,28 @@ namespace ChocolArm64.Instruction
             EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
         }
 
+        public static void Shadd_V(AILEmitterCtx Context)
+        {
+            EmitVectorBinaryOpSx(Context, () =>
+            {
+                Context.Emit(OpCodes.Add);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Shr);
+            });
+        }
+
+        public static void Shsub_V(AILEmitterCtx Context)
+        {
+            EmitVectorBinaryOpSx(Context, () =>
+            {
+                Context.Emit(OpCodes.Sub);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Shr);
+            });
+        }
+
         public static void Smax_V(AILEmitterCtx Context)
         {
             Type[] Types = new Type[] { typeof(long), typeof(long) };
@@ -1181,6 +1203,20 @@ namespace ChocolArm64.Instruction
             EmitVectorSaturatingNarrowOpSxZx(Context, () => { });
         }
 
+        public static void Srhadd_V(AILEmitterCtx Context)
+        {
+            EmitVectorBinaryOpSx(Context, () =>
+            {
+                Context.Emit(OpCodes.Add);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Add);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Shr);
+            });
+        }
+
         public static void Ssubw_V(AILEmitterCtx Context)
         {
             EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
@@ -1303,28 +1339,20 @@ namespace ChocolArm64.Instruction
             {
                 Context.Emit(OpCodes.Add);
 
-                Context.EmitLdc_I4(1);
+                Context.Emit(OpCodes.Ldc_I4_1);
-
                 Context.Emit(OpCodes.Shr_Un);
             });
         }
 
-        public static void Umin_V(AILEmitterCtx Context)
+        public static void Uhsub_V(AILEmitterCtx Context)
         {
-            Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
+            EmitVectorBinaryOpZx(Context, () =>
-
-            MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
-
-            EmitVectorBinaryOpZx(Context, () => Context.EmitCall(MthdInfo));
-        }
-
-        public static void Uminp_V(AILEmitterCtx Context)
             {
-            Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
+                Context.Emit(OpCodes.Sub);
 
-            MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
+                Context.Emit(OpCodes.Ldc_I4_1);
-
+                Context.Emit(OpCodes.Shr_Un);
-            EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
+            });
         }
 
         public static void Umax_V(AILEmitterCtx Context)
@@ -1345,6 +1373,24 @@ namespace ChocolArm64.Instruction
             EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
         }
 
+        public static void Umin_V(AILEmitterCtx Context)
+        {
+            Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
+
+            MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
+
+            EmitVectorBinaryOpZx(Context, () => Context.EmitCall(MthdInfo));
+        }
+
+        public static void Uminp_V(AILEmitterCtx Context)
+        {
+            Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
+
+            MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
+
+            EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
+        }
+
         public static void Umull_V(AILEmitterCtx Context)
         {
             EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
@@ -1380,6 +1426,20 @@ namespace ChocolArm64.Instruction
             EmitVectorSaturatingNarrowOpZxZx(Context, () => { });
         }
 
+        public static void Urhadd_V(AILEmitterCtx Context)
+        {
+            EmitVectorBinaryOpZx(Context, () =>
+            {
+                Context.Emit(OpCodes.Add);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Add);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Shr_Un);
+            });
+        }
+
         public static void Usqadd_S(AILEmitterCtx Context)
         {
             EmitScalarSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);

Ryujinx.Tests/Cpu/CpuTest.cs

@@ -119,22 +119,42 @@ namespace Ryujinx.Tests.Cpu
 
         protected static Vector128<float> MakeVectorE0(double E0)
         {
+            if (!Sse2.IsSupported)
+            {
+                throw new PlatformNotSupportedException();
+            }
+
             return Sse.StaticCast<long, float>(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(E0)));
         }
 
         protected static Vector128<float> MakeVectorE0E1(double E0, double E1)
         {
-            return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(E1),
+            if (!Sse2.IsSupported)
-                                                                 BitConverter.DoubleToInt64Bits(E0)));
+            {
+                throw new PlatformNotSupportedException();
+            }
+
+            return Sse.StaticCast<long, float>(
+                Sse2.SetVector128(BitConverter.DoubleToInt64Bits(E1), BitConverter.DoubleToInt64Bits(E0)));
         }
 
         protected static Vector128<float> MakeVectorE1(double E1)
         {
+            if (!Sse2.IsSupported)
+            {
+                throw new PlatformNotSupportedException();
+            }
+
             return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(E1), 0));
         }
 
         protected static double VectorExtractDouble(Vector128<float> Vector, byte Index)
         {
+            if (!Sse41.IsSupported)
+            {
+                throw new PlatformNotSupportedException();
+            }
+
             long Value = Sse41.Extract(Sse.StaticCast<float, long>(Vector), Index);
 
             return BitConverter.Int64BitsToDouble(Value);
@@ -142,26 +162,51 @@ namespace Ryujinx.Tests.Cpu
 
         protected static Vector128<float> MakeVectorE0(ulong E0)
         {
+            if (!Sse2.IsSupported)
+            {
+                throw new PlatformNotSupportedException();
+            }
+
             return Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, E0));
         }
 
         protected static Vector128<float> MakeVectorE0E1(ulong E0, ulong E1)
         {
+            if (!Sse2.IsSupported)
+            {
+                throw new PlatformNotSupportedException();
+            }
+
             return Sse.StaticCast<ulong, float>(Sse2.SetVector128(E1, E0));
         }
 
         protected static Vector128<float> MakeVectorE1(ulong E1)
         {
+            if (!Sse2.IsSupported)
+            {
+                throw new PlatformNotSupportedException();
+            }
+
             return Sse.StaticCast<ulong, float>(Sse2.SetVector128(E1, 0));
         }
 
         protected static ulong GetVectorE0(Vector128<float> Vector)
         {
+            if (!Sse41.IsSupported)
+            {
+                throw new PlatformNotSupportedException();
+            }
+
             return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), (byte)0);
         }
 
         protected static ulong GetVectorE1(Vector128<float> Vector)
         {
+            if (!Sse41.IsSupported)
+            {
+                throw new PlatformNotSupportedException();
+            }
+
             return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), (byte)1);
         }
     }

Ryujinx.Tests/Cpu/CpuTestSimd.cs

@@ -1245,11 +1245,11 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
-        [Test, Explicit, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")] // 1250 tests.
+        [Test, Pairwise, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")]
         public void Sha256su0_V([Values(0u)]     uint Rd,
                                 [Values(1u, 0u)] uint Rn,
-                                [Random(5)] ulong Z0, [Random(5)] ulong Z1,
+                                [Random(RndCnt * 2)] ulong Z0, [Random(RndCnt * 2)] ulong Z1,
-                                [Random(5)] ulong A0, [Random(5)] ulong A1)
+                                [Random(RndCnt * 2)] ulong A0, [Random(RndCnt * 2)] ulong A1)
         {
             uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S
             Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);

Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs

@@ -10,7 +10,7 @@ namespace Ryujinx.Tests.Cpu
 {
     public class CpuTestSimdCrypto : CpuTest
     {
-        [Test, Explicit, Description("AESD <Vd>.16B, <Vn>.16B")]
+        [Test, Description("AESD <Vd>.16B, <Vn>.16B")]
         public void Aesd_V([Values(0u)] uint Rd,
                            [Values(1u)] uint Rn,
                            [Values(0x7B5B546573745665ul)] ulong ValueH,
@@ -39,7 +39,7 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
-        [Test, Explicit, Description("AESE <Vd>.16B, <Vn>.16B")]
+        [Test, Description("AESE <Vd>.16B, <Vn>.16B")]
         public void Aese_V([Values(0u)] uint Rd,
                            [Values(1u)] uint Rn,
                            [Values(0x7B5B546573745665ul)] ulong ValueH,
@@ -68,7 +68,7 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
-        [Test, Explicit, Description("AESIMC <Vd>.16B, <Vn>.16B")]
+        [Test, Description("AESIMC <Vd>.16B, <Vn>.16B")]
         public void Aesimc_V([Values(0u)]     uint Rd,
                              [Values(1u, 0u)] uint Rn,
                              [Values(0x8DCAB9DC035006BCul)] ulong ValueH,
@@ -100,7 +100,7 @@ namespace Ryujinx.Tests.Cpu
             }
         }
 
-        [Test, Explicit, Description("AESMC <Vd>.16B, <Vn>.16B")]
+        [Test, Description("AESMC <Vd>.16B, <Vn>.16B")]
         public void Aesmc_V([Values(0u)]     uint Rd,
                             [Values(1u, 0u)] uint Rn,
                             [Values(0x627A6F6644B109C8ul)] ulong ValueH,

Ryujinx.Tests/Cpu/CpuTestSimdReg.cs

@@ -1747,13 +1747,13 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
-        [Test, Explicit, Description("SHA256H <Qd>, <Qn>, <Vm>.4S")] // 2916 tests.
+        [Test, Pairwise, Description("SHA256H <Qd>, <Qn>, <Vm>.4S")]
         public void Sha256h_V([Values(0u)]     uint Rd,
                               [Values(1u, 0u)] uint Rn,
                               [Values(2u, 0u)] uint Rm,
-                              [Random(3)] ulong Z0, [Random(3)] ulong Z1,
+                              [Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1,
-                              [Random(3)] ulong A0, [Random(3)] ulong A1,
+                              [Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1,
-                              [Random(3)] ulong B0, [Random(3)] ulong B1)
+                              [Random(RndCnt / 2)] ulong B0, [Random(RndCnt / 2)] ulong B1)
         {
             uint Opcode = 0x5E004000; // SHA256H Q0, Q0, V0.4S
             Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
@@ -1784,13 +1784,13 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
-        [Test, Explicit, Description("SHA256H2 <Qd>, <Qn>, <Vm>.4S")] // 2916 tests.
+        [Test, Pairwise, Description("SHA256H2 <Qd>, <Qn>, <Vm>.4S")]
         public void Sha256h2_V([Values(0u)]     uint Rd,
                                [Values(1u, 0u)] uint Rn,
                                [Values(2u, 0u)] uint Rm,
-                               [Random(3)] ulong Z0, [Random(3)] ulong Z1,
+                               [Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1,
-                               [Random(3)] ulong A0, [Random(3)] ulong A1,
+                               [Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1,
-                               [Random(3)] ulong B0, [Random(3)] ulong B1)
+                               [Random(RndCnt / 2)] ulong B0, [Random(RndCnt / 2)] ulong B1)
         {
             uint Opcode = 0x5E005000; // SHA256H2 Q0, Q0, V0.4S
             Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
@@ -1821,13 +1821,13 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
-        [Test, Explicit, Description("SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S")] // 2916 tests.
+        [Test, Pairwise, Description("SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S")]
         public void Sha256su1_V([Values(0u)]     uint Rd,
                                 [Values(1u, 0u)] uint Rn,
                                 [Values(2u, 0u)] uint Rm,
-                                [Random(3)] ulong Z0, [Random(3)] ulong Z1,
+                                [Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1,
-                                [Random(3)] ulong A0, [Random(3)] ulong A1,
+                                [Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1,
-                                [Random(3)] ulong B0, [Random(3)] ulong B1)
+                                [Random(RndCnt / 2)] ulong B0, [Random(RndCnt / 2)] ulong B1)
         {
             uint Opcode = 0x5E006000; // SHA256SU1 V0.4S, V0.4S, V0.4S
             Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
@@ -1858,6 +1858,130 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
+        [Test, Pairwise, Description("SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Shadd_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                     [Values(1u, 0u)] uint Rn,
+                                     [Values(2u, 0u)] uint Rm,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                     [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x0E200400; // SHADD V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Shadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Shadd_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x4E200400; // SHADD V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Shadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Shsub_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                     [Values(1u, 0u)] uint Rn,
+                                     [Values(2u, 0u)] uint Rm,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                     [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x0E202400; // SHSUB V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Shsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Shsub_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x4E202400; // SHSUB V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Shsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
         [Test, Pairwise, Description("SQADD <V><d>, <V><n>, <V><m>")]
         public void Sqadd_S_B_H_S_D([Values(0u)]     uint Rd,
                                     [Values(1u, 0u)] uint Rn,
@@ -2278,6 +2402,68 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
         }
 
+        [Test, Pairwise, Description("SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Srhadd_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x0E201400; // SRHADD V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Srhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Srhadd_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                       [Values(1u, 0u)] uint Rn,
+                                       [Values(2u, 0u)] uint Rm,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                       [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x4E201400; // SRHADD V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Srhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
         [Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
         public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)]     uint Rd,
                                                  [Values(1u, 0u)] uint Rn,
@@ -2927,6 +3113,130 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
+        [Test, Pairwise, Description("UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Uhadd_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                     [Values(1u, 0u)] uint Rn,
+                                     [Values(2u, 0u)] uint Rm,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                     [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x2E200400; // UHADD V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Uhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Uhadd_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x6E200400; // UHADD V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Uhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Uhsub_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                     [Values(1u, 0u)] uint Rn,
+                                     [Values(2u, 0u)] uint Rm,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                     [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x2E202400; // UHSUB V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Uhsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Uhsub_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x6E202400; // UHSUB V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Uhsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
         [Test, Pairwise, Description("UQADD <V><d>, <V><n>, <V><m>")]
         public void Uqadd_S_B_H_S_D([Values(0u)]     uint Rd,
                                     [Values(1u, 0u)] uint Rn,
@@ -3137,6 +3447,68 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
         }
 
+        [Test, Pairwise, Description("URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Urhadd_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x2E201400; // URHADD V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Urhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Urhadd_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                       [Values(1u, 0u)] uint Rn,
+                                       [Values(2u, 0u)] uint Rm,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                       [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x6E201400; // URHADD V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Urhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
         [Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
         public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)]     uint Rd,
                                                  [Values(1u, 0u)] uint Rn,

Ryujinx.Tests/Cpu/Tester/Instructions.cs

@@ -5251,6 +5251,88 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // shadd_advsimd.html
+        public static void Shadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = false;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = (Q ? 128 : 64);
+            int elements = datasize / esize;
+
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand1 = V(datasize, n);
+            Bits operand2 = V(datasize, m);
+            BigInteger element1;
+            BigInteger element2;
+            BigInteger sum;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                sum = element1 + element2;
+
+                Elem(result, e, esize, sum.SubBigInteger(esize, 1));
+            }
+
+            V(d, result);
+        }
+
+        // shsub_advsimd.html
+        public static void Shsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = false;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = (Q ? 128 : 64);
+            int elements = datasize / esize;
+
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand1 = V(datasize, n);
+            Bits operand2 = V(datasize, m);
+            BigInteger element1;
+            BigInteger element2;
+            BigInteger diff;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                diff = element1 - element2;
+
+                Elem(result, e, esize, diff.SubBigInteger(esize, 1));
+            }
+
+            V(d, result);
+        }
+
         // sqadd_advsimd.html#SQADD_asisdsame_only
         public static void Sqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
         {
@@ -5651,6 +5733,44 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // srhadd_advsimd.html
+        public static void Srhadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = false;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = (Q ? 128 : 64);
+            int elements = datasize / esize;
+
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand1 = V(datasize, n);
+            Bits operand2 = V(datasize, m);
+            BigInteger element1;
+            BigInteger element2;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                Elem(result, e, esize, (element1 + element2 + 1).SubBigInteger(esize, 1));
+            }
+
+            V(d, result);
+        }
+
         // ssubw_advsimd.html
         public static void Ssubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
         {
@@ -6143,6 +6263,88 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // uhadd_advsimd.html
+        public static void Uhadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = true;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = (Q ? 128 : 64);
+            int elements = datasize / esize;
+
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand1 = V(datasize, n);
+            Bits operand2 = V(datasize, m);
+            BigInteger element1;
+            BigInteger element2;
+            BigInteger sum;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                sum = element1 + element2;
+
+                Elem(result, e, esize, sum.SubBigInteger(esize, 1));
+            }
+
+            V(d, result);
+        }
+
+        // uhsub_advsimd.html
+        public static void Uhsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = true;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = (Q ? 128 : 64);
+            int elements = datasize / esize;
+
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand1 = V(datasize, n);
+            Bits operand2 = V(datasize, m);
+            BigInteger element1;
+            BigInteger element2;
+            BigInteger diff;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                diff = element1 - element2;
+
+                Elem(result, e, esize, diff.SubBigInteger(esize, 1));
+            }
+
+            V(d, result);
+        }
+
         // uqadd_advsimd.html#UQADD_asisdsame_only
         public static void Uqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
         {
@@ -6339,6 +6541,44 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // urhadd_advsimd.html
+        public static void Urhadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = true;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = (Q ? 128 : 64);
+            int elements = datasize / esize;
+
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand1 = V(datasize, n);
+            Bits operand2 = V(datasize, m);
+            BigInteger element1;
+            BigInteger element2;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                Elem(result, e, esize, (element1 + element2 + 1).SubBigInteger(esize, 1));
+            }
+
+            V(d, result);
+        }
+
         // usubw_advsimd.html
         public static void Usubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
         {