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Add a new JIT compiler for CPU code (#693)

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* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
This commit is contained in:
gdkchan 2019-08-08 15:56:22 -03:00 committed by emmauss
parent 1ba58e9942
commit a731ab3a2a
310 changed files with 37389 additions and 2086 deletions
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20
ARMeilleure/ARMeilleure.csproj Normal file
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<Project Sdk="Microsoft.NET.Sdk">
<PropertyGroup>
<TargetFramework>netcoreapp2.1</TargetFramework>
<RuntimeIdentifiers>win-x64;osx-x64;linux-x64</RuntimeIdentifiers>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|AnyCPU'">
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|AnyCPU'">
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
</PropertyGroup>
<ItemGroup>
<PackageReference Include="Mono.Posix.NETStandard" Version="1.0.0" />
</ItemGroup>
</Project>

17
ARMeilleure/CodeGen/CompiledFunction.cs Normal file
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using ARMeilleure.CodeGen.Unwinding;
namespace ARMeilleure.CodeGen
{
struct CompiledFunction
{
public byte[] Code { get; }
public UnwindInfo UnwindInfo { get; }
public CompiledFunction(byte[] code, UnwindInfo unwindInfo)
{
Code = code;
UnwindInfo = unwindInfo;
}
}
}

258
ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs Normal file
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using ARMeilleure.IntermediateRepresentation;
using System;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
namespace ARMeilleure.CodeGen.Optimizations
{
static class ConstantFolding
{
public static void RunPass(Operation operation)
{
if (operation.Destination == null || operation.SourcesCount == 0)
{
return;
}
if (!AreAllSourcesConstant(operation))
{
return;
}
OperandType type = operation.Destination.Type;
switch (operation.Instruction)
{
case Instruction.Add:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => x + y);
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => x + y);
}
break;
case Instruction.BitwiseAnd:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => x & y);
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => x & y);
}
break;
case Instruction.BitwiseExclusiveOr:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => x ^ y);
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => x ^ y);
}
break;
case Instruction.BitwiseNot:
if (type == OperandType.I32)
{
EvaluateUnaryI32(operation, (x) => ~x);
}
else if (type == OperandType.I64)
{
EvaluateUnaryI64(operation, (x) => ~x);
}
break;
case Instruction.BitwiseOr:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => x | y);
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => x | y);
}
break;
case Instruction.Copy:
if (type == OperandType.I32)
{
EvaluateUnaryI32(operation, (x) => x);
}
else if (type == OperandType.I64)
{
EvaluateUnaryI64(operation, (x) => x);
}
break;
case Instruction.Divide:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => y != 0 ? x / y : 0);
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => y != 0 ? x / y : 0);
}
break;
case Instruction.DivideUI:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => y != 0 ? (int)((uint)x / (uint)y) : 0);
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => y != 0 ? (long)((ulong)x / (ulong)y) : 0);
}
break;
case Instruction.Multiply:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => x * y);
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => x * y);
}
break;
case Instruction.Negate:
if (type == OperandType.I32)
{
EvaluateUnaryI32(operation, (x) => -x);
}
else if (type == OperandType.I64)
{
EvaluateUnaryI64(operation, (x) => -x);
}
break;
case Instruction.ShiftLeft:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => x << y);
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => x << (int)y);
}
break;
case Instruction.ShiftRightSI:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => x >> y);
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => x >> (int)y);
}
break;
case Instruction.ShiftRightUI:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => (int)((uint)x >> y));
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => (long)((ulong)x >> (int)y));
}
break;
case Instruction.SignExtend16:
if (type == OperandType.I32)
{
EvaluateUnaryI32(operation, (x) => (short)x);
}
else if (type == OperandType.I64)
{
EvaluateUnaryI64(operation, (x) => (short)x);
}
break;
case Instruction.SignExtend32:
if (type == OperandType.I32)
{
EvaluateUnaryI32(operation, (x) => x);
}
else if (type == OperandType.I64)
{
EvaluateUnaryI64(operation, (x) => (int)x);
}
break;
case Instruction.SignExtend8:
if (type == OperandType.I32)
{
EvaluateUnaryI32(operation, (x) => (sbyte)x);
}
else if (type == OperandType.I64)
{
EvaluateUnaryI64(operation, (x) => (sbyte)x);
}
break;
case Instruction.Subtract:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => x - y);
}
else if (type == OperandType.I64)
{
EvaluateBinaryI64(operation, (x, y) => x - y);
}
break;
}
}
private static bool AreAllSourcesConstant(Operation operation)
{
for (int index = 0; index < operation.SourcesCount; index++)
{
if (operation.GetSource(index).Kind != OperandKind.Constant)
{
return false;
}
}
return true;
}
private static void EvaluateUnaryI32(Operation operation, Func<int, int> op)
{
int x = operation.GetSource(0).AsInt32();
operation.TurnIntoCopy(Const(op(x)));
}
private static void EvaluateUnaryI64(Operation operation, Func<long, long> op)
{
long x = operation.GetSource(0).AsInt64();
operation.TurnIntoCopy(Const(op(x)));
}
private static void EvaluateBinaryI32(Operation operation, Func<int, int, int> op)
{
int x = operation.GetSource(0).AsInt32();
int y = operation.GetSource(1).AsInt32();
operation.TurnIntoCopy(Const(op(x, y)));
}
private static void EvaluateBinaryI64(Operation operation, Func<long, long, long> op)
{
long x = operation.GetSource(0).AsInt64();
long y = operation.GetSource(1).AsInt64();
operation.TurnIntoCopy(Const(op(x, y)));
}
}
}

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ARMeilleure/CodeGen/Optimizations/Optimizer.cs Normal file
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using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System.Collections.Generic;
using System.Diagnostics;
using System.Linq;
namespace ARMeilleure.CodeGen.Optimizations
{
static class Optimizer
{
public static void RunPass(ControlFlowGraph cfg)
{
bool modified;
do
{
modified = false;
foreach (BasicBlock block in cfg.Blocks)
{
LinkedListNode<Node> node = block.Operations.First;
while (node != null)
{
LinkedListNode<Node> nextNode = node.Next;
bool isUnused = IsUnused(node.Value);
if (!(node.Value is Operation operation) || isUnused)
{
if (isUnused)
{
RemoveNode(block, node);
modified = true;
}
node = nextNode;
continue;
}
ConstantFolding.RunPass(operation);
Simplification.RunPass(operation);
if (DestIsLocalVar(operation) && IsPropagableCopy(operation))
{
PropagateCopy(operation);
RemoveNode(block, node);
modified = true;
}
node = nextNode;
}
}
}
while (modified);
}
private static void PropagateCopy(Operation copyOp)
{
// Propagate copy source operand to all uses of the destination operand.
Operand dest = copyOp.Destination;
Operand source = copyOp.GetSource(0);
Node[] uses = dest.Uses.ToArray();
foreach (Node use in uses)
{
for (int index = 0; index < use.SourcesCount; index++)
{
if (use.GetSource(index) == dest)
{
use.SetSource(index, source);
}
}
}
}
private static void RemoveNode(BasicBlock block, LinkedListNode<Node> llNode)
{
// Remove a node from the nodes list, and also remove itself
// from all the use lists on the operands that this node uses.
block.Operations.Remove(llNode);
Node node = llNode.Value;
for (int index = 0; index < node.SourcesCount; index++)
{
node.SetSource(index, null);
}
Debug.Assert(node.Destination == null || node.Destination.Uses.Count == 0);
node.Destination = null;
}
private static bool IsUnused(Node node)
{
return DestIsLocalVar(node) && node.Destination.Uses.Count == 0 && !HasSideEffects(node);
}
private static bool DestIsLocalVar(Node node)
{
return node.Destination != null && node.Destination.Kind == OperandKind.LocalVariable;
}
private static bool HasSideEffects(Node node)
{
return (node is Operation operation) && operation.Instruction == Instruction.Call;
}
private static bool IsPropagableCopy(Operation operation)
{
if (operation.Instruction != Instruction.Copy)
{
return false;
}
return operation.Destination.Type == operation.GetSource(0).Type;
}
}
}

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ARMeilleure/CodeGen/Optimizations/Simplification.cs Normal file
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using ARMeilleure.IntermediateRepresentation;
using System;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
namespace ARMeilleure.CodeGen.Optimizations
{
static class Simplification
{
public static void RunPass(Operation operation)
{
switch (operation.Instruction)
{
case Instruction.Add:
case Instruction.BitwiseExclusiveOr:
TryEliminateBinaryOpComutative(operation, 0);
break;
case Instruction.BitwiseAnd:
TryEliminateBitwiseAnd(operation);
break;
case Instruction.BitwiseOr:
TryEliminateBitwiseOr(operation);
break;
case Instruction.ConditionalSelect:
TryEliminateConditionalSelect(operation);
break;
case Instruction.Divide:
TryEliminateBinaryOpY(operation, 1);
break;
case Instruction.Multiply:
TryEliminateBinaryOpComutative(operation, 1);
break;
case Instruction.ShiftLeft:
case Instruction.ShiftRightSI:
case Instruction.ShiftRightUI:
case Instruction.Subtract:
TryEliminateBinaryOpY(operation, 0);
break;
}
}
private static void TryEliminateBitwiseAnd(Operation operation)
{
// Try to recognize and optimize those 3 patterns (in order):
// x & 0xFFFFFFFF == x, 0xFFFFFFFF & y == y,
// x & 0x00000000 == 0x00000000, 0x00000000 & y == 0x00000000
Operand x = operation.GetSource(0);
Operand y = operation.GetSource(1);
if (IsConstEqual(x, AllOnes(x.Type)))
{
operation.TurnIntoCopy(y);
}
else if (IsConstEqual(y, AllOnes(y.Type)))
{
operation.TurnIntoCopy(x);
}
else if (IsConstEqual(x, 0) || IsConstEqual(y, 0))
{
operation.TurnIntoCopy(Const(0));
}
}
private static void TryEliminateBitwiseOr(Operation operation)
{
// Try to recognize and optimize those 3 patterns (in order):
// x | 0x00000000 == x, 0x00000000 | y == y,
// x | 0xFFFFFFFF == 0xFFFFFFFF, 0xFFFFFFFF | y == 0xFFFFFFFF
Operand x = operation.GetSource(0);
Operand y = operation.GetSource(1);
if (IsConstEqual(x, 0))
{
operation.TurnIntoCopy(y);
}
else if (IsConstEqual(y, 0))
{
operation.TurnIntoCopy(x);
}
else if (IsConstEqual(x, AllOnes(x.Type)) || IsConstEqual(y, AllOnes(y.Type)))
{
operation.TurnIntoCopy(Const(AllOnes(x.Type)));
}
}
private static void TryEliminateBinaryOpY(Operation operation, ulong comparand)
{
Operand x = operation.GetSource(0);
Operand y = operation.GetSource(1);
if (IsConstEqual(y, comparand))
{
operation.TurnIntoCopy(x);
}
}
private static void TryEliminateBinaryOpComutative(Operation operation, ulong comparand)
{
Operand x = operation.GetSource(0);
Operand y = operation.GetSource(1);
if (IsConstEqual(x, comparand))
{
operation.TurnIntoCopy(y);
}
else if (IsConstEqual(y, comparand))
{
operation.TurnIntoCopy(x);
}
}
private static void TryEliminateConditionalSelect(Operation operation)
{
Operand cond = operation.GetSource(0);
if (cond.Kind != OperandKind.Constant)
{
return;
}
// The condition is constant, we can turn it into a copy, and select
// the source based on the condition value.
int srcIndex = cond.Value != 0 ? 1 : 2;
Operand source = operation.GetSource(srcIndex);
operation.TurnIntoCopy(source);
}
private static bool IsConstEqual(Operand operand, ulong comparand)
{
if (operand.Kind != OperandKind.Constant || !operand.Type.IsInteger())
{
return false;
}
return operand.Value == comparand;
}
private static ulong AllOnes(OperandType type)
{
switch (type)
{
case OperandType.I32: return ~0U;
case OperandType.I64: return ~0UL;
}
throw new ArgumentException("Invalid operand type \"" + type + "\".");
}
}
}

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ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs Normal file
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namespace ARMeilleure.CodeGen.RegisterAllocators
{
struct AllocationResult
{
public int IntUsedRegisters { get; }
public int VecUsedRegisters { get; }
public int SpillRegionSize { get; }
public AllocationResult(
int intUsedRegisters,
int vecUsedRegisters,
int spillRegionSize)
{
IntUsedRegisters = intUsedRegisters;
VecUsedRegisters = vecUsedRegisters;
SpillRegionSize = spillRegionSize;
}
}
}

246
ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs Normal file
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using ARMeilleure.IntermediateRepresentation;
using System;
using System.Collections.Generic;
namespace ARMeilleure.CodeGen.RegisterAllocators
{
class CopyResolver
{
private class ParallelCopy
{
private struct Copy
{
public Register Dest { get; }
public Register Source { get; }
public OperandType Type { get; }
public Copy(Register dest, Register source, OperandType type)
{
Dest = dest;
Source = source;
Type = type;
}
}
private List<Copy> _copies;
public int Count => _copies.Count;
public ParallelCopy()
{
_copies = new List<Copy>();
}
public void AddCopy(Register dest, Register source, OperandType type)
{
_copies.Add(new Copy(dest, source, type));
}
public void Sequence(List<Operation> sequence)
{
Dictionary<Register, Register> locations = new Dictionary<Register, Register>();
Dictionary<Register, Register> sources = new Dictionary<Register, Register>();
Dictionary<Register, OperandType> types = new Dictionary<Register, OperandType>();
Queue<Register> pendingQueue = new Queue<Register>();
Queue<Register> readyQueue = new Queue<Register>();
foreach (Copy copy in _copies)
{
locations[copy.Source] = copy.Source;
sources[copy.Dest] = copy.Source;
types[copy.Dest] = copy.Type;
pendingQueue.Enqueue(copy.Dest);
}
foreach (Copy copy in _copies)
{
// If the destination is not used anywhere, we can assign it immediately.
if (!locations.ContainsKey(copy.Dest))
{
readyQueue.Enqueue(copy.Dest);
}
}
while (pendingQueue.TryDequeue(out Register current))
{
Register copyDest;
Register origSource;
Register copySource;
while (readyQueue.TryDequeue(out copyDest))
{
origSource = sources[copyDest];
copySource = locations[origSource];
OperandType type = types[copyDest];
EmitCopy(sequence, GetRegister(copyDest, type), GetRegister(copySource, type));
locations[origSource] = copyDest;
if (origSource == copySource && sources.ContainsKey(origSource))
{
readyQueue.Enqueue(origSource);
}
}
copyDest = current;
origSource = sources[copyDest];
copySource = locations[origSource];
if (copyDest != copySource)
{
OperandType type = types[copyDest];
type = type.IsInteger() ? OperandType.I64 : OperandType.V128;
EmitXorSwap(sequence, GetRegister(copyDest, type), GetRegister(copySource, type));
locations[origSource] = copyDest;
Register swapOther = copySource;
if (copyDest != locations[sources[copySource]])
{
// Find the other swap destination register.
// To do that, we search all the pending registers, and pick
// the one where the copy source register is equal to the
// current destination register being processed (copyDest).
foreach (Register pending in pendingQueue)
{
// Is this a copy of pending <- copyDest?
if (copyDest == locations[sources[pending]])
{
swapOther = pending;
break;
}
}
}
// The value that was previously at "copyDest" now lives on
// "copySource" thanks to the swap, now we need to update the
// location for the next copy that is supposed to copy the value
// that used to live on "copyDest".
locations[sources[swapOther]] = copySource;
}
}
}
private static void EmitCopy(List<Operation> sequence, Operand x, Operand y)
{
sequence.Add(new Operation(Instruction.Copy, x, y));
}
private static void EmitXorSwap(List<Operation> sequence, Operand x, Operand y)
{
sequence.Add(new Operation(Instruction.BitwiseExclusiveOr, x, x, y));
sequence.Add(new Operation(Instruction.BitwiseExclusiveOr, y, y, x));
sequence.Add(new Operation(Instruction.BitwiseExclusiveOr, x, x, y));
}
}
private Queue<Operation> _fillQueue = new Queue<Operation>();
private Queue<Operation> _spillQueue = new Queue<Operation>();
private ParallelCopy _parallelCopy;
public bool HasCopy { get; private set; }
public CopyResolver()
{
_fillQueue = new Queue<Operation>();
_spillQueue = new Queue<Operation>();
_parallelCopy = new ParallelCopy();
}
public void AddSplit(LiveInterval left, LiveInterval right)
{
if (left.Local != right.Local)
{
throw new ArgumentException("Intervals of different variables are not allowed.");
}
OperandType type = left.Local.Type;
if (left.IsSpilled && !right.IsSpilled)
{
// Move from the stack to a register.
AddSplitFill(left, right, type);
}
else if (!left.IsSpilled && right.IsSpilled)
{
// Move from a register to the stack.
AddSplitSpill(left, right, type);
}
else if (!left.IsSpilled && !right.IsSpilled && left.Register != right.Register)
{
// Move from one register to another.
AddSplitCopy(left, right, type);
}
else if (left.SpillOffset != right.SpillOffset)
{
// This would be the stack-to-stack move case, but this is not supported.
throw new ArgumentException("Both intervals were spilled.");
}
}
private void AddSplitFill(LiveInterval left, LiveInterval right, OperandType type)
{
Operand register = GetRegister(right.Register, type);
Operand offset = new Operand(left.SpillOffset);
_fillQueue.Enqueue(new Operation(Instruction.Fill, register, offset));
HasCopy = true;
}
private void AddSplitSpill(LiveInterval left, LiveInterval right, OperandType type)
{
Operand offset = new Operand(right.SpillOffset);
Operand register = GetRegister(left.Register, type);
_spillQueue.Enqueue(new Operation(Instruction.Spill, null, offset, register));
HasCopy = true;
}
private void AddSplitCopy(LiveInterval left, LiveInterval right, OperandType type)
{
_parallelCopy.AddCopy(right.Register, left.Register, type);
HasCopy = true;
}
public Operation[] Sequence()
{
List<Operation> sequence = new List<Operation>();
while (_spillQueue.TryDequeue(out Operation spillOp))
{
sequence.Add(spillOp);
}
_parallelCopy.Sequence(sequence);
while (_fillQueue.TryDequeue(out Operation fillOp))
{
sequence.Add(fillOp);
}
return sequence.ToArray();
}
private static Operand GetRegister(Register reg, OperandType type)
{
return new Operand(reg.Index, reg.Type, type);
}
}
}

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ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs Normal file
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using ARMeilleure.Common;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System.Collections.Generic;
using System.Diagnostics;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
namespace ARMeilleure.CodeGen.RegisterAllocators
{
class HybridAllocator : IRegisterAllocator
{
private const int RegistersCount = 16;
private const int MaxIROperands = 4;
private struct BlockInfo
{
public bool HasCall { get; }
public int IntFixedRegisters { get; }
public int VecFixedRegisters { get; }
public BlockInfo(bool hasCall, int intFixedRegisters, int vecFixedRegisters)
{
HasCall = hasCall;
IntFixedRegisters = intFixedRegisters;
VecFixedRegisters = vecFixedRegisters;
}
}
private class LocalInfo
{
public int Uses { get; set; }
public int UseCount { get; set; }
public bool PreAllocated { get; set; }
public int Register { get; set; }
public int SpillOffset { get; set; }
public int Sequence { get; set; }
public Operand Temp { get; set; }
public OperandType Type { get; }
private int _first;
private int _last;
public bool IsBlockLocal => _first == _last;
public LocalInfo(OperandType type, int uses)
{
Uses = uses;
Type = type;
_first = -1;
_last = -1;
}
public void SetBlockIndex(int blkIndex)
{
if (_first == -1 || blkIndex < _first)
{
_first = blkIndex;
}
if (_last == -1 || blkIndex > _last)
{
_last = blkIndex;
}
}
}
public AllocationResult RunPass(
ControlFlowGraph cfg,
StackAllocator stackAlloc,
RegisterMasks regMasks)
{
int intUsedRegisters = 0;
int vecUsedRegisters = 0;
int intFreeRegisters = regMasks.IntAvailableRegisters;
int vecFreeRegisters = regMasks.VecAvailableRegisters;
BlockInfo[] blockInfo = new BlockInfo[cfg.Blocks.Count];
List<LocalInfo> locInfo = new List<LocalInfo>();
for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
{
BasicBlock block = cfg.PostOrderBlocks[index];
int intFixedRegisters = 0;
int vecFixedRegisters = 0;
bool hasCall = false;
foreach (Node node in block.Operations)
{
if (node is Operation operation && operation.Instruction == Instruction.Call)
{
hasCall = true;
}
for (int srcIndex = 0; srcIndex < node.SourcesCount; srcIndex++)
{
Operand source = node.GetSource(srcIndex);
if (source.Kind == OperandKind.LocalVariable)
{
locInfo[source.AsInt32() - 1].SetBlockIndex(block.Index);
}
}
for (int dstIndex = 0; dstIndex < node.DestinationsCount; dstIndex++)
{
Operand dest = node.GetDestination(dstIndex);
if (dest.Kind == OperandKind.LocalVariable)
{
LocalInfo info;
if (dest.Value != 0)
{
info = locInfo[dest.AsInt32() - 1];
}
else
{
dest.NumberLocal(locInfo.Count + 1);
info = new LocalInfo(dest.Type, UsesCount(dest));
locInfo.Add(info);
}
info.SetBlockIndex(block.Index);
}
else if (dest.Kind == OperandKind.Register)
{
if (dest.Type.IsInteger())
{
intFixedRegisters |= 1 << dest.GetRegister().Index;
}
else
{
vecFixedRegisters |= 1 << dest.GetRegister().Index;
}
}
}
}
blockInfo[block.Index] = new BlockInfo(hasCall, intFixedRegisters, vecFixedRegisters);
}
int sequence = 0;
for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
{
BasicBlock block = cfg.PostOrderBlocks[index];
BlockInfo blkInfo = blockInfo[block.Index];
int intLocalFreeRegisters = intFreeRegisters & ~blkInfo.IntFixedRegisters;
int vecLocalFreeRegisters = vecFreeRegisters & ~blkInfo.VecFixedRegisters;
int intCallerSavedRegisters = blkInfo.HasCall ? regMasks.IntCallerSavedRegisters : 0;
int vecCallerSavedRegisters = blkInfo.HasCall ? regMasks.VecCallerSavedRegisters : 0;
int intSpillTempRegisters = SelectSpillTemps(
intCallerSavedRegisters & ~blkInfo.IntFixedRegisters,
intLocalFreeRegisters);
int vecSpillTempRegisters = SelectSpillTemps(
vecCallerSavedRegisters & ~blkInfo.VecFixedRegisters,
vecLocalFreeRegisters);
intLocalFreeRegisters &= ~(intSpillTempRegisters | intCallerSavedRegisters);
vecLocalFreeRegisters &= ~(vecSpillTempRegisters | vecCallerSavedRegisters);
for (LinkedListNode<Node> llNode = block.Operations.First; llNode != null; llNode = llNode.Next)
{
Node node = llNode.Value;
int intLocalUse = 0;
int vecLocalUse = 0;
for (int srcIndex = 0; srcIndex < node.SourcesCount; srcIndex++)
{
Operand source = node.GetSource(srcIndex);
if (source.Kind != OperandKind.LocalVariable)
{
continue;
}
LocalInfo info = locInfo[source.AsInt32() - 1];
info.UseCount++;
Debug.Assert(info.UseCount <= info.Uses);
if (info.Register != -1)
{
node.SetSource(srcIndex, Register(info.Register, source.Type.ToRegisterType(), source.Type));
if (info.UseCount == info.Uses && !info.PreAllocated)
{
if (source.Type.IsInteger())
{
intLocalFreeRegisters |= 1 << info.Register;
}
else
{
vecLocalFreeRegisters |= 1 << info.Register;
}
}
}
else
{
Operand temp = info.Temp;
if (temp == null || info.Sequence != sequence)
{
temp = source.Type.IsInteger()
? GetSpillTemp(source, intSpillTempRegisters, ref intLocalUse)
: GetSpillTemp(source, vecSpillTempRegisters, ref vecLocalUse);
info.Sequence = sequence;
info.Temp = temp;
}
node.SetSource(srcIndex, temp);
Operation fillOp = new Operation(Instruction.Fill, temp, Const(info.SpillOffset));
block.Operations.AddBefore(llNode, fillOp);
}
}
int intLocalAsg = 0;
int vecLocalAsg = 0;
for (int dstIndex = 0; dstIndex < node.DestinationsCount; dstIndex++)
{
Operand dest = node.GetDestination(dstIndex);
if (dest.Kind != OperandKind.LocalVariable)
{
continue;
}
LocalInfo info = locInfo[dest.AsInt32() - 1];
if (info.UseCount == 0 && !info.PreAllocated)
{
int mask = dest.Type.IsInteger()
? intLocalFreeRegisters
: vecLocalFreeRegisters;
if (info.IsBlockLocal && mask != 0)
{
int selectedReg = BitUtils.LowestBitSet(mask);
info.Register = selectedReg;
if (dest.Type.IsInteger())
{
intLocalFreeRegisters &= ~(1 << selectedReg);
intUsedRegisters |= 1 << selectedReg;
}
else
{
vecLocalFreeRegisters &= ~(1 << selectedReg);
vecUsedRegisters |= 1 << selectedReg;
}
}
else
{
info.Register = -1;
info.SpillOffset = stackAlloc.Allocate(dest.Type.GetSizeInBytes());
}
}
info.UseCount++;
Debug.Assert(info.UseCount <= info.Uses);
if (info.Register != -1)
{
node.SetDestination(dstIndex, Register(info.Register, dest.Type.ToRegisterType(), dest.Type));
}
else
{
Operand temp = info.Temp;
if (temp == null || info.Sequence != sequence)
{
temp = dest.Type.IsInteger()
? GetSpillTemp(dest, intSpillTempRegisters, ref intLocalAsg)
: GetSpillTemp(dest, vecSpillTempRegisters, ref vecLocalAsg);
info.Sequence = sequence;
info.Temp = temp;
}
node.SetDestination(dstIndex, temp);
Operation spillOp = new Operation(Instruction.Spill, null, Const(info.SpillOffset), temp);
llNode = block.Operations.AddAfter(llNode, spillOp);
}
}
sequence++;
intUsedRegisters |= intLocalAsg | intLocalUse;
vecUsedRegisters |= vecLocalAsg | vecLocalUse;
}
}
return new AllocationResult(intUsedRegisters, vecUsedRegisters, stackAlloc.TotalSize);
}
private static int SelectSpillTemps(int mask0, int mask1)
{
int selection = 0;
int count = 0;
while (count < MaxIROperands && mask0 != 0)
{
int mask = mask0 & -mask0;
selection |= mask;
mask0 &= ~mask;
count++;
}
while (count < MaxIROperands && mask1 != 0)
{
int mask = mask1 & -mask1;
selection |= mask;
mask1 &= ~mask;
count++;
}
Debug.Assert(count == MaxIROperands, "No enough registers for spill temps.");
return selection;
}
private static Operand GetSpillTemp(Operand local, int freeMask, ref int useMask)
{
int selectedReg = BitUtils.LowestBitSet(freeMask & ~useMask);
useMask |= 1 << selectedReg;
return Register(selectedReg, local.Type.ToRegisterType(), local.Type);
}
private static int UsesCount(Operand local)
{
return local.Assignments.Count + local.Uses.Count;
}
private static IEnumerable<BasicBlock> Successors(BasicBlock block)
{
if (block.Next != null)
{
yield return block.Next;
}
if (block.Branch != null)
{
yield return block.Branch;
}
}
}
}

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ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs Normal file
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using ARMeilleure.Translation;
namespace ARMeilleure.CodeGen.RegisterAllocators
{
interface IRegisterAllocator
{
AllocationResult RunPass(
ControlFlowGraph cfg,
StackAllocator stackAlloc,
RegisterMasks regMasks);
}
}

1019
ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs Normal file
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390
ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs Normal file
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using ARMeilleure.IntermediateRepresentation;
using System;
using System.Collections.Generic;
using System.Diagnostics;
using System.Linq;
namespace ARMeilleure.CodeGen.RegisterAllocators
{
class LiveInterval : IComparable<LiveInterval>
{
public const int NotFound = -1;
private LiveInterval _parent;
private SortedSet<int> _usePositions;
public int UsesCount => _usePositions.Count;
private List<LiveRange> _ranges;
private SortedList<int, LiveInterval> _childs;
public bool IsSplit => _childs.Count != 0;
public Operand Local { get; }
public Register Register { get; set; }
public int SpillOffset { get; private set; }
public bool IsSpilled => SpillOffset != -1;
public bool IsFixed { get; }
public bool IsEmpty => _ranges.Count == 0;
public LiveInterval(Operand local = null, LiveInterval parent = null)
{
Local = local;
_parent = parent ?? this;
_usePositions = new SortedSet<int>();
_ranges = new List<LiveRange>();
_childs = new SortedList<int, LiveInterval>();
SpillOffset = -1;
}
public LiveInterval(Register register) : this()
{
IsFixed = true;
Register = register;
}
public void SetStart(int position)
{
if (_ranges.Count != 0)
{
Debug.Assert(position != _ranges[0].End);
_ranges[0] = new LiveRange(position, _ranges[0].End);
}
else
{
_ranges.Add(new LiveRange(position, position + 1));
}
}
public int GetStart()
{
if (_ranges.Count == 0)
{
throw new InvalidOperationException("Empty interval.");
}
return _ranges[0].Start;
}
public void SetEnd(int position)
{
if (_ranges.Count != 0)
{
int lastIdx = _ranges.Count - 1;
Debug.Assert(position != _ranges[lastIdx].Start);
_ranges[lastIdx] = new LiveRange(_ranges[lastIdx].Start, position);
}
else
{
_ranges.Add(new LiveRange(position, position + 1));
}
}
public int GetEnd()
{
if (_ranges.Count == 0)
{
throw new InvalidOperationException("Empty interval.");
}
return _ranges[_ranges.Count - 1].End;
}
public void AddRange(int start, int end)
{
if (start >= end)
{
throw new ArgumentException("Invalid range start position " + start + ", " + end);
}
int index = _ranges.BinarySearch(new LiveRange(start, end));
if (index >= 0)
{
// New range insersects with an existing range, we need to remove
// all the intersecting ranges before adding the new one.
// We also extend the new range as needed, based on the values of
// the existing ranges being removed.
int lIndex = index;
int rIndex = index;
while (lIndex > 0 && _ranges[lIndex - 1].End >= start)
{
lIndex--;
}
while (rIndex + 1 < _ranges.Count && _ranges[rIndex + 1].Start <= end)
{
rIndex++;
}
if (start > _ranges[lIndex].Start)
{
start = _ranges[lIndex].Start;
}
if (end < _ranges[rIndex].End)
{
end = _ranges[rIndex].End;
}
_ranges.RemoveRange(lIndex, (rIndex - lIndex) + 1);
InsertRange(lIndex, start, end);
}
else
{
InsertRange(~index, start, end);
}
}
private void InsertRange(int index, int start, int end)
{
// Here we insert a new range on the ranges list.
// If possible, we extend an existing range rather than inserting a new one.
// We can extend an existing range if any of the following conditions are true:
// - The new range starts right after the end of the previous range on the list.
// - The new range ends right before the start of the next range on the list.
// If both cases are true, we can extend either one. We prefer to extend the
// previous range, and then remove the next one, but theres no specific reason
// for that, extending either one will do.
int? extIndex = null;
if (index > 0 && _ranges[index - 1].End == start)
{
start = _ranges[index - 1].Start;
extIndex = index - 1;
}
if (index < _ranges.Count && _ranges[index].Start == end)
{
end = _ranges[index].End;
if (extIndex.HasValue)
{
_ranges.RemoveAt(index);
}
else
{
extIndex = index;
}
}
if (extIndex.HasValue)
{
_ranges[extIndex.Value] = new LiveRange(start, end);
}
else
{
_ranges.Insert(index, new LiveRange(start, end));
}
}
public void AddUsePosition(int position)
{
_usePositions.Add(position);
}
public bool Overlaps(int position)
{
return _ranges.BinarySearch(new LiveRange(position, position + 1)) >= 0;
}
public bool Overlaps(LiveInterval other)
{
foreach (LiveRange range in other._ranges)
{
if (_ranges.BinarySearch(range) >= 0)
{
return true;
}
}
return false;
}
public int GetOverlapPosition(LiveInterval other)
{
foreach (LiveRange range in other._ranges)
{
int overlapIndex = _ranges.BinarySearch(range);
if (overlapIndex >= 0)
{
// It's possible that we have multiple overlaps within a single interval,
// in this case, we pick the one with the lowest start position, since
// we return the first overlap position.
while (overlapIndex > 0 && _ranges[overlapIndex - 1].End > range.Start)
{
overlapIndex--;
}
LiveRange overlappingRange = _ranges[overlapIndex];
return overlappingRange.Start;
}
}
return NotFound;
}
public IEnumerable<LiveInterval> SplitChilds()
{
return _childs.Values;
}
public IEnumerable<int> UsePositions()
{
return _usePositions;
}
public int FirstUse()
{
if (_usePositions.Count == 0)
{
return NotFound;
}
return _usePositions.First();
}
public int NextUseAfter(int position)
{
foreach (int usePosition in _usePositions)
{
if (usePosition >= position)
{
return usePosition;
}
}
return NotFound;
}
public LiveInterval Split(int position)
{
LiveInterval right = new LiveInterval(Local, _parent);
int splitIndex = 0;
for (; splitIndex < _ranges.Count; splitIndex++)
{
LiveRange range = _ranges[splitIndex];
if (position > range.Start && position <= range.End)
{
right._ranges.Add(new LiveRange(position, range.End));
range = new LiveRange(range.Start, position);
_ranges[splitIndex++] = range;
break;
}
if (range.Start >= position)
{
break;
}
}
if (splitIndex < _ranges.Count)
{
int count = _ranges.Count - splitIndex;
right._ranges.AddRange(_ranges.GetRange(splitIndex, count));
_ranges.RemoveRange(splitIndex, count);
}
foreach (int usePosition in _usePositions.Where(x => x >= position))
{
right._usePositions.Add(usePosition);
}
_usePositions.RemoveWhere(x => x >= position);
Debug.Assert(_ranges.Count != 0, "Left interval is empty after split.");
Debug.Assert(right._ranges.Count != 0, "Right interval is empty after split.");
AddSplitChild(right);
return right;
}
private void AddSplitChild(LiveInterval child)
{
Debug.Assert(!child.IsEmpty, "Trying to insert a empty interval.");
_parent._childs.Add(child.GetStart(), child);
}
public LiveInterval GetSplitChild(int position)
{
if (Overlaps(position))
{
return this;
}
foreach (LiveInterval splitChild in _childs.Values)
{
if (splitChild.Overlaps(position))
{
return splitChild;
}
}
return null;
}
public bool TrySpillWithSiblingOffset()
{
foreach (LiveInterval splitChild in _parent._childs.Values)
{
if (splitChild.IsSpilled)
{
Spill(splitChild.SpillOffset);
return true;
}
}
return false;
}
public void Spill(int offset)
{
SpillOffset = offset;
}
public int CompareTo(LiveInterval other)
{
if (_ranges.Count == 0 || other._ranges.Count == 0)
{
return _ranges.Count.CompareTo(other._ranges.Count);
}
return _ranges[0].Start.CompareTo(other._ranges[0].Start);
}
public override string ToString()
{
return string.Join("; ", _ranges);
}
}
}

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ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs Normal file
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using System;
namespace ARMeilleure.CodeGen.RegisterAllocators
{
struct LiveRange : IComparable<LiveRange>
{
public int Start { get; }
public int End { get; }
public LiveRange(int start, int end)
{
Start = start;
End = end;
}
public int CompareTo(LiveRange other)
{
if (Start < other.End && other.Start < End)
{
return 0;
}
return Start.CompareTo(other.Start);
}
public override string ToString()
{
return $"[{Start}, {End}[";
}
}
}

47
ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs Normal file
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using ARMeilleure.IntermediateRepresentation;
using System;
namespace ARMeilleure.CodeGen.RegisterAllocators
{
struct RegisterMasks
{
public int IntAvailableRegisters { get; }
public int VecAvailableRegisters { get; }
public int IntCallerSavedRegisters { get; }
public int VecCallerSavedRegisters { get; }
public int IntCalleeSavedRegisters { get; }
public int VecCalleeSavedRegisters { get; }
public RegisterMasks(
int intAvailableRegisters,
int vecAvailableRegisters,
int intCallerSavedRegisters,
int vecCallerSavedRegisters,
int intCalleeSavedRegisters,
int vecCalleeSavedRegisters)
{
IntAvailableRegisters = intAvailableRegisters;
VecAvailableRegisters = vecAvailableRegisters;
IntCallerSavedRegisters = intCallerSavedRegisters;
VecCallerSavedRegisters = vecCallerSavedRegisters;
IntCalleeSavedRegisters = intCalleeSavedRegisters;
VecCalleeSavedRegisters = vecCalleeSavedRegisters;
}
public int GetAvailableRegisters(RegisterType type)
{
if (type == RegisterType.Integer)
{
return IntAvailableRegisters;
}
else if (type == RegisterType.Vector)
{
return VecAvailableRegisters;
}
else
{
throw new ArgumentException($"Invalid register type \"{type}\".");
}
}
}
}

27
ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs Normal file
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using ARMeilleure.Common;
using ARMeilleure.IntermediateRepresentation;
using System;
namespace ARMeilleure.CodeGen.RegisterAllocators
{
class StackAllocator
{
private int _offset;
public int TotalSize => _offset;
public int Allocate(OperandType type)
{
return Allocate(type.GetSizeInBytes());
}
public int Allocate(int sizeInBytes)
{
int offset = _offset;
_offset += sizeInBytes;
return offset;
}
}
}

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ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs Normal file
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namespace ARMeilleure.CodeGen.Unwinding
{
struct UnwindInfo
{
public UnwindPushEntry[] PushEntries { get; }
public int PrologueSize { get; }
public int FixedAllocSize { get; }
public UnwindInfo(UnwindPushEntry[] pushEntries, int prologueSize, int fixedAllocSize)
{
PushEntries = pushEntries;
PrologueSize = prologueSize;
FixedAllocSize = fixedAllocSize;
}
}
}

20
ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs Normal file
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using ARMeilleure.IntermediateRepresentation;
namespace ARMeilleure.CodeGen.Unwinding
{
struct UnwindPushEntry
{
public int Index { get; }
public RegisterType Type { get; }
public int StreamEndOffset { get; }
public UnwindPushEntry(int index, RegisterType type, int streamEndOffset)
{
Index = index;
Type = type;
StreamEndOffset = streamEndOffset;
}
}
}

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ARMeilleure/CodeGen/X86/Assembler.cs Normal file
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8
ARMeilleure/CodeGen/X86/CallConvName.cs Normal file
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namespace ARMeilleure.CodeGen.X86
{
enum CallConvName
{
SystemV,
Windows
}
}

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ARMeilleure/CodeGen/X86/CallingConvention.cs Normal file
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using System;
using System.Runtime.InteropServices;
namespace ARMeilleure.CodeGen.X86
{
static class CallingConvention
{
private const int RegistersMask = 0xffff;
public static int GetIntAvailableRegisters()
{
return RegistersMask & ~(1 << (int)X86Register.Rsp);
}
public static int GetVecAvailableRegisters()
{
return RegistersMask;
}
public static int GetIntCallerSavedRegisters()
{
if (GetCurrentCallConv() == CallConvName.Windows)
{
return (1 << (int)X86Register.Rax) |
(1 << (int)X86Register.Rcx) |
(1 << (int)X86Register.Rdx) |
(1 << (int)X86Register.R8) |
(1 << (int)X86Register.R9) |
(1 << (int)X86Register.R10) |
(1 << (int)X86Register.R11);
}
else /* if (GetCurrentCallConv() == CallConvName.SystemV) */
{
return (1 << (int)X86Register.Rax) |
(1 << (int)X86Register.Rcx) |
(1 << (int)X86Register.Rdx) |
(1 << (int)X86Register.Rsi) |
(1 << (int)X86Register.Rdi) |
(1 << (int)X86Register.R8) |
(1 << (int)X86Register.R9) |
(1 << (int)X86Register.R10) |
(1 << (int)X86Register.R11);
}
}
public static int GetVecCallerSavedRegisters()
{
if (GetCurrentCallConv() == CallConvName.Windows)
{
return (1 << (int)X86Register.Xmm0) |
(1 << (int)X86Register.Xmm1) |
(1 << (int)X86Register.Xmm2) |
(1 << (int)X86Register.Xmm3) |
(1 << (int)X86Register.Xmm4) |
(1 << (int)X86Register.Xmm5);
}
else /* if (GetCurrentCallConv() == CallConvName.SystemV) */
{
return RegistersMask;
}
}
public static int GetIntCalleeSavedRegisters()
{
return GetIntCallerSavedRegisters() ^ RegistersMask;
}
public static int GetVecCalleeSavedRegisters()
{
return GetVecCallerSavedRegisters() ^ RegistersMask;
}
public static int GetArgumentsOnRegsCount()
{
return 4;
}
public static int GetIntArgumentsOnRegsCount()
{
return 6;
}
public static int GetVecArgumentsOnRegsCount()
{
return 8;
}
public static X86Register GetIntArgumentRegister(int index)
{
if (GetCurrentCallConv() == CallConvName.Windows)
{
switch (index)
{
case 0: return X86Register.Rcx;
case 1: return X86Register.Rdx;
case 2: return X86Register.R8;
case 3: return X86Register.R9;
}
}
else /* if (GetCurrentCallConv() == CallConvName.SystemV) */
{
switch (index)
{
case 0: return X86Register.Rdi;
case 1: return X86Register.Rsi;
case 2: return X86Register.Rdx;
case 3: return X86Register.Rcx;
case 4: return X86Register.R8;
case 5: return X86Register.R9;
}
}
throw new ArgumentOutOfRangeException(nameof(index));
}
public static X86Register GetVecArgumentRegister(int index)
{
int count;
if (GetCurrentCallConv() == CallConvName.Windows)
{
count = 4;
}
else /* if (GetCurrentCallConv() == CallConvName.SystemV) */
{
count = 8;
}
if ((uint)index < count)
{
return X86Register.Xmm0 + index;
}
throw new ArgumentOutOfRangeException(nameof(index));
}
public static X86Register GetIntReturnRegister()
{
return X86Register.Rax;
}
public static X86Register GetIntReturnRegisterHigh()
{
return X86Register.Rdx;
}
public static X86Register GetVecReturnRegister()
{
return X86Register.Xmm0;
}
public static CallConvName GetCurrentCallConv()
{
return RuntimeInformation.IsOSPlatform(OSPlatform.Windows)
? CallConvName.Windows
: CallConvName.SystemV;
}
}
}

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using ARMeilleure.CodeGen.RegisterAllocators;
using ARMeilleure.Common;
using ARMeilleure.IntermediateRepresentation;
using System.Collections.Generic;
using System.Diagnostics;
using System.IO;
namespace ARMeilleure.CodeGen.X86
{
class CodeGenContext
{
private const int ReservedBytesForJump = 1;
private Stream _stream;
public int StreamOffset => (int)_stream.Length;
public AllocationResult AllocResult { get; }
public Assembler Assembler { get; }
public BasicBlock CurrBlock { get; private set; }
public int CallArgsRegionSize { get; }
public int XmmSaveRegionSize { get; }
private long[] _blockOffsets;
private struct Jump
{
public bool IsConditional { get; }
public X86Condition Condition { get; }
public BasicBlock Target { get; }
public long JumpPosition { get; }
public long RelativeOffset { get; set; }
public int InstSize { get; set; }
public Jump(BasicBlock target, long jumpPosition)
{
IsConditional = false;
Condition = 0;
Target = target;
JumpPosition = jumpPosition;
RelativeOffset = 0;
InstSize = 0;
}
public Jump(X86Condition condition, BasicBlock target, long jumpPosition)
{
IsConditional = true;
Condition = condition;
Target = target;
JumpPosition = jumpPosition;
RelativeOffset = 0;
InstSize = 0;
}
}
private List<Jump> _jumps;
private X86Condition _jNearCondition;
private long _jNearPosition;
private int _jNearLength;
public CodeGenContext(Stream stream, AllocationResult allocResult, int maxCallArgs, int blocksCount)
{
_stream = stream;
AllocResult = allocResult;
Assembler = new Assembler(stream);
CallArgsRegionSize = GetCallArgsRegionSize(allocResult, maxCallArgs, out int xmmSaveRegionSize);
XmmSaveRegionSize = xmmSaveRegionSize;
_blockOffsets = new long[blocksCount];
_jumps = new List<Jump>();
}
private int GetCallArgsRegionSize(AllocationResult allocResult, int maxCallArgs, out int xmmSaveRegionSize)
{
// We need to add 8 bytes to the total size, as the call to this
// function already pushed 8 bytes (the return address).
int intMask = CallingConvention.GetIntCalleeSavedRegisters() & allocResult.IntUsedRegisters;
int vecMask = CallingConvention.GetVecCalleeSavedRegisters() & allocResult.VecUsedRegisters;
xmmSaveRegionSize = BitUtils.CountBits(vecMask) * 16;
int calleeSaveRegionSize = BitUtils.CountBits(intMask) * 8 + xmmSaveRegionSize + 8;
int argsCount = maxCallArgs;
if (argsCount < 0)
{
// When the function has no calls, argsCount is -1.
// In this case, we don't need to allocate the shadow space.
argsCount = 0;
}
else if (argsCount < 4)
{
// The ABI mandates that the space for at least 4 arguments
// is reserved on the stack (this is called shadow space).
argsCount = 4;
}
int frameSize = calleeSaveRegionSize + allocResult.SpillRegionSize;
// TODO: Instead of always multiplying by 16 (the largest possible size of a variable,
// since a V128 has 16 bytes), we should calculate the exact size consumed by the
// arguments passed to the called functions on the stack.
int callArgsAndFrameSize = frameSize + argsCount * 16;
// Ensure that the Stack Pointer will be aligned to 16 bytes.
callArgsAndFrameSize = (callArgsAndFrameSize + 0xf) & ~0xf;
return callArgsAndFrameSize - frameSize;
}
public void EnterBlock(BasicBlock block)
{
_blockOffsets[block.Index] = _stream.Position;
CurrBlock = block;
}
public void JumpTo(BasicBlock target)
{
_jumps.Add(new Jump(target, _stream.Position));
WritePadding(ReservedBytesForJump);
}
public void JumpTo(X86Condition condition, BasicBlock target)
{
_jumps.Add(new Jump(condition, target, _stream.Position));
WritePadding(ReservedBytesForJump);
}
public void JumpToNear(X86Condition condition)
{
_jNearCondition = condition;
_jNearPosition = _stream.Position;
_jNearLength = Assembler.GetJccLength(0);
_stream.Seek(_jNearLength, SeekOrigin.Current);
}
public void JumpHere()
{
long currentPosition = _stream.Position;
_stream.Seek(_jNearPosition, SeekOrigin.Begin);
long offset = currentPosition - (_jNearPosition + _jNearLength);
Debug.Assert(_jNearLength == Assembler.GetJccLength(offset), "Relative offset doesn't fit on near jump.");
Assembler.Jcc(_jNearCondition, offset);
_stream.Seek(currentPosition, SeekOrigin.Begin);
}
private void WritePadding(int size)
{
while (size-- > 0)
{
_stream.WriteByte(0);
}
}
public byte[] GetCode()
{
// Write jump relative offsets.
bool modified;
do
{
modified = false;
for (int index = 0; index < _jumps.Count; index++)
{
Jump jump = _jumps[index];
long jumpTarget = _blockOffsets[jump.Target.Index];
long offset = jumpTarget - jump.JumpPosition;
if (offset < 0)
{
for (int index2 = index - 1; index2 >= 0; index2--)
{
Jump jump2 = _jumps[index2];
if (jump2.JumpPosition < jumpTarget)
{
break;
}
offset -= jump2.InstSize - ReservedBytesForJump;
}
}
else
{
for (int index2 = index + 1; index2 < _jumps.Count; index2++)
{
Jump jump2 = _jumps[index2];
if (jump2.JumpPosition >= jumpTarget)
{
break;
}
offset += jump2.InstSize - ReservedBytesForJump;
}
offset -= ReservedBytesForJump;
}
if (jump.IsConditional)
{
jump.InstSize = Assembler.GetJccLength(offset);
}
else
{
jump.InstSize = Assembler.GetJmpLength(offset);
}
// The jump is relative to the next instruction, not the current one.
// Since we didn't know the next instruction address when calculating
// the offset (as the size of the current jump instruction was not know),
// we now need to compensate the offset with the jump instruction size.
// It's also worth to note that:
// - This is only needed for backward jumps.
// - The GetJmpLength and GetJccLength also compensates the offset
// internally when computing the jump instruction size.
if (offset < 0)
{
offset -= jump.InstSize;
}
if (jump.RelativeOffset != offset)
{
modified = true;
}
jump.RelativeOffset = offset;
_jumps[index] = jump;
}
}
while (modified);
// Write the code, ignoring the dummy bytes after jumps, into a new stream.
_stream.Seek(0, SeekOrigin.Begin);
using (MemoryStream codeStream = new MemoryStream())
{
Assembler assembler = new Assembler(codeStream);
byte[] buffer;
for (int index = 0; index < _jumps.Count; index++)
{
Jump jump = _jumps[index];
buffer = new byte[jump.JumpPosition - _stream.Position];
_stream.Read(buffer, 0, buffer.Length);
_stream.Seek(ReservedBytesForJump, SeekOrigin.Current);
codeStream.Write(buffer);
if (jump.IsConditional)
{
assembler.Jcc(jump.Condition, jump.RelativeOffset);
}
else
{
assembler.Jmp(jump.RelativeOffset);
}
}
buffer = new byte[_stream.Length - _stream.Position];
_stream.Read(buffer, 0, buffer.Length);
codeStream.Write(buffer);
return codeStream.ToArray();
}
}
}
}

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ARMeilleure/CodeGen/X86/HardwareCapabilities.cs Normal file
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using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
namespace ARMeilleure.CodeGen.X86
{
static class HardwareCapabilities
{
private delegate ulong GetFeatureInfo();
private static ulong _featureInfo;
public static bool SupportsSse3 => (_featureInfo & (1UL << 0)) != 0;
public static bool SupportsPclmulqdq => (_featureInfo & (1UL << 1)) != 0;
public static bool SupportsSsse3 => (_featureInfo & (1UL << 9)) != 0;
public static bool SupportsFma => (_featureInfo & (1UL << 12)) != 0;
public static bool SupportsCx16 => (_featureInfo & (1UL << 13)) != 0;
public static bool SupportsSse41 => (_featureInfo & (1UL << 19)) != 0;
public static bool SupportsSse42 => (_featureInfo & (1UL << 20)) != 0;
public static bool SupportsPopcnt => (_featureInfo & (1UL << 23)) != 0;
public static bool SupportsAesni => (_featureInfo & (1UL << 25)) != 0;
public static bool SupportsAvx => (_featureInfo & (1UL << 28)) != 0;
public static bool SupportsF16c => (_featureInfo & (1UL << 29)) != 0;
public static bool SupportsSse => (_featureInfo & (1UL << 32 + 25)) != 0;
public static bool SupportsSse2 => (_featureInfo & (1UL << 32 + 26)) != 0;
public static bool ForceLegacySse { get; set; }
public static bool SupportsVexEncoding => !ForceLegacySse && SupportsAvx;
static HardwareCapabilities()
{
EmitterContext context = new EmitterContext();
Operand featureInfo = context.CpuId();
context.Return(featureInfo);
ControlFlowGraph cfg = context.GetControlFlowGraph();
OperandType[] argTypes = new OperandType[0];
GetFeatureInfo getFeatureInfo = Compiler.Compile<GetFeatureInfo>(
cfg,
argTypes,
OperandType.I64,
CompilerOptions.HighCq);
_featureInfo = getFeatureInfo();
}
}
}

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ARMeilleure/CodeGen/X86/IntrinsicInfo.cs Normal file
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namespace ARMeilleure.CodeGen.X86
{
struct IntrinsicInfo
{
public X86Instruction Inst { get; }
public IntrinsicType Type { get; }
public IntrinsicInfo(X86Instruction inst, IntrinsicType type)
{
Inst = inst;
Type = type;
}
}
}

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ARMeilleure/CodeGen/X86/IntrinsicTable.cs Normal file
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using ARMeilleure.Common;
using ARMeilleure.IntermediateRepresentation;
namespace ARMeilleure.CodeGen.X86
{
static class IntrinsicTable
{
private const int BadOp = 0;
private static IntrinsicInfo[] _intrinTable;
static IntrinsicTable()
{
_intrinTable = new IntrinsicInfo[EnumUtils.GetCount(typeof(Intrinsic))];
Add(Intrinsic.X86Addpd, new IntrinsicInfo(X86Instruction.Addpd, IntrinsicType.Binary));
Add(Intrinsic.X86Addps, new IntrinsicInfo(X86Instruction.Addps, IntrinsicType.Binary));
Add(Intrinsic.X86Addsd, new IntrinsicInfo(X86Instruction.Addsd, IntrinsicType.Binary));
Add(Intrinsic.X86Addss, new IntrinsicInfo(X86Instruction.Addss, IntrinsicType.Binary));
Add(Intrinsic.X86Andnpd, new IntrinsicInfo(X86Instruction.Andnpd, IntrinsicType.Binary));
Add(Intrinsic.X86Andnps, new IntrinsicInfo(X86Instruction.Andnps, IntrinsicType.Binary));
Add(Intrinsic.X86Cmppd, new IntrinsicInfo(X86Instruction.Cmppd, IntrinsicType.TernaryImm));
Add(Intrinsic.X86Cmpps, new IntrinsicInfo(X86Instruction.Cmpps, IntrinsicType.TernaryImm));
Add(Intrinsic.X86Cmpsd, new IntrinsicInfo(X86Instruction.Cmpsd, IntrinsicType.TernaryImm));
Add(Intrinsic.X86Cmpss, new IntrinsicInfo(X86Instruction.Cmpss, IntrinsicType.TernaryImm));
Add(Intrinsic.X86Comisdeq, new IntrinsicInfo(X86Instruction.Comisd, IntrinsicType.Comis_));
Add(Intrinsic.X86Comisdge, new IntrinsicInfo(X86Instruction.Comisd, IntrinsicType.Comis_));
Add(Intrinsic.X86Comisdlt, new IntrinsicInfo(X86Instruction.Comisd, IntrinsicType.Comis_));
Add(Intrinsic.X86Comisseq, new IntrinsicInfo(X86Instruction.Comiss, IntrinsicType.Comis_));
Add(Intrinsic.X86Comissge, new IntrinsicInfo(X86Instruction.Comiss, IntrinsicType.Comis_));
Add(Intrinsic.X86Comisslt, new IntrinsicInfo(X86Instruction.Comiss, IntrinsicType.Comis_));
Add(Intrinsic.X86Cvtdq2pd, new IntrinsicInfo(X86Instruction.Cvtdq2pd, IntrinsicType.Unary));
Add(Intrinsic.X86Cvtdq2ps, new IntrinsicInfo(X86Instruction.Cvtdq2ps, IntrinsicType.Unary));
Add(Intrinsic.X86Cvtpd2dq, new IntrinsicInfo(X86Instruction.Cvtpd2dq, IntrinsicType.Unary));
Add(Intrinsic.X86Cvtpd2ps, new IntrinsicInfo(X86Instruction.Cvtpd2ps, IntrinsicType.Unary));
Add(Intrinsic.X86Cvtps2dq, new IntrinsicInfo(X86Instruction.Cvtps2dq, IntrinsicType.Unary));
Add(Intrinsic.X86Cvtps2pd, new IntrinsicInfo(X86Instruction.Cvtps2pd, IntrinsicType.Unary));
Add(Intrinsic.X86Cvtsd2si, new IntrinsicInfo(X86Instruction.Cvtsd2si, IntrinsicType.UnaryToGpr));
Add(Intrinsic.X86Cvtsd2ss, new IntrinsicInfo(X86Instruction.Cvtsd2ss, IntrinsicType.Binary));
Add(Intrinsic.X86Cvtss2sd, new IntrinsicInfo(X86Instruction.Cvtss2sd, IntrinsicType.Binary));
Add(Intrinsic.X86Divpd, new IntrinsicInfo(X86Instruction.Divpd, IntrinsicType.Binary));
Add(Intrinsic.X86Divps, new IntrinsicInfo(X86Instruction.Divps, IntrinsicType.Binary));
Add(Intrinsic.X86Divsd, new IntrinsicInfo(X86Instruction.Divsd, IntrinsicType.Binary));
Add(Intrinsic.X86Divss, new IntrinsicInfo(X86Instruction.Divss, IntrinsicType.Binary));
Add(Intrinsic.X86Haddpd, new IntrinsicInfo(X86Instruction.Haddpd, IntrinsicType.Binary));
Add(Intrinsic.X86Haddps, new IntrinsicInfo(X86Instruction.Haddps, IntrinsicType.Binary));
Add(Intrinsic.X86Maxpd, new IntrinsicInfo(X86Instruction.Maxpd, IntrinsicType.Binary));
Add(Intrinsic.X86Maxps, new IntrinsicInfo(X86Instruction.Maxps, IntrinsicType.Binary));
Add(Intrinsic.X86Maxsd, new IntrinsicInfo(X86Instruction.Maxsd, IntrinsicType.Binary));
Add(Intrinsic.X86Maxss, new IntrinsicInfo(X86Instruction.Maxss, IntrinsicType.Binary));
Add(Intrinsic.X86Minpd, new IntrinsicInfo(X86Instruction.Minpd, IntrinsicType.Binary));
Add(Intrinsic.X86Minps, new IntrinsicInfo(X86Instruction.Minps, IntrinsicType.Binary));
Add(Intrinsic.X86Minsd, new IntrinsicInfo(X86Instruction.Minsd, IntrinsicType.Binary));
Add(Intrinsic.X86Minss, new IntrinsicInfo(X86Instruction.Minss, IntrinsicType.Binary));
Add(Intrinsic.X86Movhlps, new IntrinsicInfo(X86Instruction.Movhlps, IntrinsicType.Binary));
Add(Intrinsic.X86Movlhps, new IntrinsicInfo(X86Instruction.Movlhps, IntrinsicType.Binary));
Add(Intrinsic.X86Mulpd, new IntrinsicInfo(X86Instruction.Mulpd, IntrinsicType.Binary));
Add(Intrinsic.X86Mulps, new IntrinsicInfo(X86Instruction.Mulps, IntrinsicType.Binary));
Add(Intrinsic.X86Mulsd, new IntrinsicInfo(X86Instruction.Mulsd, IntrinsicType.Binary));
Add(Intrinsic.X86Mulss, new IntrinsicInfo(X86Instruction.Mulss, IntrinsicType.Binary));
Add(Intrinsic.X86Paddb, new IntrinsicInfo(X86Instruction.Paddb, IntrinsicType.Binary));
Add(Intrinsic.X86Paddd, new IntrinsicInfo(X86Instruction.Paddd, IntrinsicType.Binary));
Add(Intrinsic.X86Paddq, new IntrinsicInfo(X86Instruction.Paddq, IntrinsicType.Binary));
Add(Intrinsic.X86Paddw, new IntrinsicInfo(X86Instruction.Paddw, IntrinsicType.Binary));
Add(Intrinsic.X86Pand, new IntrinsicInfo(X86Instruction.Pand, IntrinsicType.Binary));
Add(Intrinsic.X86Pandn, new IntrinsicInfo(X86Instruction.Pandn, IntrinsicType.Binary));
Add(Intrinsic.X86Pavgb, new IntrinsicInfo(X86Instruction.Pavgb, IntrinsicType.Binary));
Add(Intrinsic.X86Pavgw, new IntrinsicInfo(X86Instruction.Pavgw, IntrinsicType.Binary));
Add(Intrinsic.X86Pblendvb, new IntrinsicInfo(X86Instruction.Pblendvb, IntrinsicType.Ternary));
Add(Intrinsic.X86Pcmpeqb, new IntrinsicInfo(X86Instruction.Pcmpeqb, IntrinsicType.Binary));
Add(Intrinsic.X86Pcmpeqd, new IntrinsicInfo(X86Instruction.Pcmpeqd, IntrinsicType.Binary));
Add(Intrinsic.X86Pcmpeqq, new IntrinsicInfo(X86Instruction.Pcmpeqq, IntrinsicType.Binary));
Add(Intrinsic.X86Pcmpeqw, new IntrinsicInfo(X86Instruction.Pcmpeqw, IntrinsicType.Binary));
Add(Intrinsic.X86Pcmpgtb, new IntrinsicInfo(X86Instruction.Pcmpgtb, IntrinsicType.Binary));
Add(Intrinsic.X86Pcmpgtd, new IntrinsicInfo(X86Instruction.Pcmpgtd, IntrinsicType.Binary));
Add(Intrinsic.X86Pcmpgtq, new IntrinsicInfo(X86Instruction.Pcmpgtq, IntrinsicType.Binary));
Add(Intrinsic.X86Pcmpgtw, new IntrinsicInfo(X86Instruction.Pcmpgtw, IntrinsicType.Binary));
Add(Intrinsic.X86Pmaxsb, new IntrinsicInfo(X86Instruction.Pmaxsb, IntrinsicType.Binary));
Add(Intrinsic.X86Pmaxsd, new IntrinsicInfo(X86Instruction.Pmaxsd, IntrinsicType.Binary));
Add(Intrinsic.X86Pmaxsw, new IntrinsicInfo(X86Instruction.Pmaxsw, IntrinsicType.Binary));
Add(Intrinsic.X86Pmaxub, new IntrinsicInfo(X86Instruction.Pmaxub, IntrinsicType.Binary));
Add(Intrinsic.X86Pmaxud, new IntrinsicInfo(X86Instruction.Pmaxud, IntrinsicType.Binary));
Add(Intrinsic.X86Pmaxuw, new IntrinsicInfo(X86Instruction.Pmaxuw, IntrinsicType.Binary));
Add(Intrinsic.X86Pminsb, new IntrinsicInfo(X86Instruction.Pminsb, IntrinsicType.Binary));
Add(Intrinsic.X86Pminsd, new IntrinsicInfo(X86Instruction.Pminsd, IntrinsicType.Binary));
Add(Intrinsic.X86Pminsw, new IntrinsicInfo(X86Instruction.Pminsw, IntrinsicType.Binary));
Add(Intrinsic.X86Pminub, new IntrinsicInfo(X86Instruction.Pminub, IntrinsicType.Binary));
Add(Intrinsic.X86Pminud, new IntrinsicInfo(X86Instruction.Pminud, IntrinsicType.Binary));
Add(Intrinsic.X86Pminuw, new IntrinsicInfo(X86Instruction.Pminuw, IntrinsicType.Binary));
Add(Intrinsic.X86Pmovsxbw, new IntrinsicInfo(X86Instruction.Pmovsxbw, IntrinsicType.Unary));
Add(Intrinsic.X86Pmovsxdq, new IntrinsicInfo(X86Instruction.Pmovsxdq, IntrinsicType.Unary));
Add(Intrinsic.X86Pmovsxwd, new IntrinsicInfo(X86Instruction.Pmovsxwd, IntrinsicType.Unary));
Add(Intrinsic.X86Pmovzxbw, new IntrinsicInfo(X86Instruction.Pmovzxbw, IntrinsicType.Unary));
Add(Intrinsic.X86Pmovzxdq, new IntrinsicInfo(X86Instruction.Pmovzxdq, IntrinsicType.Unary));
Add(Intrinsic.X86Pmovzxwd, new IntrinsicInfo(X86Instruction.Pmovzxwd, IntrinsicType.Unary));
Add(Intrinsic.X86Pmulld, new IntrinsicInfo(X86Instruction.Pmulld, IntrinsicType.Binary));
Add(Intrinsic.X86Pmullw, new IntrinsicInfo(X86Instruction.Pmullw, IntrinsicType.Binary));
Add(Intrinsic.X86Popcnt, new IntrinsicInfo(X86Instruction.Popcnt, IntrinsicType.PopCount));
Add(Intrinsic.X86Por, new IntrinsicInfo(X86Instruction.Por, IntrinsicType.Binary));
Add(Intrinsic.X86Pshufb, new IntrinsicInfo(X86Instruction.Pshufb, IntrinsicType.Binary));
Add(Intrinsic.X86Pslld, new IntrinsicInfo(X86Instruction.Pslld, IntrinsicType.Binary));
Add(Intrinsic.X86Pslldq, new IntrinsicInfo(X86Instruction.Pslldq, IntrinsicType.Binary));
Add(Intrinsic.X86Psllq, new IntrinsicInfo(X86Instruction.Psllq, IntrinsicType.Binary));
Add(Intrinsic.X86Psllw, new IntrinsicInfo(X86Instruction.Psllw, IntrinsicType.Binary));
Add(Intrinsic.X86Psrad, new IntrinsicInfo(X86Instruction.Psrad, IntrinsicType.Binary));
Add(Intrinsic.X86Psraw, new IntrinsicInfo(X86Instruction.Psraw, IntrinsicType.Binary));
Add(Intrinsic.X86Psrld, new IntrinsicInfo(X86Instruction.Psrld, IntrinsicType.Binary));
Add(Intrinsic.X86Psrlq, new IntrinsicInfo(X86Instruction.Psrlq, IntrinsicType.Binary));
Add(Intrinsic.X86Psrldq, new IntrinsicInfo(X86Instruction.Psrldq, IntrinsicType.Binary));
Add(Intrinsic.X86Psrlw, new IntrinsicInfo(X86Instruction.Psrlw, IntrinsicType.Binary));
Add(Intrinsic.X86Psubb, new IntrinsicInfo(X86Instruction.Psubb, IntrinsicType.Binary));
Add(Intrinsic.X86Psubd, new IntrinsicInfo(X86Instruction.Psubd, IntrinsicType.Binary));
Add(Intrinsic.X86Psubq, new IntrinsicInfo(X86Instruction.Psubq, IntrinsicType.Binary));
Add(Intrinsic.X86Psubw, new IntrinsicInfo(X86Instruction.Psubw, IntrinsicType.Binary));
Add(Intrinsic.X86Punpckhbw, new IntrinsicInfo(X86Instruction.Punpckhbw, IntrinsicType.Binary));
Add(Intrinsic.X86Punpckhdq, new IntrinsicInfo(X86Instruction.Punpckhdq, IntrinsicType.Binary));
Add(Intrinsic.X86Punpckhqdq, new IntrinsicInfo(X86Instruction.Punpckhqdq, IntrinsicType.Binary));
Add(Intrinsic.X86Punpckhwd, new IntrinsicInfo(X86Instruction.Punpckhwd, IntrinsicType.Binary));
Add(Intrinsic.X86Punpcklbw, new IntrinsicInfo(X86Instruction.Punpcklbw, IntrinsicType.Binary));
Add(Intrinsic.X86Punpckldq, new IntrinsicInfo(X86Instruction.Punpckldq, IntrinsicType.Binary));
Add(Intrinsic.X86Punpcklqdq, new IntrinsicInfo(X86Instruction.Punpcklqdq, IntrinsicType.Binary));
Add(Intrinsic.X86Punpcklwd, new IntrinsicInfo(X86Instruction.Punpcklwd, IntrinsicType.Binary));
Add(Intrinsic.X86Pxor, new IntrinsicInfo(X86Instruction.Pxor, IntrinsicType.Binary));
Add(Intrinsic.X86Rcpps, new IntrinsicInfo(X86Instruction.Rcpps, IntrinsicType.Unary));
Add(Intrinsic.X86Rcpss, new IntrinsicInfo(X86Instruction.Rcpss, IntrinsicType.Unary));
Add(Intrinsic.X86Roundpd, new IntrinsicInfo(X86Instruction.Roundpd, IntrinsicType.BinaryImm));
Add(Intrinsic.X86Roundps, new IntrinsicInfo(X86Instruction.Roundps, IntrinsicType.BinaryImm));
Add(Intrinsic.X86Roundsd, new IntrinsicInfo(X86Instruction.Roundsd, IntrinsicType.BinaryImm));
Add(Intrinsic.X86Roundss, new IntrinsicInfo(X86Instruction.Roundss, IntrinsicType.BinaryImm));
Add(Intrinsic.X86Rsqrtps, new IntrinsicInfo(X86Instruction.Rsqrtps, IntrinsicType.Unary));
Add(Intrinsic.X86Rsqrtss, new IntrinsicInfo(X86Instruction.Rsqrtss, IntrinsicType.Unary));
Add(Intrinsic.X86Shufpd, new IntrinsicInfo(X86Instruction.Shufpd, IntrinsicType.TernaryImm));
Add(Intrinsic.X86Shufps, new IntrinsicInfo(X86Instruction.Shufps, IntrinsicType.TernaryImm));
Add(Intrinsic.X86Sqrtpd, new IntrinsicInfo(X86Instruction.Sqrtpd, IntrinsicType.Unary));
Add(Intrinsic.X86Sqrtps, new IntrinsicInfo(X86Instruction.Sqrtps, IntrinsicType.Unary));
Add(Intrinsic.X86Sqrtsd, new IntrinsicInfo(X86Instruction.Sqrtsd, IntrinsicType.Unary));
Add(Intrinsic.X86Sqrtss, new IntrinsicInfo(X86Instruction.Sqrtss, IntrinsicType.Unary));
Add(Intrinsic.X86Subpd, new IntrinsicInfo(X86Instruction.Subpd, IntrinsicType.Binary));
Add(Intrinsic.X86Subps, new IntrinsicInfo(X86Instruction.Subps, IntrinsicType.Binary));
Add(Intrinsic.X86Subsd, new IntrinsicInfo(X86Instruction.Subsd, IntrinsicType.Binary));
Add(Intrinsic.X86Subss, new IntrinsicInfo(X86Instruction.Subss, IntrinsicType.Binary));
Add(Intrinsic.X86Unpckhpd, new IntrinsicInfo(X86Instruction.Unpckhpd, IntrinsicType.Binary));
Add(Intrinsic.X86Unpckhps, new IntrinsicInfo(X86Instruction.Unpckhps, IntrinsicType.Binary));
Add(Intrinsic.X86Unpcklpd, new IntrinsicInfo(X86Instruction.Unpcklpd, IntrinsicType.Binary));
Add(Intrinsic.X86Unpcklps, new IntrinsicInfo(X86Instruction.Unpcklps, IntrinsicType.Binary));
Add(Intrinsic.X86Xorpd, new IntrinsicInfo(X86Instruction.Xorpd, IntrinsicType.Binary));
Add(Intrinsic.X86Xorps, new IntrinsicInfo(X86Instruction.Xorps, IntrinsicType.Binary));
}
private static void Add(Intrinsic intrin, IntrinsicInfo info)
{
_intrinTable[(int)intrin] = info;
}
public static IntrinsicInfo GetInfo(Intrinsic intrin)
{
return _intrinTable[(int)intrin];
}
}
}

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ARMeilleure/CodeGen/X86/IntrinsicType.cs Normal file
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namespace ARMeilleure.CodeGen.X86
{
enum IntrinsicType
{
Comis_,
PopCount,
Unary,
UnaryToGpr,
Binary,
BinaryImm,
Ternary,
TernaryImm
}
}

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ARMeilleure/CodeGen/X86/X86Condition.cs Normal file
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namespace ARMeilleure.CodeGen.X86
{
enum X86Condition
{
Overflow = 0x0,
NotOverflow = 0x1,
Below = 0x2,
AboveOrEqual = 0x3,
Equal = 0x4,
NotEqual = 0x5,
BelowOrEqual = 0x6,
Above = 0x7,
Sign = 0x8,
NotSign = 0x9,
ParityEven = 0xa,
ParityOdd = 0xb,
Less = 0xc,
GreaterOrEqual = 0xd,
LessOrEqual = 0xe,
Greater = 0xf
}
}

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namespace ARMeilleure.CodeGen.X86
{
enum X86Instruction
{
Add,
Addpd,
Addps,
Addsd,
Addss,
And,
Andnpd,
Andnps,
Bsr,
Bswap,
Call,
Cmovcc,
Cmp,
Cmppd,
Cmpps,
Cmpsd,
Cmpss,
Cmpxchg16b,
Comisd,
Comiss,
Cpuid,
Cvtdq2pd,
Cvtdq2ps,
Cvtpd2dq,
Cvtpd2ps,
Cvtps2dq,
Cvtps2pd,
Cvtsd2si,
Cvtsd2ss,
Cvtsi2sd,
Cvtsi2ss,
Cvtss2sd,
Div,
Divpd,
Divps,
Divsd,
Divss,
Haddpd,
Haddps,
Idiv,
Imul,
Imul128,
Insertps,
Lea,
Maxpd,
Maxps,
Maxsd,
Maxss,
Minpd,
Minps,
Minsd,
Minss,
Mov,
Mov16,
Mov8,
Movd,
Movdqu,
Movhlps,
Movlhps,
Movq,
Movsd,
Movss,
Movsx16,
Movsx32,
Movsx8,
Movzx16,
Movzx8,
Mul128,
Mulpd,
Mulps,
Mulsd,
Mulss,
Neg,
Not,
Or,
Paddb,
Paddd,
Paddq,
Paddw,
Pand,
Pandn,
Pavgb,
Pavgw,
Pblendvb,
Pcmpeqb,
Pcmpeqd,
Pcmpeqq,
Pcmpeqw,
Pcmpgtb,
Pcmpgtd,
Pcmpgtq,
Pcmpgtw,
Pextrb,
Pextrd,
Pextrq,
Pextrw,
Pinsrb,
Pinsrd,
Pinsrq,
Pinsrw,
Pmaxsb,
Pmaxsd,
Pmaxsw,
Pmaxub,
Pmaxud,
Pmaxuw,
Pminsb,
Pminsd,
Pminsw,
Pminub,
Pminud,
Pminuw,
Pmovsxbw,
Pmovsxdq,
Pmovsxwd,
Pmovzxbw,
Pmovzxdq,
Pmovzxwd,
Pmulld,
Pmullw,
Pop,
Popcnt,
Por,
Pshufb,
Pshufd,
Pslld,
Pslldq,
Psllq,
Psllw,
Psrad,
Psraw,
Psrld,
Psrlq,
Psrldq,
Psrlw,
Psubb,
Psubd,
Psubq,
Psubw,
Punpckhbw,
Punpckhdq,
Punpckhqdq,
Punpckhwd,
Punpcklbw,
Punpckldq,
Punpcklqdq,
Punpcklwd,
Push,
Pxor,
Rcpps,
Rcpss,
Ror,
Roundpd,
Roundps,
Roundsd,
Roundss,
Rsqrtps,
Rsqrtss,
Sar,
Setcc,
Shl,
Shr,
Shufpd,
Shufps,
Sqrtpd,
Sqrtps,
Sqrtsd,
Sqrtss,
Sub,
Subpd,
Subps,
Subsd,
Subss,
Test,
Unpckhpd,
Unpckhps,
Unpcklpd,
Unpcklps,
Vpblendvb,
Xor,
Xorpd,
Xorps,
Count
}
}

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ARMeilleure/CodeGen/X86/X86Register.cs Normal file
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namespace ARMeilleure.CodeGen.X86
{
enum X86Register
{
Invalid = -1,
Rax = 0,
Rcx = 1,
Rdx = 2,
Rbx = 3,
Rsp = 4,
Rbp = 5,
Rsi = 6,
Rdi = 7,
R8 = 8,
R9 = 9,
R10 = 10,
R11 = 11,
R12 = 12,
R13 = 13,
R14 = 14,
R15 = 15,
Xmm0 = 0,
Xmm1 = 1,
Xmm2 = 2,
Xmm3 = 3,
Xmm4 = 4,
Xmm5 = 5,
Xmm6 = 6,
Xmm7 = 7,
Xmm8 = 8,
Xmm9 = 9,
Xmm10 = 10,
Xmm11 = 11,
Xmm12 = 12,
Xmm13 = 13,
Xmm14 = 14,
Xmm15 = 15
}
}

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using System.Collections;
using System.Collections.Generic;
namespace ARMeilleure.Common
{
class BitMap : IEnumerable<int>
{
private const int IntSize = 32;
private const int IntMask = IntSize - 1;
private List<int> _masks;
public BitMap(int initialCapacity)
{
int count = (initialCapacity + IntMask) / IntSize;
_masks = new List<int>(count);
while (count-- > 0)
{
_masks.Add(0);
}
}
public bool Set(int bit)
{
EnsureCapacity(bit + 1);
int wordIndex = bit / IntSize;
int wordBit = bit & IntMask;
int wordMask = 1 << wordBit;
if ((_masks[wordIndex] & wordMask) != 0)
{
return false;
}
_masks[wordIndex] |= wordMask;
return true;
}
public void Clear(int bit)
{
EnsureCapacity(bit + 1);
int wordIndex = bit / IntSize;
int wordBit = bit & IntMask;
int wordMask = 1 << wordBit;
_masks[wordIndex] &= ~wordMask;
}
public bool IsSet(int bit)
{
EnsureCapacity(bit + 1);
int wordIndex = bit / IntSize;
int wordBit = bit & IntMask;
return (_masks[wordIndex] & (1 << wordBit)) != 0;
}
public bool Set(BitMap map)
{
EnsureCapacity(map._masks.Count * IntSize);
bool modified = false;
for (int index = 0; index < _masks.Count; index++)
{
int newValue = _masks[index] | map._masks[index];
if (_masks[index] != newValue)
{
_masks[index] = newValue;
modified = true;
}
}
return modified;
}
public bool Clear(BitMap map)
{
EnsureCapacity(map._masks.Count * IntSize);
bool modified = false;
for (int index = 0; index < _masks.Count; index++)
{
int newValue = _masks[index] & ~map._masks[index];
if (_masks[index] != newValue)
{
_masks[index] = newValue;
modified = true;
}
}
return modified;
}
private void EnsureCapacity(int size)
{
while (_masks.Count * IntSize < size)
{
_masks.Add(0);
}
}
public IEnumerator<int> GetEnumerator()
{
for (int index = 0; index < _masks.Count; index++)
{
int mask = _masks[index];
while (mask != 0)
{
int bit = BitUtils.LowestBitSet(mask);
mask &= ~(1 << bit);
yield return index * IntSize + bit;
}
}
}
IEnumerator IEnumerable.GetEnumerator()
{
return GetEnumerator();
}
}
}

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using System.Runtime.CompilerServices;
namespace ARMeilleure.Common
{
static class BitUtils
{
private const int DeBrujinSequence = 0x77cb531;
private static int[] DeBrujinLbsLut;
static BitUtils()
{
DeBrujinLbsLut = new int[32];
for (int index = 0; index < DeBrujinLbsLut.Length; index++)
{
uint lutIndex = (uint)(DeBrujinSequence * (1 << index)) >> 27;
DeBrujinLbsLut[lutIndex] = index;
}
}
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static int LowestBitSet(int value)
{
if (value == 0)
{
return -1;
}
int lsb = value & -value;
return DeBrujinLbsLut[(uint)(DeBrujinSequence * lsb) >> 27];
}
public static int HighestBitSet(int value)
{
if (value == 0)
{
return -1;
}
for (int bit = 31; bit >= 0; bit--)
{
if (((value >> bit) & 1) != 0)
{
return bit;
}
}
return -1;
}
private static readonly sbyte[] HbsNibbleLut = { -1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 };
public static int HighestBitSetNibble(int value) => HbsNibbleLut[value & 0b1111];
public static long Replicate(long bits, int size)
{
long output = 0;
for (int bit = 0; bit < 64; bit += size)
{
output |= bits << bit;
}
return output;
}
public static int CountBits(int value)
{
int count = 0;
while (value != 0)
{
value &= ~(value & -value);
count++;
}
return count;
}
public static long FillWithOnes(int bits)
{
return bits == 64 ? -1L : (1L << bits) - 1;
}
public static int RotateRight(int bits, int shift, int size)
{
return (int)RotateRight((uint)bits, shift, size);
}
public static uint RotateRight(uint bits, int shift, int size)
{
return (bits >> shift) | (bits << (size - shift));
}
public static long RotateRight(long bits, int shift, int size)
{
return (long)RotateRight((ulong)bits, shift, size);
}
public static ulong RotateRight(ulong bits, int shift, int size)
{
return (bits >> shift) | (bits << (size - shift));
}
}
}

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using System;
namespace ARMeilleure.Common
{
static class EnumUtils
{
public static int GetCount(Type enumType)
{
return Enum.GetNames(enumType).Length;
}
}
}

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using System;
using System.Collections.Generic;
namespace ARMeilleure.Decoders
{
class Block
{
public ulong Address { get; set; }
public ulong EndAddress { get; set; }
public Block Next { get; set; }
public Block Branch { get; set; }
public List<OpCode> OpCodes { get; private set; }
public Block()
{
OpCodes = new List<OpCode>();
}
public Block(ulong address) : this()
{
Address = address;
}
public void Split(Block rightBlock)
{
int splitIndex = BinarySearch(OpCodes, rightBlock.Address);
if ((ulong)OpCodes[splitIndex].Address < rightBlock.Address)
{
splitIndex++;
}
int splitCount = OpCodes.Count - splitIndex;
if (splitCount <= 0)
{
throw new ArgumentException("Can't split at right block address.");
}
rightBlock.EndAddress = EndAddress;
rightBlock.Next = Next;
rightBlock.Branch = Branch;
rightBlock.OpCodes.AddRange(OpCodes.GetRange(splitIndex, splitCount));
EndAddress = rightBlock.Address;
Next = rightBlock;
Branch = null;
OpCodes.RemoveRange(splitIndex, splitCount);
}
private static int BinarySearch(List<OpCode> opCodes, ulong address)
{
int left = 0;
int middle = 0;
int right = opCodes.Count - 1;
while (left <= right)
{
int size = right - left;
middle = left + (size >> 1);
OpCode opCode = opCodes[middle];
if (address == (ulong)opCode.Address)
{
break;
}
if (address < (ulong)opCode.Address)
{
right = middle - 1;
}
else
{
left = middle + 1;
}
}
return middle;
}
public OpCode GetLastOp()
{
if (OpCodes.Count > 0)
{
return OpCodes[OpCodes.Count - 1];
}
return null;
}
}
}

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ARMeilleure/Decoders/Condition.cs Normal file
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namespace ARMeilleure.Decoders
{
enum Condition
{
Eq = 0,
Ne = 1,
GeUn = 2,
LtUn = 3,
Mi = 4,
Pl = 5,
Vs = 6,
Vc = 7,
GtUn = 8,
LeUn = 9,
Ge = 10,
Lt = 11,
Gt = 12,
Le = 13,
Al = 14,
Nv = 15
}
static class ConditionExtensions
{
public static Condition Invert(this Condition cond)
{
// Bit 0 of all conditions is basically a negation bit, so
// inverting this bit has the effect of inverting the condition.
return (Condition)((int)cond ^ 1);
}
}
}

10
ARMeilleure/Decoders/DataOp.cs Normal file
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namespace ARMeilleure.Decoders
{
enum DataOp
{
Adr = 0,
Arithmetic = 1,
Logical = 2,
BitField = 3
}
}

351
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using ARMeilleure.Instructions;
using ARMeilleure.Memory;
using ARMeilleure.State;
using System;
using System.Collections.Concurrent;
using System.Collections.Generic;
using System.Reflection.Emit;
namespace ARMeilleure.Decoders
{
static class Decoder
{
private delegate object MakeOp(InstDescriptor inst, ulong address, int opCode);
private static ConcurrentDictionary<Type, MakeOp> _opActivators;
static Decoder()
{
_opActivators = new ConcurrentDictionary<Type, MakeOp>();
}
public static Block[] DecodeBasicBlock(MemoryManager memory, ulong address, ExecutionMode mode)
{
Block block = new Block(address);
FillBlock(memory, mode, block, ulong.MaxValue);
return new Block[] { block };
}
public static Block[] DecodeFunction(MemoryManager memory, ulong address, ExecutionMode mode)
{
List<Block> blocks = new List<Block>();
Queue<Block> workQueue = new Queue<Block>();
Dictionary<ulong, Block> visited = new Dictionary<ulong, Block>();
Block GetBlock(ulong blkAddress)
{
if (!visited.TryGetValue(blkAddress, out Block block))
{
block = new Block(blkAddress);
workQueue.Enqueue(block);
visited.Add(blkAddress, block);
}
return block;
}
GetBlock(address);
while (workQueue.TryDequeue(out Block currBlock))
{
// Check if the current block is inside another block.
if (BinarySearch(blocks, currBlock.Address, out int nBlkIndex))
{
Block nBlock = blocks[nBlkIndex];
if (nBlock.Address == currBlock.Address)
{
throw new InvalidOperationException("Found duplicate block address on the list.");
}
nBlock.Split(currBlock);
blocks.Insert(nBlkIndex + 1, currBlock);
continue;
}
// If we have a block after the current one, set the limit address.
ulong limitAddress = ulong.MaxValue;
if (nBlkIndex != blocks.Count)
{
Block nBlock = blocks[nBlkIndex];
int nextIndex = nBlkIndex + 1;
if (nBlock.Address < currBlock.Address && nextIndex < blocks.Count)
{
limitAddress = blocks[nextIndex].Address;
}
else if (nBlock.Address > currBlock.Address)
{
limitAddress = blocks[nBlkIndex].Address;
}
}
FillBlock(memory, mode, currBlock, limitAddress);
if (currBlock.OpCodes.Count != 0)
{
// Set child blocks. "Branch" is the block the branch instruction
// points to (when taken), "Next" is the block at the next address,
// executed when the branch is not taken. For Unconditional Branches
// (except BL/BLR that are sub calls) or end of executable, Next is null.
OpCode lastOp = currBlock.GetLastOp();
bool isCall = IsCall(lastOp);
if (lastOp is IOpCodeBImm op && !isCall)
{
currBlock.Branch = GetBlock((ulong)op.Immediate);
}
if (!IsUnconditionalBranch(lastOp) /*|| isCall*/)
{
currBlock.Next = GetBlock(currBlock.EndAddress);
}
}
// Insert the new block on the list (sorted by address).
if (blocks.Count != 0)
{
Block nBlock = blocks[nBlkIndex];
blocks.Insert(nBlkIndex + (nBlock.Address < currBlock.Address ? 1 : 0), currBlock);
}
else
{
blocks.Add(currBlock);
}
}
return blocks.ToArray();
}
private static bool BinarySearch(List<Block> blocks, ulong address, out int index)
{
index = 0;
int left = 0;
int right = blocks.Count - 1;
while (left <= right)
{
int size = right - left;
int middle = left + (size >> 1);
Block block = blocks[middle];
index = middle;
if (address >= block.Address && address < block.EndAddress)
{
return true;
}
if (address < block.Address)
{
right = middle - 1;
}
else
{
left = middle + 1;
}
}
return false;
}
private static void FillBlock(
MemoryManager memory,
ExecutionMode mode,
Block block,
ulong limitAddress)
{
ulong address = block.Address;
OpCode opCode;
do
{
if (address >= limitAddress)
{
break;
}
opCode = DecodeOpCode(memory, address, mode);
block.OpCodes.Add(opCode);
address += (ulong)opCode.OpCodeSizeInBytes;
}
while (!(IsBranch(opCode) || IsException(opCode)));
block.EndAddress = address;
}
private static bool IsBranch(OpCode opCode)
{
return opCode is OpCodeBImm ||
opCode is OpCodeBReg || IsAarch32Branch(opCode);
}
private static bool IsUnconditionalBranch(OpCode opCode)
{
return opCode is OpCodeBImmAl ||
opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode);
}
private static bool IsAarch32UnconditionalBranch(OpCode opCode)
{
if (!(opCode is OpCode32 op))
{
return false;
}
// Note: On ARM32, most instructions have conditional execution,
// so there's no "Always" (unconditional) branch like on ARM64.
// We need to check if the condition is "Always" instead.
return IsAarch32Branch(op) && op.Cond >= Condition.Al;
}
private static bool IsAarch32Branch(OpCode opCode)
{
// Note: On ARM32, most ALU operations can write to R15 (PC),
// so we must consider such operations as a branch in potential aswell.
if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc)
{
return true;
}
// Same thing for memory operations. We have the cases where PC is a target
// register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
// a write back to PC (wback == true && Rn == 15), however the later may
// be "undefined" depending on the CPU, so compilers should not produce that.
if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult)
{
int rt, rn;
bool wBack, isLoad;
if (opCode is IOpCode32Mem opMem)
{
rt = opMem.Rt;
rn = opMem.Rn;
wBack = opMem.WBack;
isLoad = opMem.IsLoad;
// For the dual load, we also need to take into account the
// case were Rt2 == 15 (PC).
if (rt == 14 && opMem.Instruction.Name == InstName.Ldrd)
{
rt = RegisterAlias.Aarch32Pc;
}
}
else if (opCode is IOpCode32MemMult opMemMult)
{
const int pcMask = 1 << RegisterAlias.Aarch32Pc;
rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
rn = opMemMult.Rn;
wBack = opMemMult.PostOffset != 0;
isLoad = opMemMult.IsLoad;
}
else
{
throw new NotImplementedException($"The type \"{opCode.GetType().Name}\" is not implemented on the decoder.");
}
if ((rt == RegisterAlias.Aarch32Pc && isLoad) ||
(rn == RegisterAlias.Aarch32Pc && wBack))
{
return true;
}
}
// Explicit branch instructions.
return opCode is IOpCode32BImm ||
opCode is IOpCode32BReg;
}
private static bool IsCall(OpCode opCode)
{
// TODO (CQ): ARM32 support.
return opCode.Instruction.Name == InstName.Bl ||
opCode.Instruction.Name == InstName.Blr;
}
private static bool IsException(OpCode opCode)
{
return opCode.Instruction.Name == InstName.Brk ||
opCode.Instruction.Name == InstName.Svc ||
opCode.Instruction.Name == InstName.Und;
}
public static OpCode DecodeOpCode(MemoryManager memory, ulong address, ExecutionMode mode)
{
int opCode = memory.ReadInt32((long)address);
InstDescriptor inst;
Type type;
if (mode == ExecutionMode.Aarch64)
{
(inst, type) = OpCodeTable.GetInstA64(opCode);
}
else
{
if (mode == ExecutionMode.Aarch32Arm)
{
(inst, type) = OpCodeTable.GetInstA32(opCode);
}
else /* if (mode == ExecutionMode.Aarch32Thumb) */
{
(inst, type) = OpCodeTable.GetInstT32(opCode);
}
}
if (type != null)
{
return MakeOpCode(inst, type, address, opCode);
}
else
{
return new OpCode(inst, address, opCode);
}
}
private static OpCode MakeOpCode(InstDescriptor inst, Type type, ulong address, int opCode)
{
MakeOp createInstance = _opActivators.GetOrAdd(type, CacheOpActivator);
return (OpCode)createInstance(inst, address, opCode);
}
private static MakeOp CacheOpActivator(Type type)
{
Type[] argTypes = new Type[] { typeof(InstDescriptor), typeof(ulong), typeof(int) };
DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes);
ILGenerator generator = mthd.GetILGenerator();
generator.Emit(OpCodes.Ldarg_0);
generator.Emit(OpCodes.Ldarg_1);
generator.Emit(OpCodes.Ldarg_2);
generator.Emit(OpCodes.Newobj, type.GetConstructor(argTypes));
generator.Emit(OpCodes.Ret);
return (MakeOp)mthd.CreateDelegate(typeof(MakeOp));
}
}
}

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using ARMeilleure.Common;
using System;
namespace ARMeilleure.Decoders
{
static class DecoderHelper
{
public struct BitMask
{
public long WMask;
public long TMask;
public int Pos;
public int Shift;
public bool IsUndefined;
public static BitMask Invalid => new BitMask { IsUndefined = true };
}
public static BitMask DecodeBitMask(int opCode, bool immediate)
{
int immS = (opCode >> 10) & 0x3f;
int immR = (opCode >> 16) & 0x3f;
int n = (opCode >> 22) & 1;
int sf = (opCode >> 31) & 1;
int length = BitUtils.HighestBitSet((~immS & 0x3f) | (n << 6));
if (length < 1 || (sf == 0 && n != 0))
{
return BitMask.Invalid;
}
int size = 1 << length;
int levels = size - 1;
int s = immS & levels;
int r = immR & levels;
if (immediate && s == levels)
{
return BitMask.Invalid;
}
long wMask = BitUtils.FillWithOnes(s + 1);
long tMask = BitUtils.FillWithOnes(((s - r) & levels) + 1);
if (r > 0)
{
wMask = BitUtils.RotateRight(wMask, r, size);
wMask &= BitUtils.FillWithOnes(size);
}
return new BitMask()
{
WMask = BitUtils.Replicate(wMask, size),
TMask = BitUtils.Replicate(tMask, size),
Pos = immS,
Shift = immR
};
}
public static long DecodeImm8Float(long imm, int size)
{
int e = 0, f = 0;
switch (size)
{
case 0: e = 8; f = 23; break;
case 1: e = 11; f = 52; break;
default: throw new ArgumentOutOfRangeException(nameof(size));
}
long value = (imm & 0x3f) << f - 4;
long eBit = (imm >> 6) & 1;
long sBit = (imm >> 7) & 1;
if (eBit != 0)
{
value |= (1L << e - 3) - 1 << f + 2;
}
value |= (eBit ^ 1) << f + e - 1;
value |= sBit << f + e;
return value;
}
public static long DecodeImm24_2(int opCode)
{
return ((long)opCode << 40) >> 38;
}
public static long DecodeImm26_2(int opCode)
{
return ((long)opCode << 38) >> 36;
}
public static long DecodeImmS19_2(int opCode)
{
return (((long)opCode << 40) >> 43) & ~3;
}
public static long DecodeImmS14_2(int opCode)
{
return (((long)opCode << 45) >> 48) & ~3;
}
}
}

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ARMeilleure/Decoders/IOpCode.cs Normal file
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using ARMeilleure.IntermediateRepresentation;
namespace ARMeilleure.Decoders
{
interface IOpCode
{
ulong Address { get; }
InstDescriptor Instruction { get; }
RegisterSize RegisterSize { get; }
int GetBitsCount();
OperandType GetOperandType();
}
}

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ARMeilleure/Decoders/IOpCode32.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCode32 : IOpCode
{
Condition Cond { get; }
uint GetPc();
}
}

10
ARMeilleure/Decoders/IOpCode32Alu.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCode32Alu : IOpCode32
{
int Rd { get; }
int Rn { get; }
bool SetFlags { get; }
}
}

4
ARMeilleure/Decoders/IOpCode32BImm.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCode32BImm : IOpCode32, IOpCodeBImm { }
}

7
ARMeilleure/Decoders/IOpCode32BReg.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCode32BReg : IOpCode32
{
int Rm { get; }
}
}

12
ARMeilleure/Decoders/IOpCode32Mem.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCode32Mem : IOpCode32
{
int Rt { get; }
int Rn { get; }
bool WBack { get; }
bool IsLoad { get; }
}
}

13
ARMeilleure/Decoders/IOpCode32MemMult.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCode32MemMult : IOpCode32
{
int Rn { get; }
int RegisterMask { get; }
int PostOffset { get; }
bool IsLoad { get; }
}
}

10
ARMeilleure/Decoders/IOpCodeAlu.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCodeAlu : IOpCode
{
int Rd { get; }
int Rn { get; }
DataOp DataOp { get; }
}
}

7
ARMeilleure/Decoders/IOpCodeAluImm.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCodeAluImm : IOpCodeAlu
{
long Immediate { get; }
}
}

10
ARMeilleure/Decoders/IOpCodeAluRs.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCodeAluRs : IOpCodeAlu
{
int Shift { get; }
int Rm { get; }
ShiftType ShiftType { get; }
}
}

10
ARMeilleure/Decoders/IOpCodeAluRx.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCodeAluRx : IOpCodeAlu
{
int Shift { get; }
int Rm { get; }
IntType IntType { get; }
}
}

7
ARMeilleure/Decoders/IOpCodeBImm.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCodeBImm : IOpCode
{
long Immediate { get; }
}
}

7
ARMeilleure/Decoders/IOpCodeCond.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCodeCond : IOpCode
{
Condition Cond { get; }
}
}

11
ARMeilleure/Decoders/IOpCodeLit.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCodeLit : IOpCode
{
int Rt { get; }
long Immediate { get; }
int Size { get; }
bool Signed { get; }
bool Prefetch { get; }
}
}

7
ARMeilleure/Decoders/IOpCodeSimd.cs Normal file
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namespace ARMeilleure.Decoders
{
interface IOpCodeSimd : IOpCode
{
int Size { get; }
}
}

18
ARMeilleure/Decoders/InstDescriptor.cs Normal file
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using ARMeilleure.Instructions;
namespace ARMeilleure.Decoders
{
struct InstDescriptor
{
public static InstDescriptor Undefined => new InstDescriptor(InstName.Und, null);
public InstName Name { get; }
public InstEmitter Emitter { get; }
public InstDescriptor(InstName name, InstEmitter emitter)
{
Name = name;
Emitter = emitter;
}
}
}

6
ARMeilleure/Decoders/InstEmitter.cs Normal file
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using ARMeilleure.Translation;
namespace ARMeilleure.Decoders
{
delegate void InstEmitter(ArmEmitterContext context);
}

14
ARMeilleure/Decoders/IntType.cs Normal file
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namespace ARMeilleure.Decoders
{
enum IntType
{
UInt8 = 0,
UInt16 = 1,
UInt32 = 2,
UInt64 = 3,
Int8 = 4,
Int16 = 5,
Int32 = 6,
Int64 = 7
}
}

48
ARMeilleure/Decoders/OpCode.cs Normal file
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using ARMeilleure.IntermediateRepresentation;
using System;
namespace ARMeilleure.Decoders
{
class OpCode : IOpCode
{
public ulong Address { get; private set; }
public int RawOpCode { get; private set; }
public int OpCodeSizeInBytes { get; protected set; } = 4;
public InstDescriptor Instruction { get; protected set; }
public RegisterSize RegisterSize { get; protected set; }
public OpCode(InstDescriptor inst, ulong address, int opCode)
{
Address = address;
RawOpCode = opCode;
Instruction = inst;
RegisterSize = RegisterSize.Int64;
}
public int GetPairsCount() => GetBitsCount() / 16;
public int GetBytesCount() => GetBitsCount() / 8;
public int GetBitsCount()
{
switch (RegisterSize)
{
case RegisterSize.Int32: return 32;
case RegisterSize.Int64: return 64;
case RegisterSize.Simd64: return 64;
case RegisterSize.Simd128: return 128;
}
throw new InvalidOperationException();
}
public OperandType GetOperandType()
{
return RegisterSize == RegisterSize.Int32 ? OperandType.I32 : OperandType.I64;
}
}
}

21
ARMeilleure/Decoders/OpCode32.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCode32 : OpCode
{
public Condition Cond { get; protected set; }
public OpCode32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
RegisterSize = RegisterSize.Int32;
Cond = (Condition)((uint)opCode >> 28);
}
public uint GetPc()
{
// Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline,
// the PC actually points 2 instructions ahead.
return (uint)Address + (uint)OpCodeSizeInBytes * 2;
}
}
}

18
ARMeilleure/Decoders/OpCode32Alu.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCode32Alu : OpCode32, IOpCode32Alu
{
public int Rd { get; private set; }
public int Rn { get; private set; }
public bool SetFlags { get; private set; }
public OpCode32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = (opCode >> 12) & 0xf;
Rn = (opCode >> 16) & 0xf;
SetFlags = ((opCode >> 20) & 1) != 0;
}
}
}

21
ARMeilleure/Decoders/OpCode32AluImm.cs Normal file
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using ARMeilleure.Common;
namespace ARMeilleure.Decoders
{
class OpCode32AluImm : OpCode32Alu
{
public int Immediate { get; private set; }
public bool IsRotated { get; private set; }
public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int value = (opCode >> 0) & 0xff;
int shift = (opCode >> 8) & 0xf;
Immediate = BitUtils.RotateRight(value, shift * 2, 32);
IsRotated = shift != 0;
}
}
}

18
ARMeilleure/Decoders/OpCode32AluRsImm.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCode32AluRsImm : OpCode32Alu
{
public int Rm { get; private set; }
public int Imm { get; private set; }
public ShiftType ShiftType { get; private set; }
public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = (opCode >> 0) & 0xf;
Imm = (opCode >> 7) & 0x1f;
ShiftType = (ShiftType)((opCode >> 5) & 3);
}
}
}

27
ARMeilleure/Decoders/OpCode32BImm.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCode32BImm : OpCode32, IOpCode32BImm
{
public long Immediate { get; private set; }
public OpCode32BImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
uint pc = GetPc();
// When the condition is never, the instruction is BLX to Thumb mode.
if (Cond != Condition.Nv)
{
pc &= ~3u;
}
Immediate = pc + DecoderHelper.DecodeImm24_2(opCode);
if (Cond == Condition.Nv)
{
long H = (opCode >> 23) & 2;
Immediate |= H;
}
}
}
}

12
ARMeilleure/Decoders/OpCode32BReg.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCode32BReg : OpCode32, IOpCode32BReg
{
public int Rm { get; private set; }
public OpCode32BReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = opCode & 0xf;
}
}
}

37
ARMeilleure/Decoders/OpCode32Mem.cs Normal file
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using ARMeilleure.Instructions;
namespace ARMeilleure.Decoders
{
class OpCode32Mem : OpCode32, IOpCode32Mem
{
public int Rt { get; private set; }
public int Rn { get; private set; }
public int Immediate { get; protected set; }
public bool Index { get; private set; }
public bool Add { get; private set; }
public bool WBack { get; private set; }
public bool Unprivileged { get; private set; }
public bool IsLoad { get; private set; }
public OpCode32Mem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = (opCode >> 12) & 0xf;
Rn = (opCode >> 16) & 0xf;
bool isLoad = (opCode & (1 << 20)) != 0;
bool w = (opCode & (1 << 21)) != 0;
bool u = (opCode & (1 << 23)) != 0;
bool p = (opCode & (1 << 24)) != 0;
Index = p;
Add = u;
WBack = !p || w;
Unprivileged = !p && w;
IsLoad = isLoad || inst.Name == InstName.Ldrd;
}
}
}

10
ARMeilleure/Decoders/OpCode32MemImm.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCode32MemImm : OpCode32Mem
{
public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Immediate = opCode & 0xfff;
}
}
}

13
ARMeilleure/Decoders/OpCode32MemImm8.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCode32MemImm8 : OpCode32Mem
{
public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int imm4L = (opCode >> 0) & 0xf;
int imm4H = (opCode >> 8) & 0xf;
Immediate = imm4L | (imm4H << 4);
}
}
}

55
ARMeilleure/Decoders/OpCode32MemMult.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCode32MemMult : OpCode32, IOpCode32MemMult
{
public int Rn { get; private set; }
public int RegisterMask { get; private set; }
public int Offset { get; private set; }
public int PostOffset { get; private set; }
public bool IsLoad { get; private set; }
public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rn = (opCode >> 16) & 0xf;
bool isLoad = (opCode & (1 << 20)) != 0;
bool w = (opCode & (1 << 21)) != 0;
bool u = (opCode & (1 << 23)) != 0;
bool p = (opCode & (1 << 24)) != 0;
RegisterMask = opCode & 0xffff;
int regsSize = 0;
for (int index = 0; index < 16; index++)
{
regsSize += (RegisterMask >> index) & 1;
}
regsSize *= 4;
if (!u)
{
Offset -= regsSize;
}
if (u == p)
{
Offset += 4;
}
if (w)
{
PostOffset = u ? regsSize : -regsSize;
}
else
{
PostOffset = 0;
}
IsLoad = isLoad;
}
}
}

17
ARMeilleure/Decoders/OpCodeAdr.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeAdr : OpCode
{
public int Rd { get; private set; }
public long Immediate { get; private set; }
public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = opCode & 0x1f;
Immediate = DecoderHelper.DecodeImmS19_2(opCode);
Immediate |= ((long)opCode >> 29) & 3;
}
}
}

21
ARMeilleure/Decoders/OpCodeAlu.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeAlu : OpCode, IOpCodeAlu
{
public int Rd { get; protected set; }
public int Rn { get; private set; }
public DataOp DataOp { get; private set; }
public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f;
DataOp = (DataOp)((opCode >> 24) & 0x3);
RegisterSize = (opCode >> 31) != 0
? RegisterSize.Int64
: RegisterSize.Int32;
}
}
}

12
ARMeilleure/Decoders/OpCodeAluBinary.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeAluBinary : OpCodeAlu
{
public int Rm { get; private set; }
public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = (opCode >> 16) & 0x1f;
}
}
}

38
ARMeilleure/Decoders/OpCodeAluImm.cs Normal file
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using System;
namespace ARMeilleure.Decoders
{
class OpCodeAluImm : OpCodeAlu, IOpCodeAluImm
{
public long Immediate { get; private set; }
public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
if (DataOp == DataOp.Arithmetic)
{
Immediate = (opCode >> 10) & 0xfff;
int shift = (opCode >> 22) & 3;
Immediate <<= shift * 12;
}
else if (DataOp == DataOp.Logical)
{
var bm = DecoderHelper.DecodeBitMask(opCode, true);
if (bm.IsUndefined)
{
Instruction = InstDescriptor.Undefined;
return;
}
Immediate = bm.WMask;
}
else
{
throw new ArgumentException(nameof(opCode));
}
}
}
}

27
ARMeilleure/Decoders/OpCodeAluRs.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs
{
public int Shift { get; private set; }
public int Rm { get; private set; }
public ShiftType ShiftType { get; private set; }
public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int shift = (opCode >> 10) & 0x3f;
if (shift >= GetBitsCount())
{
Instruction = InstDescriptor.Undefined;
return;
}
Shift = shift;
Rm = (opCode >> 16) & 0x1f;
ShiftType = (ShiftType)((opCode >> 22) & 0x3);
}
}
}

17
ARMeilleure/Decoders/OpCodeAluRx.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx
{
public int Shift { get; private set; }
public int Rm { get; private set; }
public IntType IntType { get; private set; }
public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Shift = (opCode >> 10) & 0x7;
IntType = (IntType)((opCode >> 13) & 0x7);
Rm = (opCode >> 16) & 0x1f;
}
}
}

9
ARMeilleure/Decoders/OpCodeBImm.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeBImm : OpCode, IOpCodeBImm
{
public long Immediate { get; protected set; }
public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
}

10
ARMeilleure/Decoders/OpCodeBImmAl.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeBImmAl : OpCodeBImm
{
public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode);
}
}
}

18
ARMeilleure/Decoders/OpCodeBImmCmp.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeBImmCmp : OpCodeBImm
{
public int Rt { get; private set; }
public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = opCode & 0x1f;
Immediate = (long)address + DecoderHelper.DecodeImmS19_2(opCode);
RegisterSize = (opCode >> 31) != 0
? RegisterSize.Int64
: RegisterSize.Int32;
}
}
}

23
ARMeilleure/Decoders/OpCodeBImmCond.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeBImmCond : OpCodeBImm, IOpCodeCond
{
public Condition Cond { get; private set; }
public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int o0 = (opCode >> 4) & 1;
if (o0 != 0)
{
Instruction = InstDescriptor.Undefined;
return;
}
Cond = (Condition)(opCode & 0xf);
Immediate = (long)address + DecoderHelper.DecodeImmS19_2(opCode);
}
}
}

18
ARMeilleure/Decoders/OpCodeBImmTest.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeBImmTest : OpCodeBImm
{
public int Rt { get; private set; }
public int Bit { get; private set; }
public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = opCode & 0x1f;
Immediate = (long)address + DecoderHelper.DecodeImmS14_2(opCode);
Bit = (opCode >> 19) & 0x1f;
Bit |= (opCode >> 26) & 0x20;
}
}
}

22
ARMeilleure/Decoders/OpCodeBReg.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeBReg : OpCode
{
public int Rn { get; private set; }
public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int op4 = (opCode >> 0) & 0x1f;
int op2 = (opCode >> 16) & 0x1f;
if (op2 != 0b11111 || op4 != 0b00000)
{
Instruction = InstDescriptor.Undefined;
return;
}
Rn = (opCode >> 5) & 0x1f;
}
}
}

27
ARMeilleure/Decoders/OpCodeBfm.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeBfm : OpCodeAlu
{
public long WMask { get; private set; }
public long TMask { get; private set; }
public int Pos { get; private set; }
public int Shift { get; private set; }
public OpCodeBfm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
var bm = DecoderHelper.DecodeBitMask(opCode, false);
if (bm.IsUndefined)
{
Instruction = InstDescriptor.Undefined;
return;
}
WMask = bm.WMask;
TMask = bm.TMask;
Pos = bm.Pos;
Shift = bm.Shift;
}
}
}

30
ARMeilleure/Decoders/OpCodeCcmp.cs Normal file
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using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
class OpCodeCcmp : OpCodeAlu, IOpCodeCond
{
public int Nzcv { get; private set; }
protected int RmImm;
public Condition Cond { get; private set; }
public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int o3 = (opCode >> 4) & 1;
if (o3 != 0)
{
Instruction = InstDescriptor.Undefined;
return;
}
Nzcv = (opCode >> 0) & 0xf;
Cond = (Condition)((opCode >> 12) & 0xf);
RmImm = (opCode >> 16) & 0x1f;
Rd = RegisterAlias.Zr;
}
}
}

9
ARMeilleure/Decoders/OpCodeCcmpImm.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeCcmpImm : OpCodeCcmp, IOpCodeAluImm
{
public long Immediate => RmImm;
public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
}

13
ARMeilleure/Decoders/OpCodeCcmpReg.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeCcmpReg : OpCodeCcmp, IOpCodeAluRs
{
public int Rm => RmImm;
public int Shift => 0;
public ShiftType ShiftType => ShiftType.Lsl;
public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
}

15
ARMeilleure/Decoders/OpCodeCsel.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeCsel : OpCodeAlu, IOpCodeCond
{
public int Rm { get; private set; }
public Condition Cond { get; private set; }
public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = (opCode >> 16) & 0x1f;
Cond = (Condition)((opCode >> 12) & 0xf);
}
}
}

12
ARMeilleure/Decoders/OpCodeException.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeException : OpCode
{
public int Id { get; private set; }
public OpCodeException(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Id = (opCode >> 5) & 0xffff;
}
}
}

17
ARMeilleure/Decoders/OpCodeMem.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeMem : OpCode
{
public int Rt { get; protected set; }
public int Rn { get; protected set; }
public int Size { get; protected set; }
public bool Extend64 { get; protected set; }
public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f;
Size = (opCode >> 30) & 0x3;
}
}
}

14
ARMeilleure/Decoders/OpCodeMemEx.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeMemEx : OpCodeMem
{
public int Rt2 { get; private set; }
public int Rs { get; private set; }
public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt2 = (opCode >> 10) & 0x1f;
Rs = (opCode >> 16) & 0x1f;
}
}
}

51
ARMeilleure/Decoders/OpCodeMemImm.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeMemImm : OpCodeMem
{
public long Immediate { get; protected set; }
public bool WBack { get; protected set; }
public bool PostIdx { get; protected set; }
protected bool Unscaled { get; private set; }
private enum MemOp
{
Unscaled = 0,
PostIndexed = 1,
Unprivileged = 2,
PreIndexed = 3,
Unsigned
}
public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Extend64 = ((opCode >> 22) & 3) == 2;
WBack = ((opCode >> 24) & 1) == 0;
// The type is not valid for the Unsigned Immediate 12-bits encoding,
// because the bits 11:10 are used for the larger Immediate offset.
MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned;
PostIdx = type == MemOp.PostIndexed;
Unscaled = type == MemOp.Unscaled ||
type == MemOp.Unprivileged;
// Unscaled and Unprivileged doesn't write back,
// but they do use the 9-bits Signed Immediate.
if (Unscaled)
{
WBack = false;
}
if (WBack || Unscaled)
{
// 9-bits Signed Immediate.
Immediate = (opCode << 11) >> 23;
}
else
{
// 12-bits Unsigned Immediate.
Immediate = ((opCode >> 10) & 0xfff) << Size;
}
}
}
}

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ARMeilleure/Decoders/OpCodeMemLit.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeMemLit : OpCode, IOpCodeLit
{
public int Rt { get; private set; }
public long Immediate { get; private set; }
public int Size { get; private set; }
public bool Signed { get; private set; }
public bool Prefetch { get; private set; }
public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = opCode & 0x1f;
Immediate = (long)address + DecoderHelper.DecodeImmS19_2(opCode);
switch ((opCode >> 30) & 3)
{
case 0: Size = 2; Signed = false; Prefetch = false; break;
case 1: Size = 3; Signed = false; Prefetch = false; break;
case 2: Size = 2; Signed = true; Prefetch = false; break;
case 3: Size = 0; Signed = false; Prefetch = true; break;
}
}
}
}

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ARMeilleure/Decoders/OpCodeMemPair.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeMemPair : OpCodeMemImm
{
public int Rt2 { get; private set; }
public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt2 = (opCode >> 10) & 0x1f;
WBack = ((opCode >> 23) & 0x1) != 0;
PostIdx = ((opCode >> 23) & 0x3) == 1;
Extend64 = ((opCode >> 30) & 0x3) == 1;
Size = ((opCode >> 31) & 0x1) | 2;
DecodeImm(opCode);
}
protected void DecodeImm(int opCode)
{
Immediate = ((long)(opCode >> 15) << 57) >> (57 - Size);
}
}
}

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ARMeilleure/Decoders/OpCodeMemReg.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeMemReg : OpCodeMem
{
public bool Shift { get; private set; }
public int Rm { get; private set; }
public IntType IntType { get; private set; }
public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Shift = ((opCode >> 12) & 0x1) != 0;
IntType = (IntType)((opCode >> 13) & 0x7);
Rm = (opCode >> 16) & 0x1f;
Extend64 = ((opCode >> 22) & 0x3) == 2;
}
}
}

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ARMeilleure/Decoders/OpCodeMov.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeMov : OpCode
{
public int Rd { get; private set; }
public long Immediate { get; private set; }
public int Bit { get; private set; }
public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int p1 = (opCode >> 22) & 1;
int sf = (opCode >> 31) & 1;
if (sf == 0 && p1 != 0)
{
Instruction = InstDescriptor.Undefined;
return;
}
Rd = (opCode >> 0) & 0x1f;
Immediate = (opCode >> 5) & 0xffff;
Bit = (opCode >> 21) & 0x3;
Bit <<= 4;
Immediate <<= Bit;
RegisterSize = (opCode >> 31) != 0
? RegisterSize.Int64
: RegisterSize.Int32;
}
}
}

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ARMeilleure/Decoders/OpCodeMul.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeMul : OpCodeAlu
{
public int Rm { get; private set; }
public int Ra { get; private set; }
public OpCodeMul(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Ra = (opCode >> 10) & 0x1f;
Rm = (opCode >> 16) & 0x1f;
}
}
}

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ARMeilleure/Decoders/OpCodeSimd.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeSimd : OpCode, IOpCodeSimd
{
public int Rd { get; private set; }
public int Rn { get; private set; }
public int Opc { get; private set; }
public int Size { get; protected set; }
public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f;
Opc = (opCode >> 15) & 0x3;
Size = (opCode >> 22) & 0x3;
RegisterSize = ((opCode >> 30) & 1) != 0
? RegisterSize.Simd128
: RegisterSize.Simd64;
}
}
}

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ARMeilleure/Decoders/OpCodeSimdCvt.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeSimdCvt : OpCodeSimd
{
public int FBits { get; private set; }
public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int scale = (opCode >> 10) & 0x3f;
int sf = (opCode >> 31) & 0x1;
FBits = 64 - scale;
RegisterSize = sf != 0
? RegisterSize.Int64
: RegisterSize.Int32;
}
}
}

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ARMeilleure/Decoders/OpCodeSimdExt.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeSimdExt : OpCodeSimdReg
{
public int Imm4 { get; private set; }
public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Imm4 = (opCode >> 11) & 0xf;
}
}
}

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ARMeilleure/Decoders/OpCodeSimdFcond.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeSimdFcond : OpCodeSimdReg, IOpCodeCond
{
public int Nzcv { get; private set; }
public Condition Cond { get; private set; }
public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Nzcv = (opCode >> 0) & 0xf;
Cond = (Condition)((opCode >> 12) & 0xf);
}
}
}

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ARMeilleure/Decoders/OpCodeSimdFmov.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeSimdFmov : OpCode, IOpCodeSimd
{
public int Rd { get; private set; }
public long Immediate { get; private set; }
public int Size { get; private set; }
public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int imm5 = (opCode >> 5) & 0x1f;
int type = (opCode >> 22) & 0x3;
if (imm5 != 0b00000 || type > 1)
{
Instruction = InstDescriptor.Undefined;
return;
}
Size = type;
long imm;
Rd = (opCode >> 0) & 0x1f;
imm = (opCode >> 13) & 0xff;
Immediate = DecoderHelper.DecodeImm8Float(imm, type);
}
}
}

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ARMeilleure/Decoders/OpCodeSimdImm.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeSimdImm : OpCode, IOpCodeSimd
{
public int Rd { get; private set; }
public long Immediate { get; private set; }
public int Size { get; private set; }
public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = opCode & 0x1f;
int cMode = (opCode >> 12) & 0xf;
int op = (opCode >> 29) & 0x1;
int modeLow = cMode & 1;
int modeHigh = cMode >> 1;
long imm;
imm = ((uint)opCode >> 5) & 0x1f;
imm |= ((uint)opCode >> 11) & 0xe0;
if (modeHigh == 0b111)
{
Size = modeLow != 0 ? op : 3;
switch (op | (modeLow << 1))
{
case 0:
// 64-bits Immediate.
// Transform abcd efgh into abcd efgh abcd efgh ...
imm = (long)((ulong)imm * 0x0101010101010101);
break;
case 1:
// 64-bits Immediate.
// Transform abcd efgh into aaaa aaaa bbbb bbbb ...
imm = (imm & 0xf0) >> 4 | (imm & 0x0f) << 4;
imm = (imm & 0xcc) >> 2 | (imm & 0x33) << 2;
imm = (imm & 0xaa) >> 1 | (imm & 0x55) << 1;
imm = (long)((ulong)imm * 0x8040201008040201);
imm = (long)((ulong)imm & 0x8080808080808080);
imm |= imm >> 4;
imm |= imm >> 2;
imm |= imm >> 1;
break;
case 2:
case 3:
// Floating point Immediate.
imm = DecoderHelper.DecodeImm8Float(imm, Size);
break;
}
}
else if ((modeHigh & 0b110) == 0b100)
{
// 16-bits shifted Immediate.
Size = 1; imm <<= (modeHigh & 1) << 3;
}
else if ((modeHigh & 0b100) == 0b000)
{
// 32-bits shifted Immediate.
Size = 2; imm <<= modeHigh << 3;
}
else if ((modeHigh & 0b111) == 0b110)
{
// 32-bits shifted Immediate (fill with ones).
Size = 2; imm = ShlOnes(imm, 8 << modeLow);
}
else
{
// 8 bits without shift.
Size = 0;
}
Immediate = imm;
RegisterSize = ((opCode >> 30) & 1) != 0
? RegisterSize.Simd128
: RegisterSize.Simd64;
}
private static long ShlOnes(long value, int shift)
{
if (shift != 0)
{
return value << shift | (long)(ulong.MaxValue >> (64 - shift));
}
else
{
return value;
}
}
}
}

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ARMeilleure/Decoders/OpCodeSimdIns.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeSimdIns : OpCodeSimd
{
public int SrcIndex { get; private set; }
public int DstIndex { get; private set; }
public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int imm4 = (opCode >> 11) & 0xf;
int imm5 = (opCode >> 16) & 0x1f;
if (imm5 == 0b10000)
{
Instruction = InstDescriptor.Undefined;
return;
}
Size = imm5 & -imm5;
switch (Size)
{
case 1: Size = 0; break;
case 2: Size = 1; break;
case 4: Size = 2; break;
case 8: Size = 3; break;
}
SrcIndex = imm4 >> Size;
DstIndex = imm5 >> (Size + 1);
}
}
}

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ARMeilleure/Decoders/OpCodeSimdMemImm.cs Normal file
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namespace ARMeilleure.Decoders
{
class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd
{
public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Size |= (opCode >> 21) & 4;
if (!WBack && !Unscaled && Size >= 4)
{
Immediate <<= 4;
}
Extend64 = false;
}
}
}

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