diff --git a/ChocolArm64/Instruction/AInstEmitSimdCmp.cs b/ChocolArm64/Instruction/AInstEmitSimdCmp.cs
index 583ad702..8a8376b2 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdCmp.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdCmp.cs
@@ -14,7 +14,7 @@ namespace ChocolArm64.Instruction
     {
         public static void Cmeq_V(AILEmitterCtx Context)
         {
-            if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg)
+            if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg Op && Op.Size < 3)
             {
                 EmitSse2Call(Context, nameof(Sse2.CompareEqual));
             }
@@ -26,19 +26,12 @@ namespace ChocolArm64.Instruction
 
         public static void Cmge_V(AILEmitterCtx Context)
         {
-            if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg)
-            {
-                EmitSse2Call(Context, nameof(Sse2.CompareGreaterThanOrEqual));
-            }
-            else
-            {
-                EmitVectorCmp(Context, OpCodes.Bge_S);
-            }
+            EmitVectorCmp(Context, OpCodes.Bge_S);
         }
 
         public static void Cmgt_V(AILEmitterCtx Context)
         {
-            if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg)
+            if (AOptimizations.UseSse2 && Context.CurrOp is AOpCodeSimdReg Op && Op.Size < 3)
             {
                 EmitSse2Call(Context, nameof(Sse2.CompareGreaterThan));
             }
diff --git a/Ryujinx.Core/Gpu/NvGpuVmm.cs b/Ryujinx.Core/Gpu/NvGpuVmm.cs
index ddd21238..1c408964 100644
--- a/Ryujinx.Core/Gpu/NvGpuVmm.cs
+++ b/Ryujinx.Core/Gpu/NvGpuVmm.cs
@@ -1,7 +1,6 @@
 using ChocolArm64.Memory;
-using System.Collections.Concurrent;
-
 using Ryujinx.Graphics.Gal;
+using System.Collections.Concurrent;
 
 namespace Ryujinx.Core.Gpu
 {