From ff53dcf5607a82ad38388502b4cf5cc8cca77733 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Mon, 26 Jun 2023 07:25:06 +0200 Subject: [PATCH] [ARMeilleure] Address dotnet-format issues (#5357) * dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Silence dotnet format IDE0060 warnings * Silence dotnet format IDE0052 warnings * Address or silence dotnet format IDE1006 warnings * Address or silence dotnet format CA2208 warnings * Address dotnet format CA1822 warnings * Address or silence dotnet format CA1069 warnings * Silence CA1806 and CA1834 issues * Address dotnet format CA1401 warnings * Fix new dotnet-format issues after rebase * Address review comments * Address dotnet format CA2208 warnings properly * Fix formatting for switch expressions * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Add previously silenced warnings back I have no clue how these disappeared * Revert formatting changes for OpCodeTable.cs * Enable formatting for a few cases again * Format if-blocks correctly * Enable formatting for a few more cases again * Fix inline comment alignment * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Disable 'prefer switch expression' rule * Add comments to disabled warnings * Remove a few unused parameters * Adjust namespaces * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Start working on disabled warnings * Fix and silence a few dotnet-format warnings again * Address IDE0251 warnings * Address a few disabled IDE0060 warnings * Silence IDE0060 in .editorconfig * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * First dotnet format pass * Remove unnecessary formatting exclusion * Add unsafe dotnet format changes * Change visibility of JitSupportDarwin to internal --- src/ARMeilleure/Allocators.cs | 5 +- .../CodeGen/Arm64/Arm64Optimizer.cs | 2 +- src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs | 28 +- .../CodeGen/Arm64/ArmExtensionType.cs | 2 +- src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs | 4 +- src/ARMeilleure/CodeGen/Arm64/Assembler.cs | 8 +- .../CodeGen/Arm64/CallingConvention.cs | 2 +- .../CodeGen/Arm64/CodeGenCommon.cs | 2 +- .../CodeGen/Arm64/CodeGenContext.cs | 14 +- .../CodeGen/Arm64/CodeGenerator.cs | 119 ++-- .../CodeGen/Arm64/CodeGeneratorIntrinsic.cs | 2 +- .../CodeGen/Arm64/HardwareCapabilities.cs | 169 +++-- .../CodeGen/Arm64/IntrinsicInfo.cs | 6 +- .../CodeGen/Arm64/IntrinsicTable.cs | 6 +- .../CodeGen/Arm64/IntrinsicType.cs | 4 +- src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs | 34 +- src/ARMeilleure/CodeGen/CompiledFunction.cs | 6 +- src/ARMeilleure/CodeGen/Linking/RelocEntry.cs | 2 +- src/ARMeilleure/CodeGen/Linking/RelocInfo.cs | 2 +- src/ARMeilleure/CodeGen/Linking/SymbolType.cs | 2 +- .../CodeGen/Optimizations/ConstantFolding.cs | 4 +- .../CodeGen/Optimizations/Optimizer.cs | 4 +- .../CodeGen/Optimizations/Simplification.cs | 13 +- .../RegisterAllocators/AllocationResult.cs | 6 +- .../RegisterAllocators/CopyResolver.cs | 42 +- .../RegisterAllocators/HybridAllocator.cs | 18 +- .../RegisterAllocators/IRegisterAllocator.cs | 2 +- .../RegisterAllocators/LinearScanAllocator.cs | 57 +- .../RegisterAllocators/LiveInterval.cs | 8 +- .../RegisterAllocators/LiveIntervalList.cs | 6 +- .../CodeGen/RegisterAllocators/LiveRange.cs | 2 +- .../RegisterAllocators/RegisterMasks.cs | 12 +- .../RegisterAllocators/StackAllocator.cs | 2 +- .../CodeGen/RegisterAllocators/UseList.cs | 36 +- .../CodeGen/Unwinding/UnwindInfo.cs | 2 +- .../CodeGen/Unwinding/UnwindPseudoOp.cs | 10 +- .../CodeGen/Unwinding/UnwindPushEntry.cs | 2 +- src/ARMeilleure/CodeGen/X86/Assembler.cs | 67 +- src/ARMeilleure/CodeGen/X86/AssemblerTable.cs | 52 +- src/ARMeilleure/CodeGen/X86/CallConvName.cs | 4 +- .../CodeGen/X86/CallingConvention.cs | 34 +- src/ARMeilleure/CodeGen/X86/CodeGenContext.cs | 4 +- src/ARMeilleure/CodeGen/X86/CodeGenerator.cs | 618 +++++++++--------- .../CodeGen/X86/HardwareCapabilities.cs | 12 +- src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs | 4 +- src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs | 6 +- src/ARMeilleure/CodeGen/X86/IntrinsicType.cs | 4 +- src/ARMeilleure/CodeGen/X86/Mxcsr.cs | 2 +- src/ARMeilleure/CodeGen/X86/PreAllocator.cs | 296 ++++----- .../CodeGen/X86/PreAllocatorSystemV.cs | 25 +- .../CodeGen/X86/PreAllocatorWindows.cs | 4 +- src/ARMeilleure/CodeGen/X86/X86Condition.cs | 36 +- src/ARMeilleure/CodeGen/X86/X86Instruction.cs | 4 +- src/ARMeilleure/CodeGen/X86/X86Optimizer.cs | 2 +- src/ARMeilleure/CodeGen/X86/X86Register.cs | 31 +- src/ARMeilleure/Common/ArenaAllocator.cs | 15 +- src/ARMeilleure/Common/BitMap.cs | 12 +- src/ARMeilleure/Decoders/Block.cs | 16 +- src/ARMeilleure/Decoders/Condition.cs | 26 +- src/ARMeilleure/Decoders/DataOp.cs | 8 +- src/ARMeilleure/Decoders/Decoder.cs | 34 +- src/ARMeilleure/Decoders/DecoderHelper.cs | 46 +- src/ARMeilleure/Decoders/DecoderMode.cs | 2 +- src/ARMeilleure/Decoders/IOpCode.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32Alu.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32AluImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32AluImm16.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32BImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32BReg.cs | 2 +- .../Decoders/IOpCode32Exception.cs | 2 +- .../Decoders/IOpCode32HasSetFlags.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32Mem.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32MemMult.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32MemReg.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCodeAlu.cs | 2 +- src/ARMeilleure/Decoders/IOpCodeAluImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCodeAluRs.cs | 4 +- src/ARMeilleure/Decoders/IOpCodeAluRx.cs | 4 +- src/ARMeilleure/Decoders/IOpCodeBImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCodeCond.cs | 2 +- src/ARMeilleure/Decoders/IOpCodeLit.cs | 10 +- src/ARMeilleure/Decoders/IOpCodeSimd.cs | 2 +- src/ARMeilleure/Decoders/InstDescriptor.cs | 8 +- src/ARMeilleure/Decoders/InstEmitter.cs | 2 +- src/ARMeilleure/Decoders/IntType.cs | 12 +- src/ARMeilleure/Decoders/OpCode.cs | 27 +- src/ARMeilleure/Decoders/OpCode32.cs | 2 +- src/ARMeilleure/Decoders/OpCode32Alu.cs | 2 +- src/ARMeilleure/Decoders/OpCode32AluImm.cs | 2 +- src/ARMeilleure/Decoders/OpCode32AluRsImm.cs | 6 +- src/ARMeilleure/Decoders/OpCode32BImm.cs | 2 +- src/ARMeilleure/Decoders/OpCode32BReg.cs | 2 +- src/ARMeilleure/Decoders/OpCode32Mem.cs | 20 +- src/ARMeilleure/Decoders/OpCode32MemImm.cs | 2 +- src/ARMeilleure/Decoders/OpCode32MemImm8.cs | 2 +- src/ARMeilleure/Decoders/OpCode32MemMult.cs | 12 +- src/ARMeilleure/Decoders/OpCode32Mrs.cs | 4 +- src/ARMeilleure/Decoders/OpCode32MsrReg.cs | 8 +- src/ARMeilleure/Decoders/OpCode32Sat.cs | 2 +- src/ARMeilleure/Decoders/OpCode32Sat16.cs | 2 +- src/ARMeilleure/Decoders/OpCode32SimdBase.cs | 24 +- src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs | 6 +- src/ARMeilleure/Decoders/OpCode32SimdLong.cs | 12 +- .../Decoders/OpCode32SimdMemPair.cs | 4 +- src/ARMeilleure/Decoders/OpCode32SimdSel.cs | 2 +- src/ARMeilleure/Decoders/OpCodeAdr.cs | 6 +- src/ARMeilleure/Decoders/OpCodeAlu.cs | 6 +- src/ARMeilleure/Decoders/OpCodeAluBinary.cs | 2 +- src/ARMeilleure/Decoders/OpCodeAluImm.cs | 4 +- src/ARMeilleure/Decoders/OpCodeAluRs.cs | 6 +- src/ARMeilleure/Decoders/OpCodeAluRx.cs | 8 +- src/ARMeilleure/Decoders/OpCodeBImm.cs | 2 +- src/ARMeilleure/Decoders/OpCodeBImmAl.cs | 2 +- src/ARMeilleure/Decoders/OpCodeBImmCmp.cs | 2 +- src/ARMeilleure/Decoders/OpCodeBImmCond.cs | 2 +- src/ARMeilleure/Decoders/OpCodeBImmTest.cs | 6 +- src/ARMeilleure/Decoders/OpCodeBReg.cs | 4 +- src/ARMeilleure/Decoders/OpCodeBfm.cs | 8 +- src/ARMeilleure/Decoders/OpCodeCcmp.cs | 10 +- src/ARMeilleure/Decoders/OpCodeCcmpImm.cs | 2 +- src/ARMeilleure/Decoders/OpCodeCcmpReg.cs | 2 +- src/ARMeilleure/Decoders/OpCodeCsel.cs | 4 +- src/ARMeilleure/Decoders/OpCodeException.cs | 2 +- src/ARMeilleure/Decoders/OpCodeMem.cs | 12 +- src/ARMeilleure/Decoders/OpCodeMemEx.cs | 6 +- src/ARMeilleure/Decoders/OpCodeMemImm.cs | 22 +- src/ARMeilleure/Decoders/OpCodeMemLit.cs | 34 +- src/ARMeilleure/Decoders/OpCodeMemPair.cs | 10 +- src/ARMeilleure/Decoders/OpCodeMemReg.cs | 12 +- src/ARMeilleure/Decoders/OpCodeMov.cs | 8 +- src/ARMeilleure/Decoders/OpCodeMul.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimd.cs | 14 +- src/ARMeilleure/Decoders/OpCodeSimdCvt.cs | 4 +- src/ARMeilleure/Decoders/OpCodeSimdExt.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimdFcond.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimdFmov.cs | 8 +- src/ARMeilleure/Decoders/OpCodeSimdHelper.cs | 9 +- src/ARMeilleure/Decoders/OpCodeSimdImm.cs | 21 +- src/ARMeilleure/Decoders/OpCodeSimdIns.cs | 20 +- src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs | 8 +- src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs | 51 +- src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs | 100 +-- src/ARMeilleure/Decoders/OpCodeSimdReg.cs | 12 +- src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs | 8 +- .../Decoders/OpCodeSimdRegElemF.cs | 4 +- src/ARMeilleure/Decoders/OpCodeSimdTbl.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSystem.cs | 14 +- src/ARMeilleure/Decoders/OpCodeT16.cs | 2 +- .../Decoders/OpCodeT16AddSubImm3.cs | 6 +- src/ARMeilleure/Decoders/OpCodeT16BImm11.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT16BImm8.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs | 22 +- src/ARMeilleure/Decoders/OpCodeT16MemMult.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs | 4 +- src/ARMeilleure/Decoders/OpCodeT32.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32Alu.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32AluImm.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32AluReg.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs | 6 +- src/ARMeilleure/Decoders/OpCodeT32BImm20.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32BImm24.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs | 4 +- src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs | 4 +- src/ARMeilleure/Decoders/OpCodeT32MemMult.cs | 12 +- src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs | 4 +- src/ARMeilleure/Decoders/OpCodeT32Tb.cs | 2 +- src/ARMeilleure/Decoders/OpCodeTable.cs | 67 +- .../Decoders/Optimizations/TailCallRemover.cs | 12 +- src/ARMeilleure/Decoders/RegisterSize.cs | 4 +- src/ARMeilleure/Decoders/ShiftType.cs | 4 +- src/ARMeilleure/Diagnostics/IRDumper.cs | 32 +- src/ARMeilleure/Diagnostics/Logger.cs | 4 +- src/ARMeilleure/Diagnostics/PassName.cs | 4 +- src/ARMeilleure/Diagnostics/Symbols.cs | 3 +- .../Diagnostics/TranslatorEventSource.cs | 6 +- src/ARMeilleure/Instructions/CryptoHelper.cs | 38 +- src/ARMeilleure/Instructions/InstEmitAlu.cs | 19 +- src/ARMeilleure/Instructions/InstEmitAlu32.cs | 3 +- .../Instructions/InstEmitAluHelper.cs | 135 ++-- src/ARMeilleure/Instructions/InstEmitBfm.cs | 6 +- src/ARMeilleure/Instructions/InstEmitCcmp.cs | 5 +- src/ARMeilleure/Instructions/InstEmitCsel.cs | 7 +- src/ARMeilleure/Instructions/InstEmitDiv.cs | 7 +- .../Instructions/InstEmitException.cs | 2 +- src/ARMeilleure/Instructions/InstEmitFlow.cs | 6 +- .../Instructions/InstEmitFlow32.cs | 6 +- .../Instructions/InstEmitFlowHelper.cs | 76 +-- .../Instructions/InstEmitHashHelper.cs | 16 +- .../Instructions/InstEmitHelper.cs | 129 ++-- .../Instructions/InstEmitMemory.cs | 68 +- .../Instructions/InstEmitMemory32.cs | 25 +- .../Instructions/InstEmitMemoryEx.cs | 35 +- .../Instructions/InstEmitMemoryExHelper.cs | 13 +- .../Instructions/InstEmitMemoryHelper.cs | 261 +++++--- src/ARMeilleure/Instructions/InstEmitMove.cs | 2 +- src/ARMeilleure/Instructions/InstEmitMul.cs | 13 +- src/ARMeilleure/Instructions/InstEmitMul32.cs | 11 +- .../Instructions/InstEmitSimdArithmetic.cs | 116 ++-- .../Instructions/InstEmitSimdArithmetic32.cs | 9 +- .../Instructions/InstEmitSimdCmp.cs | 7 +- .../Instructions/InstEmitSimdCvt.cs | 149 +++-- .../Instructions/InstEmitSimdCvt32.cs | 55 +- .../Instructions/InstEmitSimdHash.cs | 8 +- .../Instructions/InstEmitSimdHash32.cs | 4 +- .../Instructions/InstEmitSimdHashHelper.cs | 6 +- .../Instructions/InstEmitSimdHelper.cs | 174 ++--- .../Instructions/InstEmitSimdHelper32.cs | 49 +- .../Instructions/InstEmitSimdHelper32Arm64.cs | 18 +- .../Instructions/InstEmitSimdHelperArm64.cs | 8 +- .../Instructions/InstEmitSimdLogical.cs | 21 +- .../Instructions/InstEmitSimdLogical32.cs | 24 +- .../Instructions/InstEmitSimdMemory.cs | 4 +- .../Instructions/InstEmitSimdMove.cs | 85 ++- .../Instructions/InstEmitSimdMove32.cs | 7 +- .../Instructions/InstEmitSimdShift.cs | 39 +- .../Instructions/InstEmitSimdShift32.cs | 7 +- .../Instructions/InstEmitSystem.cs | 90 ++- .../Instructions/InstEmitSystem32.cs | 55 +- .../Instructions/NativeInterface.cs | 6 +- src/ARMeilleure/Instructions/SoftFallback.cs | 94 ++- src/ARMeilleure/Instructions/SoftFloat.cs | 306 ++++----- .../IntermediateRepresentation/BasicBlock.cs | 11 +- .../BasicBlockFrequency.cs | 4 +- .../IntermediateRepresentation/Comparison.cs | 20 +- .../IntermediateRepresentation/Instruction.cs | 4 +- .../IntermediateRepresentation/Intrinsic.cs | 6 +- .../MemoryOperand.cs | 12 +- .../IntermediateRepresentation/Multiplier.cs | 4 +- .../IntermediateRepresentation/Operand.cs | 80 +-- .../IntermediateRepresentation/OperandKind.cs | 4 +- .../IntermediateRepresentation/OperandType.cs | 55 +- .../IntermediateRepresentation/Operation.cs | 64 +- .../IntermediateRepresentation/Register.cs | 6 +- .../RegisterType.cs | 4 +- src/ARMeilleure/Memory/IJitMemoryBlock.cs | 2 +- src/ARMeilleure/Memory/IMemoryManager.cs | 2 +- src/ARMeilleure/Memory/MemoryManagerType.cs | 2 +- src/ARMeilleure/Native/JitSupportDarwin.cs | 2 +- src/ARMeilleure/Optimizations.cs | 44 +- src/ARMeilleure/Signal/NativeSignalHandler.cs | 18 +- src/ARMeilleure/Signal/TestMethods.cs | 6 +- .../Signal/UnixSignalHandlerRegistration.cs | 4 +- .../Signal/WindowsPartialUnmapHandler.cs | 2 + src/ARMeilleure/State/Aarch32Mode.cs | 16 +- src/ARMeilleure/State/ExceptionCallback.cs | 2 +- src/ARMeilleure/State/ExecutionContext.cs | 6 +- src/ARMeilleure/State/ExecutionMode.cs | 4 +- src/ARMeilleure/State/FPCR.cs | 6 +- src/ARMeilleure/State/FPException.cs | 10 +- src/ARMeilleure/State/FPRoundingMode.cs | 8 +- src/ARMeilleure/State/FPSCR.cs | 2 +- src/ARMeilleure/State/FPSR.cs | 2 +- src/ARMeilleure/State/FPState.cs | 2 +- src/ARMeilleure/State/FPType.cs | 2 +- src/ARMeilleure/State/ICounter.cs | 2 +- src/ARMeilleure/State/NativeContext.cs | 4 +- src/ARMeilleure/State/PState.cs | 2 +- src/ARMeilleure/State/RegisterAlias.cs | 18 +- src/ARMeilleure/State/RegisterConsts.cs | 14 +- src/ARMeilleure/State/V128.cs | 40 +- src/ARMeilleure/Statistics.cs | 14 +- .../Translation/ArmEmitterContext.cs | 10 +- .../Translation/Cache/CacheEntry.cs | 8 +- .../Translation/Cache/CacheMemoryAllocator.cs | 2 +- src/ARMeilleure/Translation/Cache/JitCache.cs | 32 +- .../Translation/Cache/JitCacheInvalidation.cs | 8 +- .../Translation/Cache/JitUnwindWindows.cs | 113 ++-- src/ARMeilleure/Translation/Compiler.cs | 10 +- .../Translation/CompilerContext.cs | 18 +- .../Translation/CompilerOptions.cs | 12 +- .../Translation/ControlFlowGraph.cs | 4 +- src/ARMeilleure/Translation/DelegateInfo.cs | 2 + src/ARMeilleure/Translation/Dominance.cs | 4 +- src/ARMeilleure/Translation/EmitterContext.cs | 8 +- src/ARMeilleure/Translation/GuestFunction.cs | 2 +- src/ARMeilleure/Translation/IntervalTree.cs | 132 ++-- .../Translation/PTC/EncodingCache.cs | 2 +- .../Translation/PTC/IPtcLoadState.cs | 2 +- src/ARMeilleure/Translation/PTC/Ptc.cs | 405 ++++++------ .../Translation/PTC/PtcFormatter.cs | 4 +- .../Translation/PTC/PtcLoadingState.cs | 4 +- .../Translation/PTC/PtcProfiler.cs | 130 ++-- src/ARMeilleure/Translation/PTC/PtcState.cs | 4 +- .../Translation/RegisterToLocal.cs | 4 +- src/ARMeilleure/Translation/RegisterUsage.cs | 25 +- .../Translation/SsaConstruction.cs | 4 +- .../Translation/SsaDeconstruction.cs | 2 +- .../Translation/TranslatedFunction.cs | 2 +- src/ARMeilleure/Translation/Translator.cs | 16 +- .../Translation/TranslatorStubs.cs | 2 +- .../Translation/TranslatorTestMethods.cs | 5 +- 300 files changed, 3515 insertions(+), 3120 deletions(-) diff --git a/src/ARMeilleure/Allocators.cs b/src/ARMeilleure/Allocators.cs index deabf9a2..ba782b99 100644 --- a/src/ARMeilleure/Allocators.cs +++ b/src/ARMeilleure/Allocators.cs @@ -23,10 +23,7 @@ namespace ARMeilleure [MethodImpl(MethodImplOptions.AggressiveInlining)] private static ArenaAllocator GetAllocator(ref ArenaAllocator alloc, uint pageSize, uint pageCount) { - if (alloc == null) - { - alloc = new ArenaAllocator(pageSize, pageCount); - } + alloc ??= new ArenaAllocator(pageSize, pageCount); return alloc; } diff --git a/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs b/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs index fdd4d024..00ffd195 100644 --- a/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs +++ b/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs @@ -221,7 +221,7 @@ namespace ARMeilleure.CodeGen.Arm64 2 => Multiplier.x4, 3 => Multiplier.x8, 4 => Multiplier.x16, - _ => Multiplier.x1 + _ => Multiplier.x1, }; baseOp = indexOnSrc2 ? src1 : src2; diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs b/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs index db27a810..5db89859 100644 --- a/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs +++ b/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs @@ -5,22 +5,22 @@ namespace ARMeilleure.CodeGen.Arm64 { enum ArmCondition { - Eq = 0, - Ne = 1, + Eq = 0, + Ne = 1, GeUn = 2, LtUn = 3, - Mi = 4, - Pl = 5, - Vs = 6, - Vc = 7, + Mi = 4, + Pl = 5, + Vs = 6, + Vc = 7, GtUn = 8, LeUn = 9, - Ge = 10, - Lt = 11, - Gt = 12, - Le = 13, - Al = 14, - Nv = 15 + Ge = 10, + Lt = 11, + Gt = 12, + Le = 13, + Al = 14, + Nv = 15, } static class ComparisonArm64Extensions @@ -29,6 +29,7 @@ namespace ARMeilleure.CodeGen.Arm64 { return comp switch { +#pragma warning disable IDE0055 // Disable formatting Comparison.Equal => ArmCondition.Eq, Comparison.NotEqual => ArmCondition.Ne, Comparison.Greater => ArmCondition.Gt, @@ -39,8 +40,9 @@ namespace ARMeilleure.CodeGen.Arm64 Comparison.Less => ArmCondition.Lt, Comparison.GreaterOrEqualUI => ArmCondition.GeUn, Comparison.LessUI => ArmCondition.LtUn, +#pragma warning restore IDE0055 - _ => throw new ArgumentException(null, nameof(comp)) + _ => throw new ArgumentException(null, nameof(comp)), }; } } diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs b/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs index 062a6d0b..20ccfd4b 100644 --- a/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs +++ b/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs @@ -9,6 +9,6 @@ namespace ARMeilleure.CodeGen.Arm64 Sxtb = 4, Sxth = 5, Sxtw = 6, - Sxtx = 7 + Sxtx = 7, } } diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs b/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs index d223a146..f32407c4 100644 --- a/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs +++ b/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs @@ -6,6 +6,6 @@ namespace ARMeilleure.CodeGen.Arm64 Lsl = 0, Lsr = 1, Asr = 2, - Ror = 3 + Ror = 3, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/Assembler.cs b/src/ARMeilleure/CodeGen/Arm64/Assembler.cs index 0ec0be7c..41684faf 100644 --- a/src/ARMeilleure/CodeGen/Arm64/Assembler.cs +++ b/src/ARMeilleure/CodeGen/Arm64/Assembler.cs @@ -188,7 +188,7 @@ namespace ARMeilleure.CodeGen.Arm64 uint rmode = topHalf ? 1u << 19 : 0u; uint ftype = rd.Type == OperandType.FP64 || rn.Type == OperandType.FP64 ? 1u << 22 : 0u; - uint sf = rd.Type == OperandType.I64 || rn.Type == OperandType.I64 ? SfFlag : 0u; + uint sf = rd.Type == OperandType.I64 || rn.Type == OperandType.I64 ? SfFlag : 0u; WriteUInt32(0x1e260000u | (opcode << 16) | rmode | ftype | sf | EncodeReg(rd) | (EncodeReg(rn) << 5)); } @@ -992,7 +992,7 @@ namespace ARMeilleure.CodeGen.Arm64 { OperandType.FP32 => 0, OperandType.FP64 => 1, - _ => 2 + _ => 2, }; instruction = vecInst | ((uint)opc << 30); @@ -1124,10 +1124,11 @@ namespace ARMeilleure.CodeGen.Arm64 OperandType.FP32 => 2, OperandType.FP64 => 3, OperandType.V128 => 4, - _ => throw new ArgumentException($"Invalid type {type}.") + _ => throw new ArgumentException($"Invalid type {type}."), }; } +#pragma warning disable IDE0051 // Remove unused private member private void WriteInt16(short value) { WriteUInt16((ushort)value); @@ -1142,6 +1143,7 @@ namespace ARMeilleure.CodeGen.Arm64 { _stream.WriteByte(value); } +#pragma warning restore IDE0051 private void WriteUInt16(ushort value) { diff --git a/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs b/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs index fda8d786..a487c2ed 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs @@ -93,4 +93,4 @@ namespace ARMeilleure.CodeGen.Arm64 return 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs index 8d1e597b..1f0148d5 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs @@ -88,4 +88,4 @@ namespace ARMeilleure.CodeGen.Arm64 return true; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs index 0dd5355f..12ebabdd 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs @@ -14,7 +14,7 @@ namespace ARMeilleure.CodeGen.Arm64 private const int CbnzInstLength = 4; private const int LdrLitInstLength = 4; - private Stream _stream; + private readonly Stream _stream; public int StreamOffset => (int)_stream.Length; @@ -32,7 +32,7 @@ namespace ARMeilleure.CodeGen.Arm64 private readonly Dictionary _visitedBlocks; private readonly Dictionary> _pendingBranches; - private struct ConstantPoolEntry + private readonly struct ConstantPoolEntry { public readonly int Offset; public readonly Symbol Symbol; @@ -58,7 +58,7 @@ namespace ARMeilleure.CodeGen.Arm64 private readonly bool _relocatable; - public CodeGenContext(AllocationResult allocResult, int maxCallArgs, int blocksCount, bool relocatable) + public CodeGenContext(AllocationResult allocResult, int maxCallArgs, bool relocatable) { _stream = MemoryStreamManager.Shared.GetStream(); @@ -93,10 +93,10 @@ namespace ARMeilleure.CodeGen.Arm64 if (_pendingBranches.TryGetValue(block, out var list)) { - foreach (var tuple in list) + foreach ((ArmCondition condition, long branchPos) in list) { - _stream.Seek(tuple.BranchPos, SeekOrigin.Begin); - WriteBranch(tuple.Condition, target); + _stream.Seek(branchPos, SeekOrigin.Begin); + WriteBranch(condition, target); } _stream.Seek(target, SeekOrigin.Begin); @@ -284,4 +284,4 @@ namespace ARMeilleure.CodeGen.Arm64 _stream.WriteByte((byte)(value >> 56)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs index 92719850..2df86671 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs @@ -10,7 +10,6 @@ using System; using System.Collections.Generic; using System.Diagnostics; using System.Numerics; - using static ARMeilleure.IntermediateRepresentation.Operand; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -31,15 +30,16 @@ namespace ARMeilleure.CodeGen.Arm64 { Byte, Hword, - Auto + Auto, } - private static Action[] _instTable; + private static readonly Action[] _instTable; static CodeGenerator() { _instTable = new Action[EnumUtils.GetCount(typeof(Instruction))]; +#pragma warning disable IDE0055 // Disable formatting Add(Instruction.Add, GenerateAdd); Add(Instruction.BitwiseAnd, GenerateBitwiseAnd); Add(Instruction.BitwiseExclusiveOr, GenerateBitwiseExclusiveOr); @@ -48,7 +48,7 @@ namespace ARMeilleure.CodeGen.Arm64 Add(Instruction.BranchIf, GenerateBranchIf); Add(Instruction.ByteSwap, GenerateByteSwap); Add(Instruction.Call, GenerateCall); - //Add(Instruction.Clobber, GenerateClobber); + // Add(Instruction.Clobber, GenerateClobber); Add(Instruction.Compare, GenerateCompare); Add(Instruction.CompareAndSwap, GenerateCompareAndSwap); Add(Instruction.CompareAndSwap16, GenerateCompareAndSwap16); @@ -100,6 +100,7 @@ namespace ARMeilleure.CodeGen.Arm64 Add(Instruction.ZeroExtend16, GenerateZeroExtend16); Add(Instruction.ZeroExtend32, GenerateZeroExtend32); Add(Instruction.ZeroExtend8, GenerateZeroExtend8); +#pragma warning restore IDE0055 static void Add(Instruction inst, Action func) { @@ -131,7 +132,7 @@ namespace ARMeilleure.CodeGen.Arm64 StackAllocator stackAlloc = new(); - PreAllocator.RunPass(cctx, stackAlloc, out int maxCallArgs); + PreAllocator.RunPass(cctx, out int maxCallArgs); Logger.EndPass(PassName.PreAllocation, cfg); @@ -170,7 +171,7 @@ namespace ARMeilleure.CodeGen.Arm64 bool relocatable = (cctx.Options & CompilerOptions.Relocatable) != 0; - CodeGenContext context = new(allocResult, maxCallArgs, cfg.Blocks.Count, relocatable); + CodeGenContext context = new(allocResult, maxCallArgs, relocatable); UnwindInfo unwindInfo = WritePrologue(context); @@ -292,7 +293,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateBitwiseNot(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -330,7 +331,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateByteSwap(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -364,15 +365,15 @@ namespace ARMeilleure.CodeGen.Arm64 { if (operation.SourcesCount == 5) // CompareAndSwap128 has 5 sources, compared to CompareAndSwap64/32's 3. { - Operand actualLow = operation.GetDestination(0); - Operand actualHigh = operation.GetDestination(1); - Operand temp0 = operation.GetDestination(2); - Operand temp1 = operation.GetDestination(3); - Operand address = operation.GetSource(0); - Operand expectedLow = operation.GetSource(1); + Operand actualLow = operation.GetDestination(0); + Operand actualHigh = operation.GetDestination(1); + Operand temp0 = operation.GetDestination(2); + Operand temp1 = operation.GetDestination(3); + Operand address = operation.GetSource(0); + Operand expectedLow = operation.GetSource(1); Operand expectedHigh = operation.GetSource(2); - Operand desiredLow = operation.GetSource(3); - Operand desiredHigh = operation.GetSource(4); + Operand desiredLow = operation.GetSource(3); + Operand desiredHigh = operation.GetSource(4); GenerateAtomicDcas( context, @@ -388,11 +389,11 @@ namespace ARMeilleure.CodeGen.Arm64 } else { - Operand actual = operation.GetDestination(0); - Operand result = operation.GetDestination(1); - Operand address = operation.GetSource(0); + Operand actual = operation.GetDestination(0); + Operand result = operation.GetDestination(1); + Operand address = operation.GetSource(0); Operand expected = operation.GetSource(1); - Operand desired = operation.GetSource(2); + Operand desired = operation.GetSource(2); GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Auto); } @@ -400,22 +401,22 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateCompareAndSwap16(CodeGenContext context, Operation operation) { - Operand actual = operation.GetDestination(0); - Operand result = operation.GetDestination(1); - Operand address = operation.GetSource(0); + Operand actual = operation.GetDestination(0); + Operand result = operation.GetDestination(1); + Operand address = operation.GetSource(0); Operand expected = operation.GetSource(1); - Operand desired = operation.GetSource(2); + Operand desired = operation.GetSource(2); GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Hword); } private static void GenerateCompareAndSwap8(CodeGenContext context, Operation operation) { - Operand actual = operation.GetDestination(0); - Operand result = operation.GetDestination(1); - Operand address = operation.GetSource(0); + Operand actual = operation.GetDestination(0); + Operand result = operation.GetDestination(1); + Operand address = operation.GetSource(0); Operand expected = operation.GetSource(1); - Operand desired = operation.GetSource(2); + Operand desired = operation.GetSource(2); GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Byte); } @@ -444,13 +445,13 @@ namespace ARMeilleure.CodeGen.Arm64 Debug.Assert(dest.Type.IsInteger()); Debug.Assert(src1.Type == OperandType.I32); - context.Assembler.Cmp (src1, Const(src1.Type, 0)); + context.Assembler.Cmp(src1, Const(src1.Type, 0)); context.Assembler.Csel(dest, src2, src3, ArmCondition.Ne); } private static void GenerateConvertI64ToI32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.I32 && source.Type == OperandType.I64); @@ -460,7 +461,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateConvertToFP(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64); @@ -479,7 +480,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateConvertToFPUI(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64); @@ -491,7 +492,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateCopy(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); EnsureSameType(dest, source); @@ -523,7 +524,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateCountLeadingZeros(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); EnsureSameType(dest, source); @@ -535,9 +536,9 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateDivide(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand dividend = operation.GetSource(0); - Operand divisor = operation.GetSource(1); + Operand divisor = operation.GetSource(1); ValidateBinOp(dest, dividend, divisor); @@ -553,9 +554,9 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateDivideUI(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand dividend = operation.GetSource(0); - Operand divisor = operation.GetSource(1); + Operand divisor = operation.GetSource(1); ValidateBinOp(dest, dividend, divisor); @@ -564,7 +565,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateLoad(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = operation.GetSource(0); context.Assembler.Ldr(value, address); @@ -572,7 +573,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateLoad16(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = operation.GetSource(0); Debug.Assert(value.Type.IsInteger()); @@ -582,7 +583,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateLoad8(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = operation.GetSource(0); Debug.Assert(value.Type.IsInteger()); @@ -641,7 +642,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateNegate(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -728,7 +729,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateSignExtend16(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -738,7 +739,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateSignExtend32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -748,7 +749,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateSignExtend8(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -758,7 +759,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateFill(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand offset = operation.GetSource(0); Debug.Assert(offset.Kind == OperandKind.Constant); @@ -799,7 +800,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateStackAlloc(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand offset = operation.GetSource(0); Debug.Assert(offset.Kind == OperandKind.Constant); @@ -811,7 +812,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateStore(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = operation.GetSource(0); context.Assembler.Str(value, address); @@ -819,7 +820,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateStore16(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = operation.GetSource(0); Debug.Assert(value.Type.IsInteger()); @@ -829,7 +830,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateStore8(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = operation.GetSource(0); Debug.Assert(value.Type.IsInteger()); @@ -876,7 +877,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateVectorCreateScalar(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); if (dest != default) @@ -1022,7 +1023,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128); @@ -1032,7 +1033,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128); @@ -1042,7 +1043,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateZeroExtend16(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1052,7 +1053,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateZeroExtend32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1068,7 +1069,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateZeroExtend8(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1078,7 +1079,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static UnwindInfo WritePrologue(CodeGenContext context) { - List pushEntries = new List(); + List pushEntries = new(); Operand rsp = Register(SpRegister); @@ -1568,11 +1569,13 @@ namespace ARMeilleure.CodeGen.Arm64 Debug.Assert(op1.Type == op3.Type); } +#pragma warning disable IDE0051 // Remove unused private member private static void EnsureSameType(Operand op1, Operand op2, Operand op3, Operand op4) { Debug.Assert(op1.Type == op2.Type); Debug.Assert(op1.Type == op3.Type); Debug.Assert(op1.Type == op4.Type); } +#pragma warning restore IDE0051 } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs index 1309404a..b8737055 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs @@ -688,4 +688,4 @@ namespace ARMeilleure.CodeGen.Arm64 context.Assembler.WriteInstruction(instruction, rd, rn); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs b/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs index 99ff299e..86afc2b4 100644 --- a/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs +++ b/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs @@ -1,7 +1,4 @@ using System; -using System.Linq; -using System.Reflection; -using System.Runtime.CompilerServices; using System.Runtime.InteropServices; using System.Runtime.Intrinsics.Arm; using System.Runtime.Versioning; @@ -35,7 +32,7 @@ namespace ARMeilleure.CodeGen.Arm64 } } -#region Linux + #region Linux private const ulong AT_HWCAP = 16; private const ulong AT_HWCAP2 = 26; @@ -46,88 +43,88 @@ namespace ARMeilleure.CodeGen.Arm64 [Flags] public enum LinuxFeatureFlagsHwCap : ulong { - Fp = 1 << 0, - Asimd = 1 << 1, - Evtstrm = 1 << 2, - Aes = 1 << 3, - Pmull = 1 << 4, - Sha1 = 1 << 5, - Sha2 = 1 << 6, - Crc32 = 1 << 7, - Atomics = 1 << 8, - FpHp = 1 << 9, - AsimdHp = 1 << 10, - CpuId = 1 << 11, - AsimdRdm = 1 << 12, - Jscvt = 1 << 13, - Fcma = 1 << 14, - Lrcpc = 1 << 15, - DcpOp = 1 << 16, - Sha3 = 1 << 17, - Sm3 = 1 << 18, - Sm4 = 1 << 19, - AsimdDp = 1 << 20, - Sha512 = 1 << 21, - Sve = 1 << 22, - AsimdFhm = 1 << 23, - Dit = 1 << 24, - Uscat = 1 << 25, - Ilrcpc = 1 << 26, - FlagM = 1 << 27, - Ssbs = 1 << 28, - Sb = 1 << 29, - Paca = 1 << 30, - Pacg = 1UL << 31 + Fp = 1 << 0, + Asimd = 1 << 1, + Evtstrm = 1 << 2, + Aes = 1 << 3, + Pmull = 1 << 4, + Sha1 = 1 << 5, + Sha2 = 1 << 6, + Crc32 = 1 << 7, + Atomics = 1 << 8, + FpHp = 1 << 9, + AsimdHp = 1 << 10, + CpuId = 1 << 11, + AsimdRdm = 1 << 12, + Jscvt = 1 << 13, + Fcma = 1 << 14, + Lrcpc = 1 << 15, + DcpOp = 1 << 16, + Sha3 = 1 << 17, + Sm3 = 1 << 18, + Sm4 = 1 << 19, + AsimdDp = 1 << 20, + Sha512 = 1 << 21, + Sve = 1 << 22, + AsimdFhm = 1 << 23, + Dit = 1 << 24, + Uscat = 1 << 25, + Ilrcpc = 1 << 26, + FlagM = 1 << 27, + Ssbs = 1 << 28, + Sb = 1 << 29, + Paca = 1 << 30, + Pacg = 1UL << 31, } [Flags] public enum LinuxFeatureFlagsHwCap2 : ulong { - Dcpodp = 1 << 0, - Sve2 = 1 << 1, - SveAes = 1 << 2, - SvePmull = 1 << 3, - SveBitperm = 1 << 4, - SveSha3 = 1 << 5, - SveSm4 = 1 << 6, - FlagM2 = 1 << 7, - Frint = 1 << 8, - SveI8mm = 1 << 9, - SveF32mm = 1 << 10, - SveF64mm = 1 << 11, - SveBf16 = 1 << 12, - I8mm = 1 << 13, - Bf16 = 1 << 14, - Dgh = 1 << 15, - Rng = 1 << 16, - Bti = 1 << 17, - Mte = 1 << 18, - Ecv = 1 << 19, - Afp = 1 << 20, - Rpres = 1 << 21, - Mte3 = 1 << 22, - Sme = 1 << 23, - Sme_i16i64 = 1 << 24, - Sme_f64f64 = 1 << 25, - Sme_i8i32 = 1 << 26, - Sme_f16f32 = 1 << 27, - Sme_b16f32 = 1 << 28, - Sme_f32f32 = 1 << 29, - Sme_fa64 = 1 << 30, - Wfxt = 1UL << 31, - Ebf16 = 1UL << 32, - Sve_Ebf16 = 1UL << 33, - Cssc = 1UL << 34, - Rprfm = 1UL << 35, - Sve2p1 = 1UL << 36 + Dcpodp = 1 << 0, + Sve2 = 1 << 1, + SveAes = 1 << 2, + SvePmull = 1 << 3, + SveBitperm = 1 << 4, + SveSha3 = 1 << 5, + SveSm4 = 1 << 6, + FlagM2 = 1 << 7, + Frint = 1 << 8, + SveI8mm = 1 << 9, + SveF32mm = 1 << 10, + SveF64mm = 1 << 11, + SveBf16 = 1 << 12, + I8mm = 1 << 13, + Bf16 = 1 << 14, + Dgh = 1 << 15, + Rng = 1 << 16, + Bti = 1 << 17, + Mte = 1 << 18, + Ecv = 1 << 19, + Afp = 1 << 20, + Rpres = 1 << 21, + Mte3 = 1 << 22, + Sme = 1 << 23, + Sme_i16i64 = 1 << 24, + Sme_f64f64 = 1 << 25, + Sme_i8i32 = 1 << 26, + Sme_f16f32 = 1 << 27, + Sme_b16f32 = 1 << 28, + Sme_f32f32 = 1 << 29, + Sme_fa64 = 1 << 30, + Wfxt = 1UL << 31, + Ebf16 = 1UL << 32, + Sve_Ebf16 = 1UL << 33, + Cssc = 1UL << 34, + Rprfm = 1UL << 35, + Sve2p1 = 1UL << 36, } public static LinuxFeatureFlagsHwCap LinuxFeatureInfoHwCap { get; } = 0; public static LinuxFeatureFlagsHwCap2 LinuxFeatureInfoHwCap2 { get; } = 0; -#endregion + #endregion -#region macOS + #region macOS [LibraryImport("libSystem.dylib", SetLastError = true)] private static unsafe partial int sysctlbyname([MarshalAs(UnmanagedType.LPStr)] string name, out int oldValue, ref ulong oldSize, IntPtr newValue, ulong newValueSize); @@ -143,7 +140,7 @@ namespace ARMeilleure.CodeGen.Arm64 return false; } - private static string[] _sysctlNames = new string[] + private static readonly string[] _sysctlNames = new string[] { "hw.optional.floatingpoint", "hw.optional.AdvSIMD", @@ -153,26 +150,26 @@ namespace ARMeilleure.CodeGen.Arm64 "hw.optional.arm.FEAT_LSE", "hw.optional.armv8_crc32", "hw.optional.arm.FEAT_SHA1", - "hw.optional.arm.FEAT_SHA256" + "hw.optional.arm.FEAT_SHA256", }; [Flags] public enum MacOsFeatureFlags { - Fp = 1 << 0, + Fp = 1 << 0, AdvSimd = 1 << 1, - Fp16 = 1 << 2, - Aes = 1 << 3, - Pmull = 1 << 4, - Lse = 1 << 5, - Crc32 = 1 << 6, - Sha1 = 1 << 7, - Sha256 = 1 << 8 + Fp16 = 1 << 2, + Aes = 1 << 3, + Pmull = 1 << 4, + Lse = 1 << 5, + Crc32 = 1 << 6, + Sha1 = 1 << 7, + Sha256 = 1 << 8, } public static MacOsFeatureFlags MacOsFeatureInfo { get; } = 0; -#endregion + #endregion public static bool SupportsAdvSimd => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Asimd) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.AdvSimd); public static bool SupportsAes => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Aes) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Aes); diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs index 8695db90..956fc778 100644 --- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs +++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs @@ -1,8 +1,8 @@ namespace ARMeilleure.CodeGen.Arm64 { - struct IntrinsicInfo + readonly struct IntrinsicInfo { - public uint Inst { get; } + public uint Inst { get; } public IntrinsicType Type { get; } public IntrinsicInfo(uint inst, IntrinsicType type) @@ -11,4 +11,4 @@ namespace ARMeilleure.CodeGen.Arm64 Type = type; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs index c2bd0bd5..dbd5bdd1 100644 --- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs +++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs @@ -5,12 +5,13 @@ namespace ARMeilleure.CodeGen.Arm64 { static class IntrinsicTable { - private static IntrinsicInfo[] _intrinTable; + private static readonly IntrinsicInfo[] _intrinTable; static IntrinsicTable() { _intrinTable = new IntrinsicInfo[EnumUtils.GetCount(typeof(Intrinsic))]; +#pragma warning disable IDE0055 // Disable formatting Add(Intrinsic.Arm64AbsS, new IntrinsicInfo(0x5e20b800u, IntrinsicType.ScalarUnary)); Add(Intrinsic.Arm64AbsV, new IntrinsicInfo(0x0e20b800u, IntrinsicType.VectorUnary)); Add(Intrinsic.Arm64AddhnV, new IntrinsicInfo(0x0e204000u, IntrinsicType.VectorTernaryRd)); @@ -448,6 +449,7 @@ namespace ARMeilleure.CodeGen.Arm64 Add(Intrinsic.Arm64XtnV, new IntrinsicInfo(0x0e212800u, IntrinsicType.VectorUnary)); Add(Intrinsic.Arm64Zip1V, new IntrinsicInfo(0x0e003800u, IntrinsicType.VectorBinary)); Add(Intrinsic.Arm64Zip2V, new IntrinsicInfo(0x0e007800u, IntrinsicType.VectorBinary)); +#pragma warning restore IDE0055 } private static void Add(Intrinsic intrin, IntrinsicInfo info) @@ -460,4 +462,4 @@ namespace ARMeilleure.CodeGen.Arm64 return _intrinTable[(int)intrin]; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs index df61ea1e..7538575c 100644 --- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs +++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs @@ -55,6 +55,6 @@ namespace ARMeilleure.CodeGen.Arm64 VectorTernaryShrRd, GetRegister, - SetRegister + SetRegister, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs b/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs index 74f80e0f..f66bb66e 100644 --- a/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs +++ b/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs @@ -1,4 +1,3 @@ -using ARMeilleure.CodeGen.RegisterAllocators; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; @@ -31,7 +30,7 @@ namespace ARMeilleure.CodeGen.Arm64 } } - public static void RunPass(CompilerContext cctx, StackAllocator stackAlloc, out int maxCallArgs) + public static void RunPass(CompilerContext cctx, out int maxCallArgs) { maxCallArgs = -1; @@ -41,7 +40,7 @@ namespace ARMeilleure.CodeGen.Arm64 for (BasicBlock block = cctx.Cfg.Blocks.First; block != null; block = block.ListNext) { - ConstantDict constants = new ConstantDict(); + ConstantDict constants = new(); Operation nextNode; @@ -92,7 +91,7 @@ namespace ARMeilleure.CodeGen.Arm64 InsertReturnCopy(block.Operations, node); break; case Instruction.Tailcall: - InsertTailcallCopies(constants, block.Operations, stackAlloc, node, node); + InsertTailcallCopies(constants, block.Operations, node, node); break; } } @@ -138,10 +137,7 @@ namespace ARMeilleure.CodeGen.Arm64 { src2 = node.GetSource(1); - Operand temp = src1; - - src1 = src2; - src2 = temp; + (src2, src1) = (src1, src2); node.SetSource(0, src1); node.SetSource(1, src2); @@ -265,9 +261,9 @@ namespace ARMeilleure.CodeGen.Arm64 Operand dest = operation.Destination; - List sources = new List + List sources = new() { - operation.GetSource(0) + operation.GetSource(0), }; int argsCount = operation.SourcesCount - 1; @@ -302,10 +298,10 @@ namespace ARMeilleure.CodeGen.Arm64 if (source.Type == OperandType.V128 && passOnReg) { // V128 is a struct, we pass each half on a GPR if possible. - Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); + Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); - nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0))); + nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0))); nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg2, source, Const(1))); continue; @@ -339,7 +335,7 @@ namespace ARMeilleure.CodeGen.Arm64 { if (dest.Type == OperandType.V128) { - Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); + Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64); node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, retLReg)); @@ -364,16 +360,14 @@ namespace ARMeilleure.CodeGen.Arm64 operation.SetSources(sources.ToArray()); } - private static void InsertTailcallCopies( - ConstantDict constants, + private static void InsertTailcallCopies(ConstantDict constants, IntrusiveList nodes, - StackAllocator stackAlloc, Operation node, Operation operation) { - List sources = new List + List sources = new() { - operation.GetSource(0) + operation.GetSource(0), }; int argsCount = operation.SourcesCount - 1; @@ -403,7 +397,7 @@ namespace ARMeilleure.CodeGen.Arm64 if (source.Type == OperandType.V128 && passOnReg) { // V128 is a struct, we pass each half on a GPR if possible. - Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); + Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0))); @@ -519,7 +513,7 @@ namespace ARMeilleure.CodeGen.Arm64 if (source.Type == OperandType.V128) { - Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); + Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64); nodes.AddBefore(node, Operation(Instruction.VectorExtract, retLReg, source, Const(0))); diff --git a/src/ARMeilleure/CodeGen/CompiledFunction.cs b/src/ARMeilleure/CodeGen/CompiledFunction.cs index 0560bf2e..3844cbfc 100644 --- a/src/ARMeilleure/CodeGen/CompiledFunction.cs +++ b/src/ARMeilleure/CodeGen/CompiledFunction.cs @@ -35,9 +35,9 @@ namespace ARMeilleure.CodeGen /// Relocation info internal CompiledFunction(byte[] code, UnwindInfo unwindInfo, RelocInfo relocInfo) { - Code = code; + Code = code; UnwindInfo = unwindInfo; - RelocInfo = relocInfo; + RelocInfo = relocInfo; } /// @@ -65,4 +65,4 @@ namespace ARMeilleure.CodeGen return Marshal.GetDelegateForFunctionPointer(codePointer); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs b/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs index a27bfded..d103bc39 100644 --- a/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs +++ b/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs @@ -35,4 +35,4 @@ namespace ARMeilleure.CodeGen.Linking return $"({nameof(Position)} = {Position}, {nameof(Symbol)} = {Symbol})"; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs b/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs index caaf08e3..01ff0347 100644 --- a/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs +++ b/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs @@ -29,4 +29,4 @@ namespace ARMeilleure.CodeGen.Linking _entries = entries; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Linking/SymbolType.cs b/src/ARMeilleure/CodeGen/Linking/SymbolType.cs index b05b6969..ed348751 100644 --- a/src/ARMeilleure/CodeGen/Linking/SymbolType.cs +++ b/src/ARMeilleure/CodeGen/Linking/SymbolType.cs @@ -23,6 +23,6 @@ /// /// Refers to a special symbol which is handled by . /// - Special + Special, } } diff --git a/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs b/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs index c5a22a53..be3dff58 100644 --- a/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs +++ b/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs @@ -164,7 +164,7 @@ namespace ARMeilleure.CodeGen.Optimizations } break; - case Instruction.Multiply: + case Instruction.Multiply: if (type == OperandType.I32) { EvaluateBinaryI32(operation, (x, y) => x * y); @@ -343,4 +343,4 @@ namespace ARMeilleure.CodeGen.Optimizations operation.TurnIntoCopy(Const(op(x, y))); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Optimizations/Optimizer.cs b/src/ARMeilleure/CodeGen/Optimizations/Optimizer.cs index a45bb455..1afc3a78 100644 --- a/src/ARMeilleure/CodeGen/Optimizations/Optimizer.cs +++ b/src/ARMeilleure/CodeGen/Optimizations/Optimizer.cs @@ -182,7 +182,7 @@ namespace ARMeilleure.CodeGen.Optimizations private static void PropagateCopy(ref Span buffer, Operation copyOp) { // Propagate copy source operand to all uses of the destination operand. - Operand dest = copyOp.Destination; + Operand dest = copyOp.Destination; Operand source = copyOp.GetSource(0); Span uses = dest.GetUses(ref buffer); @@ -249,4 +249,4 @@ namespace ARMeilleure.CodeGen.Optimizations return operation.Destination.Type == operation.GetSource(0).Type; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs b/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs index a439d642..53a7f3ed 100644 --- a/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs +++ b/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs @@ -171,13 +171,12 @@ namespace ARMeilleure.CodeGen.Optimizations private static ulong AllOnes(OperandType type) { - switch (type) + return type switch { - case OperandType.I32: return ~0U; - case OperandType.I64: return ~0UL; - } - - throw new ArgumentException("Invalid operand type \"" + type + "\"."); + OperandType.I32 => ~0U, + OperandType.I64 => ~0UL, + _ => throw new ArgumentException("Invalid operand type \"" + type + "\"."), + }; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs index 43e5c7e2..7b9c2f77 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs @@ -4,7 +4,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { public int IntUsedRegisters { get; } public int VecUsedRegisters { get; } - public int SpillRegionSize { get; } + public int SpillRegionSize { get; } public AllocationResult( int intUsedRegisters, @@ -13,7 +13,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { IntUsedRegisters = intUsedRegisters; VecUsedRegisters = vecUsedRegisters; - SpillRegionSize = spillRegionSize; + SpillRegionSize = spillRegionSize; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs index 587b1a02..af10330b 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs @@ -1,7 +1,6 @@ using ARMeilleure.IntermediateRepresentation; using System; using System.Collections.Generic; - using static ARMeilleure.IntermediateRepresentation.Operand.Factory; using static ARMeilleure.IntermediateRepresentation.Operation.Factory; @@ -13,16 +12,16 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { private readonly struct Copy { - public Register Dest { get; } + public Register Dest { get; } public Register Source { get; } public OperandType Type { get; } public Copy(Register dest, Register source, OperandType type) { - Dest = dest; + Dest = dest; Source = source; - Type = type; + Type = type; } } @@ -42,19 +41,19 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public void Sequence(List sequence) { - Dictionary locations = new Dictionary(); - Dictionary sources = new Dictionary(); + Dictionary locations = new(); + Dictionary sources = new(); - Dictionary types = new Dictionary(); + Dictionary types = new(); - Queue pendingQueue = new Queue(); - Queue readyQueue = new Queue(); + Queue pendingQueue = new(); + Queue readyQueue = new(); foreach (Copy copy in _copies) { locations[copy.Source] = copy.Source; - sources[copy.Dest] = copy.Source; - types[copy.Dest] = copy.Type; + sources[copy.Dest] = copy.Source; + types[copy.Dest] = copy.Type; pendingQueue.Enqueue(copy.Dest); } @@ -91,7 +90,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators } } - copyDest = current; + copyDest = current; origSource = sources[copyDest]; copySource = locations[origSource]; @@ -186,10 +185,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void AddSplitFill(LiveInterval left, LiveInterval right, OperandType type) { - if (_fillQueue == null) - { - _fillQueue = new Queue(); - } + _fillQueue ??= new Queue(); Operand register = GetRegister(right.Register, type); Operand offset = Const(left.SpillOffset); @@ -201,10 +197,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void AddSplitSpill(LiveInterval left, LiveInterval right, OperandType type) { - if (_spillQueue == null) - { - _spillQueue = new Queue(); - } + _spillQueue ??= new Queue(); Operand offset = Const(right.SpillOffset); Operand register = GetRegister(left.Register, type); @@ -216,10 +209,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void AddSplitCopy(LiveInterval left, LiveInterval right, OperandType type) { - if (_parallelCopy == null) - { - _parallelCopy = new ParallelCopy(); - } + _parallelCopy ??= new ParallelCopy(); _parallelCopy.AddCopy(right.Register, left.Register, type); @@ -228,7 +218,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public Operation[] Sequence() { - List sequence = new List(); + List sequence = new(); if (_spillQueue != null) { @@ -256,4 +246,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators return Register(reg.Index, reg.Type, type); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs index 25952c77..5f1d6ce8 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs @@ -20,7 +20,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public BlockInfo(bool hasCall, int intFixedRegisters, int vecFixedRegisters) { - HasCall = hasCall; + HasCall = hasCall; IntFixedRegisters = intFixedRegisters; VecFixedRegisters = vecFixedRegisters; } @@ -39,7 +39,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private int _first; private int _last; - public bool IsBlockLocal => _first == _last; + public readonly bool IsBlockLocal => _first == _last; public LocalInfo(OperandType type, int uses, int blkIndex) { @@ -53,7 +53,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators SpillOffset = default; _first = -1; - _last = -1; + _last = -1; SetBlockIndex(blkIndex); } @@ -348,17 +348,17 @@ namespace ARMeilleure.CodeGen.RegisterAllocators if (dest.Type.IsInteger()) { intLocalFreeRegisters &= ~(1 << selectedReg); - intUsedRegisters |= 1 << selectedReg; + intUsedRegisters |= 1 << selectedReg; } else { vecLocalFreeRegisters &= ~(1 << selectedReg); - vecUsedRegisters |= 1 << selectedReg; + vecUsedRegisters |= 1 << selectedReg; } } else { - info.Register = default; + info.Register = default; info.SpillOffset = Const(stackAlloc.Allocate(dest.Type.GetSizeInBytes())); } } @@ -382,7 +382,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators : GetSpillTemp(dest, vecSpillTempRegisters, ref vecLocalAsg); info.Sequence = sequence; - info.Temp = temp; + info.Temp = temp; } dest = temp; @@ -408,7 +408,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private static int SelectSpillTemps(int mask0, int mask1) { int selection = 0; - int count = 0; + int count = 0; while (count < MaxIROperands && mask0 != 0) { @@ -451,4 +451,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators return local.AssignmentsCount + local.UsesCount; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs index 8f236c25..7d4ce2ea 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators StackAllocator stackAlloc, RegisterMasks regMasks); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs index d80157af..f156e088 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs @@ -14,7 +14,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators // http://www.christianwimmer.at/Publications/Wimmer04a/Wimmer04a.pdf class LinearScanAllocator : IRegisterAllocator { - private const int InstructionGap = 2; + private const int InstructionGap = 2; private const int InstructionGapMask = InstructionGap - 1; private HashSet _blockEdges; @@ -33,7 +33,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public StackAllocator StackAlloc { get; } - public BitMap Active { get; } + public BitMap Active { get; } public BitMap Inactive { get; } public int IntUsedRegisters { get; set; } @@ -47,9 +47,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public AllocationContext(StackAllocator stackAlloc, RegisterMasks masks, int intervalsCount) { StackAlloc = stackAlloc; - Masks = masks; + Masks = masks; - Active = new BitMap(Allocators.Default, intervalsCount); + Active = new BitMap(Allocators.Default, intervalsCount); Inactive = new BitMap(Allocators.Default, intervalsCount); PopulateFreePositions(RegisterType.Integer, out _intFreePositions, out _intFreePositionsCount); @@ -443,7 +443,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators if (highest < current) { - highest = current; + highest = current; selected = index; if (current == int.MaxValue) @@ -485,9 +485,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void SplitAndSpillOverlappingInterval( AllocationContext context, - LiveInterval current, - LiveInterval interval, - int registersCount) + LiveInterval current, + LiveInterval interval, + int registersCount) { // If there's a next use after the start of the current interval, // we need to split the spilled interval twice, and re-insert it @@ -530,8 +530,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void InsertInterval(LiveInterval interval, int registersCount) { Debug.Assert(interval.UsesCount != 0, "Trying to insert a interval without uses."); - Debug.Assert(!interval.IsEmpty, "Trying to insert a empty interval."); - Debug.Assert(!interval.IsSpilled, "Trying to insert a spilled interval."); + Debug.Assert(!interval.IsEmpty, "Trying to insert a empty interval."); + Debug.Assert(!interval.IsSpilled, "Trying to insert a spilled interval."); int startIndex = registersCount * 2; @@ -545,9 +545,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators _intervals.Insert(insertIndex, interval); } - private void Spill(AllocationContext context, LiveInterval interval) + private static void Spill(AllocationContext context, LiveInterval interval) { - Debug.Assert(!interval.IsFixed, "Trying to spill a fixed interval."); + Debug.Assert(!interval.IsFixed, "Trying to spill a fixed interval."); Debug.Assert(interval.UsesCount == 0, "Trying to spill a interval with uses."); // We first check if any of the siblings were spilled, if so we can reuse @@ -561,7 +561,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void InsertSplitCopies() { - Dictionary copyResolvers = new Dictionary(); + Dictionary copyResolvers = new(); CopyResolver GetCopyResolver(int position) { @@ -668,18 +668,15 @@ namespace ARMeilleure.CodeGen.RegisterAllocators continue; } - int lEnd = _blockRanges[block.Index].End - 1; + int lEnd = _blockRanges[block.Index].End - 1; int rStart = _blockRanges[succIndex].Start; - LiveInterval left = interval.GetSplitChild(lEnd); + LiveInterval left = interval.GetSplitChild(lEnd); LiveInterval right = interval.GetSplitChild(rStart); if (left != default && right != default && left != right) { - if (copyResolver == null) - { - copyResolver = new CopyResolver(); - } + copyResolver ??= new CopyResolver(); copyResolver.AddSplit(left, right); } @@ -856,14 +853,14 @@ namespace ARMeilleure.CodeGen.RegisterAllocators int mapSize = _intervals.Count; - BitMap[] blkLiveGen = new BitMap[cfg.Blocks.Count]; + BitMap[] blkLiveGen = new BitMap[cfg.Blocks.Count]; BitMap[] blkLiveKill = new BitMap[cfg.Blocks.Count]; // Compute local live sets. for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext) { - BitMap liveGen = new BitMap(Allocators.Default, mapSize); - BitMap liveKill = new BitMap(Allocators.Default, mapSize); + BitMap liveGen = new(Allocators.Default, mapSize); + BitMap liveKill = new(Allocators.Default, mapSize); for (Operation node = block.Operations.First; node != default; node = node.ListNext) { @@ -910,17 +907,17 @@ namespace ARMeilleure.CodeGen.RegisterAllocators } } - blkLiveGen [block.Index] = liveGen; + blkLiveGen[block.Index] = liveGen; blkLiveKill[block.Index] = liveKill; } // Compute global live sets. - BitMap[] blkLiveIn = new BitMap[cfg.Blocks.Count]; + BitMap[] blkLiveIn = new BitMap[cfg.Blocks.Count]; BitMap[] blkLiveOut = new BitMap[cfg.Blocks.Count]; for (int index = 0; index < cfg.Blocks.Count; index++) { - blkLiveIn [index] = new BitMap(Allocators.Default, mapSize); + blkLiveIn[index] = new BitMap(Allocators.Default, mapSize); blkLiveOut[index] = new BitMap(Allocators.Default, mapSize); } @@ -945,9 +942,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators BitMap liveIn = blkLiveIn[block.Index]; - liveIn.Set (liveOut); + liveIn.Set(liveOut); liveIn.Clear(blkLiveKill[block.Index]); - liveIn.Set (blkLiveGen [block.Index]); + liveIn.Set(blkLiveGen[block.Index]); } } while (modified); @@ -969,7 +966,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators int instCount = Math.Max(block.Operations.Count, 1); int blockStart = operationPos - instCount * InstructionGap; - int blockEnd = operationPos; + int blockEnd = operationPos; _blockRanges[block.Index] = new LiveRange(blockStart, blockEnd); @@ -1061,7 +1058,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { int regIndex = BitOperations.TrailingZeroCount(mask); - Register callerSavedReg = new Register(regIndex, regType); + Register callerSavedReg = new(regIndex, regType); LiveInterval interval = _intervals[GetRegisterId(callerSavedReg)]; @@ -1098,4 +1095,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators kind == OperandKind.Register; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs index d739ad28..333d3951 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs @@ -240,8 +240,10 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public LiveInterval Split(int position) { - LiveInterval result = new(Local, Parent); - result.End = End; + LiveInterval result = new(Local, Parent) + { + End = End, + }; LiveRange prev = PrevRange; LiveRange curr = CurrRange; @@ -393,4 +395,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators return string.Join(", ", GetRanges()); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs index 06b979ea..d999d767 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs @@ -8,8 +8,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private int _count; private int _capacity; - public int Count => _count; - public Span Span => new(_items, _count); + public readonly int Count => _count; + public readonly Span Span => new(_items, _count); public void Add(LiveInterval interval) { @@ -37,4 +37,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators _count++; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs index e38b5190..412d597e 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs @@ -71,4 +71,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators return $"[{Start}, {End})"; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs index bc948f95..e6972cf0 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs @@ -5,8 +5,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { readonly struct RegisterMasks { - public int IntAvailableRegisters { get; } - public int VecAvailableRegisters { get; } + public int IntAvailableRegisters { get; } + public int VecAvailableRegisters { get; } public int IntCallerSavedRegisters { get; } public int VecCallerSavedRegisters { get; } public int IntCalleeSavedRegisters { get; } @@ -22,13 +22,13 @@ namespace ARMeilleure.CodeGen.RegisterAllocators int vecCalleeSavedRegisters, int registersCount) { - IntAvailableRegisters = intAvailableRegisters; - VecAvailableRegisters = vecAvailableRegisters; + IntAvailableRegisters = intAvailableRegisters; + VecAvailableRegisters = vecAvailableRegisters; IntCallerSavedRegisters = intCallerSavedRegisters; VecCallerSavedRegisters = vecCallerSavedRegisters; IntCalleeSavedRegisters = intCalleeSavedRegisters; VecCalleeSavedRegisters = vecCalleeSavedRegisters; - RegistersCount = registersCount; + RegistersCount = registersCount; } public int GetAvailableRegisters(RegisterType type) @@ -47,4 +47,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs index 038312fe..13995bc8 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs @@ -22,4 +22,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators return offset; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs index c89f0854..a945eccf 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs @@ -6,15 +6,15 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { private int* _items; private int _capacity; - private int _count; - public int Count => _count; - public int FirstUse => _count > 0 ? _items[_count - 1] : LiveInterval.NotFound; - public Span Span => new(_items, _count); + public int Count { get; private set; } + + public readonly int FirstUse => Count > 0 ? _items[Count - 1] : LiveInterval.NotFound; + public readonly Span Span => new(_items, Count); public void Add(int position) { - if (_count + 1 > _capacity) + if (Count + 1 > _capacity) { var oldSpan = Span; @@ -28,7 +28,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators // Use positions are usually inserted in descending order, so inserting in descending order is faster, // since the number of half exchanges is reduced. - int i = _count - 1; + int i = Count - 1; while (i >= 0 && _items[i] < position) { @@ -36,19 +36,19 @@ namespace ARMeilleure.CodeGen.RegisterAllocators } _items[i + 1] = position; - _count++; + Count++; } - public int NextUse(int position) + public readonly int NextUse(int position) { int index = NextUseIndex(position); return index != LiveInterval.NotFound ? _items[index] : LiveInterval.NotFound; } - public int NextUseIndex(int position) + public readonly int NextUseIndex(int position) { - int i = _count - 1; + int i = Count - 1; if (i == -1 || position > _items[0]) { @@ -69,16 +69,18 @@ namespace ARMeilleure.CodeGen.RegisterAllocators // Since the list is in descending order, the new split list takes the front of the list and the current // list takes the back of the list. - UseList result = new(); - result._count = index + 1; - result._capacity = result._count; + UseList result = new() + { + Count = index + 1, + }; + result._capacity = result.Count; result._items = _items; - _count = _count - result._count; - _capacity = _count; - _items = _items + result._count; + Count -= result.Count; + _capacity = Count; + _items += result.Count; return result; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs b/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs index 3d0bc21d..127b8423 100644 --- a/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs +++ b/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.CodeGen.Unwinding PrologSize = prologSize; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs b/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs index 4a8288a2..2045019a 100644 --- a/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs +++ b/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.CodeGen.Unwinding { enum UnwindPseudoOp { - PushReg = 0, - SetFrame = 1, + PushReg = 0, + SetFrame = 1, AllocStack = 2, - SaveReg = 3, - SaveXmm128 = 4 + SaveReg = 3, + SaveXmm128 = 4, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs b/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs index fd8ea402..507ace59 100644 --- a/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs +++ b/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs @@ -17,4 +17,4 @@ namespace ARMeilleure.CodeGen.Unwinding StackOffsetOrAllocSize = stackOffsetOrAllocSize; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/Assembler.cs b/src/ARMeilleure/CodeGen/X86/Assembler.cs index 67736a31..55bf0724 100644 --- a/src/ARMeilleure/CodeGen/X86/Assembler.cs +++ b/src/ARMeilleure/CodeGen/X86/Assembler.cs @@ -15,7 +15,7 @@ namespace ARMeilleure.CodeGen.X86 private const int OpModRMBits = 24; - private const byte RexPrefix = 0x40; + private const byte RexPrefix = 0x40; private const byte RexWPrefix = 0x48; private const byte LockPrefix = 0xf0; @@ -799,7 +799,7 @@ namespace ARMeilleure.CodeGen.X86 { JumpIndex = _jumps.Count - 1, Position = (int)_stream.Position, - Symbol = source.Symbol + Symbol = source.Symbol, }); } @@ -959,7 +959,7 @@ namespace ARMeilleure.CodeGen.X86 } } - bool needsSibByte = false; + bool needsSibByte = false; bool needsDisplacement = false; int sib = 0; @@ -971,7 +971,7 @@ namespace ARMeilleure.CodeGen.X86 X86Register baseRegLow = (X86Register)(baseReg.Index & 0b111); - needsSibByte = memOp.Index != default || baseRegLow == X86Register.Rsp; + needsSibByte = memOp.Index != default || baseRegLow == X86Register.Rsp; needsDisplacement = memOp.Displacement != 0 || baseRegLow == X86Register.Rbp; if (needsDisplacement) @@ -1049,7 +1049,7 @@ namespace ARMeilleure.CodeGen.X86 InstructionFlags.Prefix66 => 1, InstructionFlags.PrefixF3 => 2, InstructionFlags.PrefixF2 => 3, - _ => 0 + _ => 0, }; if (src1 != default) @@ -1081,11 +1081,19 @@ namespace ARMeilleure.CodeGen.X86 switch (opCodeHigh) { - case 0xf: vexByte1 |= 1; break; - case 0xf38: vexByte1 |= 2; break; - case 0xf3a: vexByte1 |= 3; break; + case 0xf: + vexByte1 |= 1; + break; + case 0xf38: + vexByte1 |= 2; + break; + case 0xf3a: + vexByte1 |= 3; + break; - default: Debug.Assert(false, $"Failed to VEX encode opcode 0x{opCode:X}."); break; + default: + Debug.Assert(false, $"Failed to VEX encode opcode 0x{opCode:X}."); + break; } vexByte2 |= (rexPrefix & 8) << 4; @@ -1191,11 +1199,19 @@ namespace ARMeilleure.CodeGen.X86 switch ((ushort)(opCode >> 8)) { - case 0xf00: mm = 0b01; break; - case 0xf38: mm = 0b10; break; - case 0xf3a: mm = 0b11; break; + case 0xf00: + mm = 0b01; + break; + case 0xf38: + mm = 0b10; + break; + case 0xf3a: + mm = 0b11; + break; - default: Debug.Fail($"Failed to EVEX encode opcode 0x{opCode:X}."); break; + default: + Debug.Fail($"Failed to EVEX encode opcode 0x{opCode:X}."); + break; } WriteByte( @@ -1217,7 +1233,7 @@ namespace ARMeilleure.CodeGen.X86 InstructionFlags.Prefix66 => 0b01, InstructionFlags.PrefixF3 => 0b10, InstructionFlags.PrefixF2 => 0b11, - _ => 0 + _ => 0, }; WriteByte( (byte)( @@ -1233,11 +1249,19 @@ namespace ARMeilleure.CodeGen.X86 byte ll = 0b00; switch (registerWidth) { - case 128: ll = 0b00; break; - case 256: ll = 0b01; break; - case 512: ll = 0b10; break; + case 128: + ll = 0b00; + break; + case 256: + ll = 0b01; + break; + case 512: + ll = 0b10; + break; - default: Debug.Fail($"Invalid EVEX vector register width {registerWidth}."); break; + default: + Debug.Fail($"Invalid EVEX vector register width {registerWidth}."); + break; } // Embedded broadcast in the case of a memory operand bool bcast = broadcast; @@ -1315,10 +1339,7 @@ namespace ARMeilleure.CodeGen.X86 ref Jump jump = ref jumps[i]; // If jump target not resolved yet, resolve it. - if (jump.JumpTarget == null) - { - jump.JumpTarget = _labels[jump.JumpLabel]; - } + jump.JumpTarget ??= _labels[jump.JumpLabel]; long jumpTarget = jump.JumpTarget.Value; long offset = jumpTarget - jump.JumpPosition; @@ -1556,4 +1577,4 @@ namespace ARMeilleure.CodeGen.X86 _stream.WriteByte((byte)(value >> 56)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs b/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs index e6a2ff07..e4114a33 100644 --- a/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs +++ b/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs @@ -1,4 +1,5 @@ using System; +using System.Diagnostics.CodeAnalysis; namespace ARMeilleure.CodeGen.X86 { @@ -12,47 +13,48 @@ namespace ARMeilleure.CodeGen.X86 private const int BadOp = 0; [Flags] + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] private enum InstructionFlags { - None = 0, - RegOnly = 1 << 0, - Reg8Src = 1 << 1, + None = 0, + RegOnly = 1 << 0, + Reg8Src = 1 << 1, Reg8Dest = 1 << 2, - RexW = 1 << 3, - Vex = 1 << 4, - Evex = 1 << 5, + RexW = 1 << 3, + Vex = 1 << 4, + Evex = 1 << 5, - PrefixBit = 16, + PrefixBit = 16, PrefixMask = 7 << PrefixBit, - Prefix66 = 1 << PrefixBit, - PrefixF3 = 2 << PrefixBit, - PrefixF2 = 4 << PrefixBit + Prefix66 = 1 << PrefixBit, + PrefixF3 = 2 << PrefixBit, + PrefixF2 = 4 << PrefixBit, } private readonly struct InstructionInfo { - public int OpRMR { get; } - public int OpRMImm8 { get; } + public int OpRMR { get; } + public int OpRMImm8 { get; } public int OpRMImm32 { get; } - public int OpRImm64 { get; } - public int OpRRM { get; } + public int OpRImm64 { get; } + public int OpRRM { get; } public InstructionFlags Flags { get; } public InstructionInfo( - int opRMR, - int opRMImm8, - int opRMImm32, - int opRImm64, - int opRRM, + int opRMR, + int opRMImm8, + int opRMImm32, + int opRImm64, + int opRRM, InstructionFlags flags) { - OpRMR = opRMR; - OpRMImm8 = opRMImm8; + OpRMR = opRMR; + OpRMImm8 = opRMImm8; OpRMImm32 = opRMImm32; - OpRImm64 = opRImm64; - OpRRM = opRRM; - Flags = flags; + OpRImm64 = opRImm64; + OpRRM = opRRM; + Flags = flags; } } @@ -62,6 +64,7 @@ namespace ARMeilleure.CodeGen.X86 { _instTable = new InstructionInfo[(int)X86Instruction.Count]; +#pragma warning disable IDE0055 // Disable formatting // Name RM/R RM/I8 RM/I32 R/I64 R/RM Flags Add(X86Instruction.Add, new InstructionInfo(0x00000001, 0x00000083, 0x00000081, BadOp, 0x00000003, InstructionFlags.None)); Add(X86Instruction.Addpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f58, InstructionFlags.Vex | InstructionFlags.Prefix66)); @@ -285,6 +288,7 @@ namespace ARMeilleure.CodeGen.X86 Add(X86Instruction.Xor, new InstructionInfo(0x00000031, 0x06000083, 0x06000081, BadOp, 0x00000033, InstructionFlags.None)); Add(X86Instruction.Xorpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f57, InstructionFlags.Vex | InstructionFlags.Prefix66)); Add(X86Instruction.Xorps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f57, InstructionFlags.Vex)); +#pragma warning restore IDE0055 static void Add(X86Instruction inst, in InstructionInfo info) { diff --git a/src/ARMeilleure/CodeGen/X86/CallConvName.cs b/src/ARMeilleure/CodeGen/X86/CallConvName.cs index be367628..6208da1e 100644 --- a/src/ARMeilleure/CodeGen/X86/CallConvName.cs +++ b/src/ARMeilleure/CodeGen/X86/CallConvName.cs @@ -3,6 +3,6 @@ namespace ARMeilleure.CodeGen.X86 enum CallConvName { SystemV, - Windows + Windows, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/CallingConvention.cs b/src/ARMeilleure/CodeGen/X86/CallingConvention.cs index 953fef5b..8433aaea 100644 --- a/src/ARMeilleure/CodeGen/X86/CallingConvention.cs +++ b/src/ARMeilleure/CodeGen/X86/CallingConvention.cs @@ -20,6 +20,7 @@ namespace ARMeilleure.CodeGen.X86 { if (GetCurrentCallConv() == CallConvName.Windows) { +#pragma warning disable IDE0055 // Disable formatting return (1 << (int)X86Register.Rax) | (1 << (int)X86Register.Rcx) | (1 << (int)X86Register.Rdx) | @@ -39,6 +40,7 @@ namespace ARMeilleure.CodeGen.X86 (1 << (int)X86Register.R9) | (1 << (int)X86Register.R10) | (1 << (int)X86Register.R11); +#pragma warning restore IDE0055 } } @@ -90,22 +92,32 @@ namespace ARMeilleure.CodeGen.X86 { switch (index) { - case 0: return X86Register.Rcx; - case 1: return X86Register.Rdx; - case 2: return X86Register.R8; - case 3: return X86Register.R9; + case 0: + return X86Register.Rcx; + case 1: + return X86Register.Rdx; + case 2: + return X86Register.R8; + case 3: + return X86Register.R9; } } else /* if (GetCurrentCallConv() == CallConvName.SystemV) */ { switch (index) { - case 0: return X86Register.Rdi; - case 1: return X86Register.Rsi; - case 2: return X86Register.Rdx; - case 3: return X86Register.Rcx; - case 4: return X86Register.R8; - case 5: return X86Register.R9; + case 0: + return X86Register.Rdi; + case 1: + return X86Register.Rsi; + case 2: + return X86Register.Rdx; + case 3: + return X86Register.Rcx; + case 4: + return X86Register.R8; + case 5: + return X86Register.R9; } } @@ -155,4 +167,4 @@ namespace ARMeilleure.CodeGen.X86 : CallConvName.SystemV; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs b/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs index 89948724..d4d4c205 100644 --- a/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs +++ b/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs @@ -30,7 +30,7 @@ namespace ARMeilleure.CodeGen.X86 Assembler = new Assembler(_stream, relocatable); CallArgsRegionSize = GetCallArgsRegionSize(allocResult, maxCallArgs, out int xmmSaveRegionSize); - XmmSaveRegionSize = xmmSaveRegionSize; + XmmSaveRegionSize = xmmSaveRegionSize; } private static int GetCallArgsRegionSize(AllocationResult allocResult, int maxCallArgs, out int xmmSaveRegionSize) @@ -102,4 +102,4 @@ namespace ARMeilleure.CodeGen.X86 return label; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs b/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs index e7179b51..3cab0b6c 100644 --- a/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs +++ b/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs @@ -17,7 +17,7 @@ namespace ARMeilleure.CodeGen.X86 static class CodeGenerator { private const int RegistersCount = 16; - private const int PageSize = 0x1000; + private const int PageSize = 0x1000; private const int StackGuardSize = 0x2000; private static readonly Action[] _instTable; @@ -26,6 +26,7 @@ namespace ARMeilleure.CodeGen.X86 { _instTable = new Action[EnumUtils.GetCount(typeof(Instruction))]; +#pragma warning disable IDE0055 // Disable formatting Add(Instruction.Add, GenerateAdd); Add(Instruction.BitwiseAnd, GenerateBitwiseAnd); Add(Instruction.BitwiseExclusiveOr, GenerateBitwiseExclusiveOr); @@ -85,6 +86,7 @@ namespace ARMeilleure.CodeGen.X86 Add(Instruction.ZeroExtend16, GenerateZeroExtend16); Add(Instruction.ZeroExtend32, GenerateZeroExtend32); Add(Instruction.ZeroExtend8, GenerateZeroExtend8); +#pragma warning restore IDE0055 static void Add(Instruction inst, Action func) { @@ -203,290 +205,290 @@ namespace ARMeilleure.CodeGen.X86 switch (info.Type) { case IntrinsicType.Comis_: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - - switch (operation.Intrinsic) - { - case Intrinsic.X86Comisdeq: - context.Assembler.Comisd(src1, src2); - context.Assembler.Setcc(dest, X86Condition.Equal); - break; - - case Intrinsic.X86Comisdge: - context.Assembler.Comisd(src1, src2); - context.Assembler.Setcc(dest, X86Condition.AboveOrEqual); - break; - - case Intrinsic.X86Comisdlt: - context.Assembler.Comisd(src1, src2); - context.Assembler.Setcc(dest, X86Condition.Below); - break; - - case Intrinsic.X86Comisseq: - context.Assembler.Comiss(src1, src2); - context.Assembler.Setcc(dest, X86Condition.Equal); - break; - - case Intrinsic.X86Comissge: - context.Assembler.Comiss(src1, src2); - context.Assembler.Setcc(dest, X86Condition.AboveOrEqual); - break; - - case Intrinsic.X86Comisslt: - context.Assembler.Comiss(src1, src2); - context.Assembler.Setcc(dest, X86Condition.Below); - break; - } - - context.Assembler.Movzx8(dest, dest, OperandType.I32); - - break; - } - - case IntrinsicType.Mxcsr: - { - Operand offset = operation.GetSource(0); - - Debug.Assert(offset.Kind == OperandKind.Constant); - Debug.Assert(offset.Type == OperandType.I32); - - int offs = offset.AsInt32() + context.CallArgsRegionSize; - - Operand rsp = Register(X86Register.Rsp); - Operand memOp = MemoryOp(OperandType.I32, rsp, default, Multiplier.x1, offs); - - Debug.Assert(HardwareCapabilities.SupportsSse || HardwareCapabilities.SupportsVexEncoding); - - if (operation.Intrinsic == Intrinsic.X86Ldmxcsr) - { - Operand bits = operation.GetSource(1); - Debug.Assert(bits.Type == OperandType.I32); - - context.Assembler.Mov(memOp, bits, OperandType.I32); - context.Assembler.Ldmxcsr(memOp); - } - else if (operation.Intrinsic == Intrinsic.X86Stmxcsr) { Operand dest = operation.Destination; - Debug.Assert(dest.Type == OperandType.I32); + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); - context.Assembler.Stmxcsr(memOp); - context.Assembler.Mov(dest, memOp, OperandType.I32); + switch (operation.Intrinsic) + { + case Intrinsic.X86Comisdeq: + context.Assembler.Comisd(src1, src2); + context.Assembler.Setcc(dest, X86Condition.Equal); + break; + + case Intrinsic.X86Comisdge: + context.Assembler.Comisd(src1, src2); + context.Assembler.Setcc(dest, X86Condition.AboveOrEqual); + break; + + case Intrinsic.X86Comisdlt: + context.Assembler.Comisd(src1, src2); + context.Assembler.Setcc(dest, X86Condition.Below); + break; + + case Intrinsic.X86Comisseq: + context.Assembler.Comiss(src1, src2); + context.Assembler.Setcc(dest, X86Condition.Equal); + break; + + case Intrinsic.X86Comissge: + context.Assembler.Comiss(src1, src2); + context.Assembler.Setcc(dest, X86Condition.AboveOrEqual); + break; + + case Intrinsic.X86Comisslt: + context.Assembler.Comiss(src1, src2); + context.Assembler.Setcc(dest, X86Condition.Below); + break; + } + + context.Assembler.Movzx8(dest, dest, OperandType.I32); + + break; } - break; - } + case IntrinsicType.Mxcsr: + { + Operand offset = operation.GetSource(0); + + Debug.Assert(offset.Kind == OperandKind.Constant); + Debug.Assert(offset.Type == OperandType.I32); + + int offs = offset.AsInt32() + context.CallArgsRegionSize; + + Operand rsp = Register(X86Register.Rsp); + Operand memOp = MemoryOp(OperandType.I32, rsp, default, Multiplier.x1, offs); + + Debug.Assert(HardwareCapabilities.SupportsSse || HardwareCapabilities.SupportsVexEncoding); + + if (operation.Intrinsic == Intrinsic.X86Ldmxcsr) + { + Operand bits = operation.GetSource(1); + Debug.Assert(bits.Type == OperandType.I32); + + context.Assembler.Mov(memOp, bits, OperandType.I32); + context.Assembler.Ldmxcsr(memOp); + } + else if (operation.Intrinsic == Intrinsic.X86Stmxcsr) + { + Operand dest = operation.Destination; + Debug.Assert(dest.Type == OperandType.I32); + + context.Assembler.Stmxcsr(memOp); + context.Assembler.Mov(dest, memOp, OperandType.I32); + } + + break; + } case IntrinsicType.PopCount: - { - Operand dest = operation.Destination; - Operand source = operation.GetSource(0); + { + Operand dest = operation.Destination; + Operand source = operation.GetSource(0); - EnsureSameType(dest, source); + EnsureSameType(dest, source); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger()); - context.Assembler.Popcnt(dest, source, dest.Type); + context.Assembler.Popcnt(dest, source, dest.Type); - break; - } + break; + } case IntrinsicType.Unary: - { - Operand dest = operation.Destination; - Operand source = operation.GetSource(0); + { + Operand dest = operation.Destination; + Operand source = operation.GetSource(0); - EnsureSameType(dest, source); + EnsureSameType(dest, source); - Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger()); - context.Assembler.WriteInstruction(info.Inst, dest, source); + context.Assembler.WriteInstruction(info.Inst, dest, source); - break; - } + break; + } case IntrinsicType.UnaryToGpr: - { - Operand dest = operation.Destination; - Operand source = operation.GetSource(0); - - Debug.Assert(dest.Type.IsInteger() && !source.Type.IsInteger()); - - if (operation.Intrinsic == Intrinsic.X86Cvtsi2si) { - if (dest.Type == OperandType.I32) - { - context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32(__m128i a) - } - else /* if (dest.Type == OperandType.I64) */ - { - context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64(__m128i a) - } - } - else - { - context.Assembler.WriteInstruction(info.Inst, dest, source, dest.Type); - } + Operand dest = operation.Destination; + Operand source = operation.GetSource(0); - break; - } + Debug.Assert(dest.Type.IsInteger() && !source.Type.IsInteger()); + + if (operation.Intrinsic == Intrinsic.X86Cvtsi2si) + { + if (dest.Type == OperandType.I32) + { + context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32(__m128i a) + } + else /* if (dest.Type == OperandType.I64) */ + { + context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64(__m128i a) + } + } + else + { + context.Assembler.WriteInstruction(info.Inst, dest, source, dest.Type); + } + + break; + } case IntrinsicType.Binary: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - - EnsureSameType(dest, src1); - - if (!HardwareCapabilities.SupportsVexEncoding) { - EnsureSameReg(dest, src1); - } + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); - Debug.Assert(!dest.Type.IsInteger()); - Debug.Assert(!src2.Type.IsInteger() || src2.Kind == OperandKind.Constant); + EnsureSameType(dest, src1); - context.Assembler.WriteInstruction(info.Inst, dest, src1, src2); + if (!HardwareCapabilities.SupportsVexEncoding) + { + EnsureSameReg(dest, src1); + } - break; - } - - case IntrinsicType.BinaryGpr: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - - EnsureSameType(dest, src1); - - if (!HardwareCapabilities.SupportsVexEncoding) - { - EnsureSameReg(dest, src1); - } - - Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger()); - - context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type); - - break; - } - - case IntrinsicType.Crc32: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - - EnsureSameReg(dest, src1); - - Debug.Assert(dest.Type.IsInteger() && src1.Type.IsInteger() && src2.Type.IsInteger()); - - context.Assembler.WriteInstruction(info.Inst, dest, src2, dest.Type); - - break; - } - - case IntrinsicType.BinaryImm: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - - EnsureSameType(dest, src1); - - if (!HardwareCapabilities.SupportsVexEncoding) - { - EnsureSameReg(dest, src1); - } - - Debug.Assert(!dest.Type.IsInteger() && src2.Kind == OperandKind.Constant); - - context.Assembler.WriteInstruction(info.Inst, dest, src1, src2.AsByte()); - - break; - } - - case IntrinsicType.Ternary: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - Operand src3 = operation.GetSource(2); - - EnsureSameType(dest, src1, src2, src3); - - Debug.Assert(!dest.Type.IsInteger()); - - if (info.Inst == X86Instruction.Blendvpd && HardwareCapabilities.SupportsVexEncoding) - { - context.Assembler.WriteInstruction(X86Instruction.Vblendvpd, dest, src1, src2, src3); - } - else if (info.Inst == X86Instruction.Blendvps && HardwareCapabilities.SupportsVexEncoding) - { - context.Assembler.WriteInstruction(X86Instruction.Vblendvps, dest, src1, src2, src3); - } - else if (info.Inst == X86Instruction.Pblendvb && HardwareCapabilities.SupportsVexEncoding) - { - context.Assembler.WriteInstruction(X86Instruction.Vpblendvb, dest, src1, src2, src3); - } - else - { - EnsureSameReg(dest, src1); - - Debug.Assert(src3.GetRegister().Index == 0); + Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(!src2.Type.IsInteger() || src2.Kind == OperandKind.Constant); context.Assembler.WriteInstruction(info.Inst, dest, src1, src2); + + break; } - break; - } + case IntrinsicType.BinaryGpr: + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + + EnsureSameType(dest, src1); + + if (!HardwareCapabilities.SupportsVexEncoding) + { + EnsureSameReg(dest, src1); + } + + Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger()); + + context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type); + + break; + } + + case IntrinsicType.Crc32: + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + + EnsureSameReg(dest, src1); + + Debug.Assert(dest.Type.IsInteger() && src1.Type.IsInteger() && src2.Type.IsInteger()); + + context.Assembler.WriteInstruction(info.Inst, dest, src2, dest.Type); + + break; + } + + case IntrinsicType.BinaryImm: + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + + EnsureSameType(dest, src1); + + if (!HardwareCapabilities.SupportsVexEncoding) + { + EnsureSameReg(dest, src1); + } + + Debug.Assert(!dest.Type.IsInteger() && src2.Kind == OperandKind.Constant); + + context.Assembler.WriteInstruction(info.Inst, dest, src1, src2.AsByte()); + + break; + } + + case IntrinsicType.Ternary: + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + Operand src3 = operation.GetSource(2); + + EnsureSameType(dest, src1, src2, src3); + + Debug.Assert(!dest.Type.IsInteger()); + + if (info.Inst == X86Instruction.Blendvpd && HardwareCapabilities.SupportsVexEncoding) + { + context.Assembler.WriteInstruction(X86Instruction.Vblendvpd, dest, src1, src2, src3); + } + else if (info.Inst == X86Instruction.Blendvps && HardwareCapabilities.SupportsVexEncoding) + { + context.Assembler.WriteInstruction(X86Instruction.Vblendvps, dest, src1, src2, src3); + } + else if (info.Inst == X86Instruction.Pblendvb && HardwareCapabilities.SupportsVexEncoding) + { + context.Assembler.WriteInstruction(X86Instruction.Vpblendvb, dest, src1, src2, src3); + } + else + { + EnsureSameReg(dest, src1); + + Debug.Assert(src3.GetRegister().Index == 0); + + context.Assembler.WriteInstruction(info.Inst, dest, src1, src2); + } + + break; + } case IntrinsicType.TernaryImm: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - Operand src3 = operation.GetSource(2); - - EnsureSameType(dest, src1, src2); - - if (!HardwareCapabilities.SupportsVexEncoding) { - EnsureSameReg(dest, src1); + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + Operand src3 = operation.GetSource(2); + + EnsureSameType(dest, src1, src2); + + if (!HardwareCapabilities.SupportsVexEncoding) + { + EnsureSameReg(dest, src1); + } + + Debug.Assert(!dest.Type.IsInteger() && src3.Kind == OperandKind.Constant); + + context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src3.AsByte()); + + break; } - Debug.Assert(!dest.Type.IsInteger() && src3.Kind == OperandKind.Constant); - - context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src3.AsByte()); - - break; - } - case IntrinsicType.Fma: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - Operand src3 = operation.GetSource(2); + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + Operand src3 = operation.GetSource(2); - Debug.Assert(HardwareCapabilities.SupportsVexEncoding); + Debug.Assert(HardwareCapabilities.SupportsVexEncoding); - Debug.Assert(dest.Kind == OperandKind.Register && src1.Kind == OperandKind.Register && src2.Kind == OperandKind.Register); - Debug.Assert(src3.Kind == OperandKind.Register || src3.Kind == OperandKind.Memory); + Debug.Assert(dest.Kind == OperandKind.Register && src1.Kind == OperandKind.Register && src2.Kind == OperandKind.Register); + Debug.Assert(src3.Kind == OperandKind.Register || src3.Kind == OperandKind.Memory); - EnsureSameType(dest, src1, src2, src3); - Debug.Assert(dest.Type == OperandType.V128); + EnsureSameType(dest, src1, src2, src3); + Debug.Assert(dest.Type == OperandType.V128); - Debug.Assert(dest.Value == src1.Value); + Debug.Assert(dest.Value == src1.Value); - context.Assembler.WriteInstruction(info.Inst, dest, src2, src3); + context.Assembler.WriteInstruction(info.Inst, dest, src2, src3); - break; - } + break; + } } } else @@ -592,7 +594,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateBitwiseNot(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -630,7 +632,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateByteSwap(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -761,19 +763,19 @@ namespace ARMeilleure.CodeGen.X86 Operand src2 = operation.GetSource(1); Operand src3 = operation.GetSource(2); - EnsureSameReg (dest, src3); + EnsureSameReg(dest, src3); EnsureSameType(dest, src2, src3); Debug.Assert(dest.Type.IsInteger()); Debug.Assert(src1.Type == OperandType.I32); - context.Assembler.Test (src1, src1, src1.Type); + context.Assembler.Test(src1, src1, src1.Type); context.Assembler.Cmovcc(dest, src2, dest.Type, X86Condition.NotEqual); } private static void GenerateConvertI64ToI32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.I32 && source.Type == OperandType.I64); @@ -783,7 +785,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateConvertToFP(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64); @@ -794,7 +796,7 @@ namespace ARMeilleure.CodeGen.X86 if (source.Type.IsInteger()) { - context.Assembler.Xorps (dest, dest, dest); + context.Assembler.Xorps(dest, dest, dest); context.Assembler.Cvtsi2ss(dest, dest, source, source.Type); } else /* if (source.Type == OperandType.FP64) */ @@ -810,7 +812,7 @@ namespace ARMeilleure.CodeGen.X86 if (source.Type.IsInteger()) { - context.Assembler.Xorps (dest, dest, dest); + context.Assembler.Xorps(dest, dest, dest); context.Assembler.Cvtsi2sd(dest, dest, source, source.Type); } else /* if (source.Type == OperandType.FP32) */ @@ -824,7 +826,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateCopy(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); EnsureSameType(dest, source); @@ -837,7 +839,7 @@ namespace ARMeilleure.CodeGen.X86 return; } - if (dest.Kind == OperandKind.Register && + if (dest.Kind == OperandKind.Register && source.Kind == OperandKind.Constant && source.Value == 0) { // Assemble "mov reg, 0" as "xor reg, reg" as the later is more efficient. @@ -855,7 +857,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateCountLeadingZeros(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); EnsureSameType(dest, source); @@ -888,9 +890,9 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateDivide(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand dividend = operation.GetSource(0); - Operand divisor = operation.GetSource(1); + Operand divisor = operation.GetSource(1); if (!dest.Type.IsInteger()) { @@ -938,7 +940,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateFill(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand offset = operation.GetSource(0); Debug.Assert(offset.Kind == OperandKind.Constant); @@ -954,7 +956,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateLoad(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = Memory(operation.GetSource(0), value.Type); GenerateLoad(context, address, value); @@ -962,7 +964,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateLoad16(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = Memory(operation.GetSource(0), value.Type); Debug.Assert(value.Type.IsInteger()); @@ -972,7 +974,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateLoad8(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = Memory(operation.GetSource(0), value.Type); Debug.Assert(value.Type.IsInteger()); @@ -1039,7 +1041,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateNegate(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -1102,7 +1104,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateSignExtend16(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1112,7 +1114,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateSignExtend32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1122,7 +1124,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateSignExtend8(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1158,7 +1160,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateStackAlloc(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand offset = operation.GetSource(0); Debug.Assert(offset.Kind == OperandKind.Constant); @@ -1174,7 +1176,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateStore(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = Memory(operation.GetSource(0), value.Type); GenerateStore(context, address, value); @@ -1182,7 +1184,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateStore16(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = Memory(operation.GetSource(0), value.Type); Debug.Assert(value.Type.IsInteger()); @@ -1192,7 +1194,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateStore8(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = Memory(operation.GetSource(0), value.Type); Debug.Assert(value.Type.IsInteger()); @@ -1231,7 +1233,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateVectorCreateScalar(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(!dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1278,7 +1280,7 @@ namespace ARMeilleure.CodeGen.X86 mask1 = BitUtils.RotateRight(mask1, 8 - index * 2, 8); context.Assembler.Pshufd(src1, src1, (byte)mask0); - context.Assembler.Movd (dest, src1); + context.Assembler.Movd(dest, src1); context.Assembler.Pshufd(src1, src1, (byte)mask1); } } @@ -1297,7 +1299,7 @@ namespace ARMeilleure.CodeGen.X86 const byte mask = 0b01_00_11_10; context.Assembler.Pshufd(src1, src1, mask); - context.Assembler.Movq (dest, src1); + context.Assembler.Movq(dest, src1); context.Assembler.Pshufd(src1, src1, mask); } } @@ -1308,7 +1310,7 @@ namespace ARMeilleure.CodeGen.X86 (index == 1 && dest.Type == OperandType.FP64)) { context.Assembler.Movhlps(dest, dest, src1); - context.Assembler.Movq (dest, dest); + context.Assembler.Movq(dest, dest); } else { @@ -1455,11 +1457,11 @@ namespace ARMeilleure.CodeGen.X86 int mask0 = 0b11_10_01_00; int mask1 = 0b11_10_01_00; - mask0 = BitUtils.RotateRight(mask0, index * 2, 8); + mask0 = BitUtils.RotateRight(mask0, index * 2, 8); mask1 = BitUtils.RotateRight(mask1, 8 - index * 2, 8); context.Assembler.Pshufd(src1, src1, (byte)mask0); // Lane to be inserted in position 0. - context.Assembler.Movss (dest, src1, src2); // dest[127:0] = src1[127:32] | src2[31:0] + context.Assembler.Movss(dest, src1, src2); // dest[127:0] = src1[127:32] | src2[31:0] context.Assembler.Pshufd(dest, dest, (byte)mask1); // Inserted lane in original position. if (dest.GetRegister() != src1.GetRegister()) @@ -1555,7 +1557,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128); @@ -1565,7 +1567,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128); @@ -1575,7 +1577,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateZeroExtend16(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1585,7 +1587,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateZeroExtend32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1601,7 +1603,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateZeroExtend8(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1613,13 +1615,25 @@ namespace ARMeilleure.CodeGen.X86 { switch (value.Type) { - case OperandType.I32: context.Assembler.Mov (value, address, OperandType.I32); break; - case OperandType.I64: context.Assembler.Mov (value, address, OperandType.I64); break; - case OperandType.FP32: context.Assembler.Movd (value, address); break; - case OperandType.FP64: context.Assembler.Movq (value, address); break; - case OperandType.V128: context.Assembler.Movdqu(value, address); break; + case OperandType.I32: + context.Assembler.Mov(value, address, OperandType.I32); + break; + case OperandType.I64: + context.Assembler.Mov(value, address, OperandType.I64); + break; + case OperandType.FP32: + context.Assembler.Movd(value, address); + break; + case OperandType.FP64: + context.Assembler.Movq(value, address); + break; + case OperandType.V128: + context.Assembler.Movdqu(value, address); + break; - default: Debug.Assert(false); break; + default: + Debug.Assert(false); + break; } } @@ -1627,13 +1641,25 @@ namespace ARMeilleure.CodeGen.X86 { switch (value.Type) { - case OperandType.I32: context.Assembler.Mov (address, value, OperandType.I32); break; - case OperandType.I64: context.Assembler.Mov (address, value, OperandType.I64); break; - case OperandType.FP32: context.Assembler.Movd (address, value); break; - case OperandType.FP64: context.Assembler.Movq (address, value); break; - case OperandType.V128: context.Assembler.Movdqu(address, value); break; + case OperandType.I32: + context.Assembler.Mov(address, value, OperandType.I32); + break; + case OperandType.I64: + context.Assembler.Mov(address, value, OperandType.I64); + break; + case OperandType.FP32: + context.Assembler.Movd(address, value); + break; + case OperandType.FP64: + context.Assembler.Movq(address, value); + break; + case OperandType.V128: + context.Assembler.Movdqu(address, value); + break; - default: Debug.Assert(false); break; + default: + Debug.Assert(false); + break; } } @@ -1670,21 +1696,21 @@ namespace ARMeilleure.CodeGen.X86 [Conditional("DEBUG")] private static void ValidateUnOp(Operand dest, Operand source) { - EnsureSameReg (dest, source); + EnsureSameReg(dest, source); EnsureSameType(dest, source); } [Conditional("DEBUG")] private static void ValidateBinOp(Operand dest, Operand src1, Operand src2) { - EnsureSameReg (dest, src1); + EnsureSameReg(dest, src1); EnsureSameType(dest, src1, src2); } [Conditional("DEBUG")] private static void ValidateShift(Operand dest, Operand src1, Operand src2) { - EnsureSameReg (dest, src1); + EnsureSameReg(dest, src1); EnsureSameType(dest, src1); Debug.Assert(dest.Type.IsInteger() && src2.Type == OperandType.I32); @@ -1722,7 +1748,7 @@ namespace ARMeilleure.CodeGen.X86 private static UnwindInfo WritePrologue(CodeGenContext context) { - List pushEntries = new List(); + List pushEntries = new(); Operand rsp = Register(X86Register.Rsp); @@ -1831,7 +1857,7 @@ namespace ARMeilleure.CodeGen.X86 size = (size + pageMask) & ~pageMask; - Operand rsp = Register(X86Register.Rsp); + Operand rsp = Register(X86Register.Rsp); Operand temp = Register(CallingConvention.GetIntReturnRegister()); for (int offset = PageSize; offset < size; offset += PageSize) @@ -1862,4 +1888,4 @@ namespace ARMeilleure.CodeGen.X86 return Operand.Factory.Register((int)register, RegisterType.Vector, OperandType.V128); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs b/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs index 07cdcd09..4f6f1e87 100644 --- a/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs +++ b/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs @@ -47,7 +47,7 @@ namespace ARMeilleure.CodeGen.X86 0xc3, // ret }; - using MemoryBlock memGetXcr0 = new MemoryBlock((ulong)asmGetXcr0.Length); + using MemoryBlock memGetXcr0 = new((ulong)asmGetXcr0.Length); memGetXcr0.Write(0, asmGetXcr0); @@ -62,7 +62,7 @@ namespace ARMeilleure.CodeGen.X86 public enum FeatureFlags1Edx { Sse = 1 << 25, - Sse2 = 1 << 26 + Sse2 = 1 << 26, } [Flags] @@ -79,7 +79,7 @@ namespace ARMeilleure.CodeGen.X86 Xsave = 1 << 26, Osxsave = 1 << 27, Avx = 1 << 28, - F16c = 1 << 29 + F16c = 1 << 29, } [Flags] @@ -90,7 +90,7 @@ namespace ARMeilleure.CodeGen.X86 Avx512dq = 1 << 17, Sha = 1 << 29, Avx512bw = 1 << 30, - Avx512vl = 1 << 31 + Avx512vl = 1 << 31, } [Flags] @@ -106,7 +106,7 @@ namespace ARMeilleure.CodeGen.X86 YmmHi128 = 1 << 2, Opmask = 1 << 5, ZmmHi256 = 1 << 6, - Hi16Zmm = 1 << 7 + Hi16Zmm = 1 << 7, } public static FeatureFlags1Edx FeatureInfo1Edx { get; } @@ -141,4 +141,4 @@ namespace ARMeilleure.CodeGen.X86 public static bool SupportsVexEncoding => SupportsAvx && !ForceLegacySse; public static bool SupportsEvexEncoding => SupportsAvx512F && !ForceLegacySse; } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs b/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs index 302bf4d3..16054c61 100644 --- a/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs +++ b/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.CodeGen.X86 readonly struct IntrinsicInfo { public X86Instruction Inst { get; } - public IntrinsicType Type { get; } + public IntrinsicType Type { get; } public IntrinsicInfo(X86Instruction inst, IntrinsicType type) { @@ -11,4 +11,4 @@ namespace ARMeilleure.CodeGen.X86 Type = type; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs b/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs index e3d94b7a..daa1f8f6 100644 --- a/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs +++ b/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs @@ -5,12 +5,13 @@ namespace ARMeilleure.CodeGen.X86 { static class IntrinsicTable { - private static IntrinsicInfo[] _intrinTable; + private static readonly IntrinsicInfo[] _intrinTable; static IntrinsicTable() { _intrinTable = new IntrinsicInfo[EnumUtils.GetCount(typeof(Intrinsic))]; +#pragma warning disable IDE0055 // Disable formatting Add(Intrinsic.X86Addpd, new IntrinsicInfo(X86Instruction.Addpd, IntrinsicType.Binary)); Add(Intrinsic.X86Addps, new IntrinsicInfo(X86Instruction.Addps, IntrinsicType.Binary)); Add(Intrinsic.X86Addsd, new IntrinsicInfo(X86Instruction.Addsd, IntrinsicType.Binary)); @@ -185,6 +186,7 @@ namespace ARMeilleure.CodeGen.X86 Add(Intrinsic.X86Vpternlogd, new IntrinsicInfo(X86Instruction.Vpternlogd, IntrinsicType.TernaryImm)); Add(Intrinsic.X86Xorpd, new IntrinsicInfo(X86Instruction.Xorpd, IntrinsicType.Binary)); Add(Intrinsic.X86Xorps, new IntrinsicInfo(X86Instruction.Xorps, IntrinsicType.Binary)); +#pragma warning restore IDE0055 } private static void Add(Intrinsic intrin, IntrinsicInfo info) @@ -197,4 +199,4 @@ namespace ARMeilleure.CodeGen.X86 return _intrinTable[(int)intrin]; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs b/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs index 5a9c14af..7c3ef354 100644 --- a/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs +++ b/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs @@ -13,6 +13,6 @@ namespace ARMeilleure.CodeGen.X86 Crc32, Ternary, TernaryImm, - Fma + Fma, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/Mxcsr.cs b/src/ARMeilleure/CodeGen/X86/Mxcsr.cs index c61eac31..83d7a584 100644 --- a/src/ARMeilleure/CodeGen/X86/Mxcsr.cs +++ b/src/ARMeilleure/CodeGen/X86/Mxcsr.cs @@ -10,6 +10,6 @@ namespace ARMeilleure.CodeGen.X86 Rlo = 1 << 13, // Round Mode low bit. Um = 1 << 11, // Underflow Mask. Dm = 1 << 8, // Denormal Mask. - Daz = 1 << 6 // Denormals Are Zero. + Daz = 1 << 6, // Denormals Are Zero. } } diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocator.cs b/src/ARMeilleure/CodeGen/X86/PreAllocator.cs index cb742d67..590c35c7 100644 --- a/src/ARMeilleure/CodeGen/X86/PreAllocator.cs +++ b/src/ARMeilleure/CodeGen/X86/PreAllocator.cs @@ -104,11 +104,11 @@ namespace ARMeilleure.CodeGen.X86 case Instruction.Tailcall: if (callConv == CallConvName.Windows) { - PreAllocatorWindows.InsertTailcallCopies(block.Operations, stackAlloc, node); + PreAllocatorWindows.InsertTailcallCopies(block.Operations, node); } else { - PreAllocatorSystemV.InsertTailcallCopies(block.Operations, stackAlloc, node); + PreAllocatorSystemV.InsertTailcallCopies(block.Operations, node); } break; @@ -177,10 +177,7 @@ namespace ARMeilleure.CodeGen.X86 { src2 = node.GetSource(1); - Operand temp = src1; - - src1 = src2; - src2 = temp; + (src2, src1) = (src1, src2); node.SetSource(0, src1); node.SetSource(1, src2); @@ -228,151 +225,151 @@ namespace ARMeilleure.CodeGen.X86 case Instruction.CompareAndSwap: case Instruction.CompareAndSwap16: case Instruction.CompareAndSwap8: - { - OperandType type = node.GetSource(1).Type; - - if (type == OperandType.V128) { - // Handle the many restrictions of the compare and exchange (16 bytes) instruction: - // - The expected value should be in RDX:RAX. - // - The new value to be written should be in RCX:RBX. - // - The value at the memory location is loaded to RDX:RAX. - void SplitOperand(Operand source, Operand lr, Operand hr) + OperandType type = node.GetSource(1).Type; + + if (type == OperandType.V128) { - nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0))); - nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1))); + // Handle the many restrictions of the compare and exchange (16 bytes) instruction: + // - The expected value should be in RDX:RAX. + // - The new value to be written should be in RCX:RBX. + // - The value at the memory location is loaded to RDX:RAX. + void SplitOperand(Operand source, Operand lr, Operand hr) + { + nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0))); + nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1))); + } + + Operand rax = Gpr(X86Register.Rax, OperandType.I64); + Operand rbx = Gpr(X86Register.Rbx, OperandType.I64); + Operand rcx = Gpr(X86Register.Rcx, OperandType.I64); + Operand rdx = Gpr(X86Register.Rdx, OperandType.I64); + + SplitOperand(node.GetSource(1), rax, rdx); + SplitOperand(node.GetSource(2), rbx, rcx); + + Operation operation = node; + + node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax)); + nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1))); + + operation.SetDestinations(new Operand[] { rdx, rax }); + operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx }); + } + else + { + // Handle the many restrictions of the compare and exchange (32/64) instruction: + // - The expected value should be in (E/R)AX. + // - The value at the memory location is loaded to (E/R)AX. + Operand expected = node.GetSource(1); + Operand newValue = node.GetSource(2); + + Operand rax = Gpr(X86Register.Rax, expected.Type); + + nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected)); + + // We need to store the new value into a temp, since it may + // be a constant, and this instruction does not support immediate operands. + Operand temp = Local(newValue.Type); + + nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue)); + + node.SetSources(new Operand[] { node.GetSource(0), rax, temp }); + + nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax)); + + node.Destination = rax; } - Operand rax = Gpr(X86Register.Rax, OperandType.I64); - Operand rbx = Gpr(X86Register.Rbx, OperandType.I64); - Operand rcx = Gpr(X86Register.Rcx, OperandType.I64); - Operand rdx = Gpr(X86Register.Rdx, OperandType.I64); - - SplitOperand(node.GetSource(1), rax, rdx); - SplitOperand(node.GetSource(2), rbx, rcx); - - Operation operation = node; - - node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax)); - nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1))); - - operation.SetDestinations(new Operand[] { rdx, rax }); - operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx }); + break; } - else - { - // Handle the many restrictions of the compare and exchange (32/64) instruction: - // - The expected value should be in (E/R)AX. - // - The value at the memory location is loaded to (E/R)AX. - Operand expected = node.GetSource(1); - Operand newValue = node.GetSource(2); - - Operand rax = Gpr(X86Register.Rax, expected.Type); - - nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected)); - - // We need to store the new value into a temp, since it may - // be a constant, and this instruction does not support immediate operands. - Operand temp = Local(newValue.Type); - - nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue)); - - node.SetSources(new Operand[] { node.GetSource(0), rax, temp }); - - nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax)); - - node.Destination = rax; - } - - break; - } case Instruction.Divide: case Instruction.DivideUI: - { - // Handle the many restrictions of the division instructions: - // - The dividend is always in RDX:RAX. - // - The result is always in RAX. - // - Additionally it also writes the remainder in RDX. - if (dest.Type.IsInteger()) { + // Handle the many restrictions of the division instructions: + // - The dividend is always in RDX:RAX. + // - The result is always in RAX. + // - Additionally it also writes the remainder in RDX. + if (dest.Type.IsInteger()) + { + Operand src1 = node.GetSource(0); + + Operand rax = Gpr(X86Register.Rax, src1.Type); + Operand rdx = Gpr(X86Register.Rdx, src1.Type); + + nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1)); + nodes.AddBefore(node, Operation(Instruction.Clobber, rdx)); + + nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax)); + + node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) }); + node.Destination = rax; + } + + break; + } + + case Instruction.Extended: + { + bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd || + node.Intrinsic == Intrinsic.X86Blendvps || + node.Intrinsic == Intrinsic.X86Pblendvb; + + // BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported. + // SHA256RNDS2 always has an implied XMM0 as a last operand. + if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2) + { + Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128); + + nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2))); + + node.SetSource(2, xmm0); + } + + break; + } + + case Instruction.Multiply64HighSI: + case Instruction.Multiply64HighUI: + { + // Handle the many restrictions of the i64 * i64 = i128 multiply instructions: + // - The multiplicand is always in RAX. + // - The lower 64-bits of the result is always in RAX. + // - The higher 64-bits of the result is always in RDX. Operand src1 = node.GetSource(0); Operand rax = Gpr(X86Register.Rax, src1.Type); Operand rdx = Gpr(X86Register.Rdx, src1.Type); - nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1)); - nodes.AddBefore(node, Operation(Instruction.Clobber, rdx)); + nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1)); - nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax)); + node.SetSource(0, rax); - node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) }); - node.Destination = rax; + nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx)); + + node.SetDestinations(new Operand[] { rdx, rax }); + + break; } - break; - } - - case Instruction.Extended: - { - bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd || - node.Intrinsic == Intrinsic.X86Blendvps || - node.Intrinsic == Intrinsic.X86Pblendvb; - - // BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported. - // SHA256RNDS2 always has an implied XMM0 as a last operand. - if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2) - { - Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128); - - nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2))); - - node.SetSource(2, xmm0); - } - - break; - } - - case Instruction.Multiply64HighSI: - case Instruction.Multiply64HighUI: - { - // Handle the many restrictions of the i64 * i64 = i128 multiply instructions: - // - The multiplicand is always in RAX. - // - The lower 64-bits of the result is always in RAX. - // - The higher 64-bits of the result is always in RDX. - Operand src1 = node.GetSource(0); - - Operand rax = Gpr(X86Register.Rax, src1.Type); - Operand rdx = Gpr(X86Register.Rdx, src1.Type); - - nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1)); - - node.SetSource(0, rax); - - nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx)); - - node.SetDestinations(new Operand[] { rdx, rax }); - - break; - } - case Instruction.RotateRight: case Instruction.ShiftLeft: case Instruction.ShiftRightSI: case Instruction.ShiftRightUI: - { - // The shift register is always implied to be CL (low 8-bits of RCX or ECX). - if (node.GetSource(1).Kind == OperandKind.LocalVariable) { - Operand rcx = Gpr(X86Register.Rcx, OperandType.I32); + // The shift register is always implied to be CL (low 8-bits of RCX or ECX). + if (node.GetSource(1).Kind == OperandKind.LocalVariable) + { + Operand rcx = Gpr(X86Register.Rcx, OperandType.I32); - nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1))); + nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1))); - node.SetSource(1, rcx); + node.SetSource(1, rcx); + } + + break; } - - break; - } } } @@ -459,7 +456,7 @@ namespace ARMeilleure.CodeGen.X86 // Unsigned integer to FP conversions are not supported on X86. // We need to turn them into signed integer to FP conversions, and // adjust the final result. - Operand dest = node.Destination; + Operand dest = node.Destination; Operand source = node.GetSource(0); Debug.Assert(source.Type.IsInteger(), $"Invalid source type \"{source.Type}\"."); @@ -472,8 +469,8 @@ namespace ARMeilleure.CodeGen.X86 // and then use the 64-bits signed conversion instructions. Operand zex = Local(OperandType.I64); - node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex, source)); - node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, zex)); + node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex, source)); + nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, zex)); } else /* if (source.Type == OperandType.I64) */ { @@ -487,15 +484,15 @@ namespace ARMeilleure.CodeGen.X86 // --- This can be done efficiently by adding the result to itself. // -- Then, we need to add the least significant bit that was shifted out. // --- We can convert the least significant bit to float, and add it to the result. - Operand lsb = Local(OperandType.I64); + Operand lsb = Local(OperandType.I64); Operand half = Local(OperandType.I64); Operand lsbF = Local(dest.Type); - node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb, source)); + node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb, source)); node = nodes.AddAfter(node, Operation(Instruction.Copy, half, source)); - node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, lsb, lsb, Const(1L))); + node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, lsb, lsb, Const(1L))); node = nodes.AddAfter(node, Operation(Instruction.ShiftRightUI, half, half, Const(1))); node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, lsbF, lsb)); @@ -513,7 +510,7 @@ namespace ARMeilleure.CodeGen.X86 // There's no SSE FP negate instruction, so we need to transform that into // a XOR of the value to be negated with a mask with the highest bit set. // This also produces -0 for a negation of the value 0. - Operand dest = node.Destination; + Operand dest = node.Destination; Operand source = node.GetSource(0); Debug.Assert(dest.Type == OperandType.FP32 || @@ -569,14 +566,14 @@ namespace ARMeilleure.CodeGen.X86 if ((index & 1) != 0) { node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp1, temp1)); - node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, temp2, temp2, Const(8))); - node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2)); + node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, temp2, temp2, Const(8))); + node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2)); } else { node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp2, temp2)); - node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, temp1, temp1, Const(0xff00))); - node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2)); + node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, temp1, temp1, Const(0xff00))); + node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2)); } Operation vinsOp = Operation(Instruction.VectorInsert16, dest, src1, temp1, Const(index >> 1)); @@ -709,16 +706,11 @@ namespace ARMeilleure.CodeGen.X86 private static bool HasConstSrc1(Instruction inst) { - switch (inst) + return inst switch { - case Instruction.Copy: - case Instruction.LoadArgument: - case Instruction.Spill: - case Instruction.SpillArg: - return true; - } - - return false; + Instruction.Copy or Instruction.LoadArgument or Instruction.Spill or Instruction.SpillArg => true, + _ => false, + }; } private static bool HasConstSrc2(Instruction inst) @@ -762,15 +754,15 @@ namespace ARMeilleure.CodeGen.X86 case Instruction.BranchIf: case Instruction.Compare: - { - Operand comp = operation.GetSource(2); + { + Operand comp = operation.GetSource(2); - Debug.Assert(comp.Kind == OperandKind.Constant); + Debug.Assert(comp.Kind == OperandKind.Constant); - var compType = (Comparison)comp.AsInt32(); + var compType = (Comparison)comp.AsInt32(); - return compType == Comparison.Equal || compType == Comparison.NotEqual; - } + return compType == Comparison.Equal || compType == Comparison.NotEqual; + } } return false; @@ -793,4 +785,4 @@ namespace ARMeilleure.CodeGen.X86 return info.Type != IntrinsicType.Crc32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs b/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs index a84d5050..e754cb09 100644 --- a/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs +++ b/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs @@ -1,4 +1,3 @@ -using ARMeilleure.CodeGen.RegisterAllocators; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; @@ -15,9 +14,9 @@ namespace ARMeilleure.CodeGen.X86 { Operand dest = node.Destination; - List sources = new List + List sources = new() { - node.GetSource(0) + node.GetSource(0), }; int argsCount = node.SourcesCount - 1; @@ -52,10 +51,10 @@ namespace ARMeilleure.CodeGen.X86 if (source.Type == OperandType.V128 && passOnReg) { // V128 is a struct, we pass each half on a GPR if possible. - Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); + Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); - nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0))); + nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0))); nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg2, source, Const(1))); continue; @@ -91,7 +90,7 @@ namespace ARMeilleure.CodeGen.X86 { if (dest.Type == OperandType.V128) { - Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); + Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64); Operation operation = node; @@ -116,11 +115,11 @@ namespace ARMeilleure.CodeGen.X86 } } - public static void InsertTailcallCopies(IntrusiveList nodes, StackAllocator stackAlloc, Operation node) + public static void InsertTailcallCopies(IntrusiveList nodes, Operation node) { - List sources = new List + List sources = new() { - node.GetSource(0) + node.GetSource(0), }; int argsCount = node.SourcesCount - 1; @@ -251,11 +250,11 @@ namespace ARMeilleure.CodeGen.X86 // V128 is a struct, we pass each half on a GPR if possible. Operand pArg = Local(OperandType.V128); - Operand argLReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount), OperandType.I64); + Operand argLReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount), OperandType.I64); Operand argHReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount + 1), OperandType.I64); Operation copyL = Operation(Instruction.VectorCreateScalar, pArg, argLReg); - Operation copyH = Operation(Instruction.VectorInsert, pArg, pArg, argHReg, Const(1)); + Operation copyH = Operation(Instruction.VectorInsert, pArg, pArg, argHReg, Const(1)); cctx.Cfg.Entry.Operations.AddFirst(copyH); cctx.Cfg.Entry.Operations.AddFirst(copyL); @@ -313,7 +312,7 @@ namespace ARMeilleure.CodeGen.X86 if (source.Type == OperandType.V128) { - Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); + Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64); nodes.AddBefore(node, Operation(Instruction.VectorExtract, retLReg, source, Const(0))); @@ -331,4 +330,4 @@ namespace ARMeilleure.CodeGen.X86 } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs b/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs index 45319e6a..10a2bd12 100644 --- a/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs +++ b/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs @@ -155,7 +155,7 @@ namespace ARMeilleure.CodeGen.X86 node.SetSources(sources); } - public static void InsertTailcallCopies(IntrusiveList nodes, StackAllocator stackAlloc, Operation node) + public static void InsertTailcallCopies(IntrusiveList nodes, Operation node) { int argsCount = node.SourcesCount - 1; int maxArgs = CallingConvention.GetArgumentsOnRegsCount(); @@ -324,4 +324,4 @@ namespace ARMeilleure.CodeGen.X86 node.SetSources(Array.Empty()); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/X86Condition.cs b/src/ARMeilleure/CodeGen/X86/X86Condition.cs index c82cbdec..70699a20 100644 --- a/src/ARMeilleure/CodeGen/X86/X86Condition.cs +++ b/src/ARMeilleure/CodeGen/X86/X86Condition.cs @@ -5,22 +5,22 @@ namespace ARMeilleure.CodeGen.X86 { enum X86Condition { - Overflow = 0x0, - NotOverflow = 0x1, - Below = 0x2, - AboveOrEqual = 0x3, - Equal = 0x4, - NotEqual = 0x5, - BelowOrEqual = 0x6, - Above = 0x7, - Sign = 0x8, - NotSign = 0x9, - ParityEven = 0xa, - ParityOdd = 0xb, - Less = 0xc, + Overflow = 0x0, + NotOverflow = 0x1, + Below = 0x2, + AboveOrEqual = 0x3, + Equal = 0x4, + NotEqual = 0x5, + BelowOrEqual = 0x6, + Above = 0x7, + Sign = 0x8, + NotSign = 0x9, + ParityEven = 0xa, + ParityOdd = 0xb, + Less = 0xc, GreaterOrEqual = 0xd, - LessOrEqual = 0xe, - Greater = 0xf + LessOrEqual = 0xe, + Greater = 0xf, } static class ComparisonX86Extensions @@ -29,6 +29,7 @@ namespace ARMeilleure.CodeGen.X86 { return comp switch { +#pragma warning disable IDE0055 // Disable formatting Comparison.Equal => X86Condition.Equal, Comparison.NotEqual => X86Condition.NotEqual, Comparison.Greater => X86Condition.Greater, @@ -39,9 +40,10 @@ namespace ARMeilleure.CodeGen.X86 Comparison.Less => X86Condition.Less, Comparison.GreaterOrEqualUI => X86Condition.AboveOrEqual, Comparison.LessUI => X86Condition.Below, +#pragma warning restore IDE0055 - _ => throw new ArgumentException(null, nameof(comp)) + _ => throw new ArgumentException(null, nameof(comp)), }; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/X86Instruction.cs b/src/ARMeilleure/CodeGen/X86/X86Instruction.cs index 9a85c516..e1979011 100644 --- a/src/ARMeilleure/CodeGen/X86/X86Instruction.cs +++ b/src/ARMeilleure/CodeGen/X86/X86Instruction.cs @@ -226,6 +226,6 @@ namespace ARMeilleure.CodeGen.X86 Xorpd, Xorps, - Count + Count, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs b/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs index 98a19b9a..9d23f9ad 100644 --- a/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs +++ b/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs @@ -215,7 +215,7 @@ namespace ARMeilleure.CodeGen.X86 1 => Multiplier.x2, 2 => Multiplier.x4, 3 => Multiplier.x8, - _ => Multiplier.x1 + _ => Multiplier.x1, }; baseOp = indexOnSrc2 ? src1 : src2; diff --git a/src/ARMeilleure/CodeGen/X86/X86Register.cs b/src/ARMeilleure/CodeGen/X86/X86Register.cs index 01f63e31..0a656366 100644 --- a/src/ARMeilleure/CodeGen/X86/X86Register.cs +++ b/src/ARMeilleure/CodeGen/X86/X86Register.cs @@ -1,5 +1,8 @@ +using System.Diagnostics.CodeAnalysis; + namespace ARMeilleure.CodeGen.X86 { + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] enum X86Register { Invalid = -1, @@ -12,8 +15,8 @@ namespace ARMeilleure.CodeGen.X86 Rbp = 5, Rsi = 6, Rdi = 7, - R8 = 8, - R9 = 9, + R8 = 8, + R9 = 9, R10 = 10, R11 = 11, R12 = 12, @@ -21,21 +24,21 @@ namespace ARMeilleure.CodeGen.X86 R14 = 14, R15 = 15, - Xmm0 = 0, - Xmm1 = 1, - Xmm2 = 2, - Xmm3 = 3, - Xmm4 = 4, - Xmm5 = 5, - Xmm6 = 6, - Xmm7 = 7, - Xmm8 = 8, - Xmm9 = 9, + Xmm0 = 0, + Xmm1 = 1, + Xmm2 = 2, + Xmm3 = 3, + Xmm4 = 4, + Xmm5 = 5, + Xmm6 = 6, + Xmm7 = 7, + Xmm8 = 8, + Xmm9 = 9, Xmm10 = 10, Xmm11 = 11, Xmm12 = 12, Xmm13 = 13, Xmm14 = 14, - Xmm15 = 15 + Xmm15 = 15, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Common/ArenaAllocator.cs b/src/ARMeilleure/Common/ArenaAllocator.cs index bce6794a..f810c2ab 100644 --- a/src/ARMeilleure/Common/ArenaAllocator.cs +++ b/src/ARMeilleure/Common/ArenaAllocator.cs @@ -82,8 +82,10 @@ namespace ARMeilleure.Common } else { - _page = new PageInfo(); - _page.Pointer = (byte*)NativeAllocator.Instance.Allocate(_pageSize); + _page = new PageInfo + { + Pointer = (byte*)NativeAllocator.Instance.Allocate(_pageSize), + }; _pages.Add(_page); } @@ -106,7 +108,7 @@ namespace ARMeilleure.Common // Free excess pages that was allocated. while (_pages.Count > _pageCount) { - NativeAllocator.Instance.Free(_pages[_pages.Count - 1].Pointer); + NativeAllocator.Instance.Free(_pages[^1].Pointer); _pages.RemoveAt(_pages.Count - 1); } @@ -125,12 +127,13 @@ namespace ARMeilleure.Common // If arena is used frequently, keep pages for longer. Otherwise keep pages for a shorter amount of time. int now = Environment.TickCount; - int count = (now - _lastReset) switch { + int count = (now - _lastReset) switch + { >= 5000 => 0, >= 2500 => 50, >= 1000 => 100, - >= 10 => 1500, - _ => 5000 + >= 10 => 1500, + _ => 5000, }; for (int i = _pages.Count - 1; i >= 0; i--) diff --git a/src/ARMeilleure/Common/BitMap.cs b/src/ARMeilleure/Common/BitMap.cs index 27ef031f..94d47ea5 100644 --- a/src/ARMeilleure/Common/BitMap.cs +++ b/src/ARMeilleure/Common/BitMap.cs @@ -138,7 +138,7 @@ namespace ARMeilleure.Common var newSpan = new Span(_masks, _count); oldSpan.CopyTo(newSpan); - newSpan.Slice(oldSpan.Length).Clear(); + newSpan[oldSpan.Length..].Clear(); _allocator.Free(oldMask); } @@ -176,8 +176,8 @@ namespace ARMeilleure.Common private int _bit; private readonly BitMap _map; - public int Current => (int)_index * IntSize + _bit; - object IEnumerator.Current => Current; + public readonly int Current => (int)_index * IntSize + _bit; + readonly object IEnumerator.Current => Current; public Enumerator(BitMap map) { @@ -214,9 +214,9 @@ namespace ARMeilleure.Common return true; } - public void Reset() { } + public readonly void Reset() { } - public void Dispose() { } + public readonly void Dispose() { } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/Block.cs b/src/ARMeilleure/Decoders/Block.cs index f296d299..bb88170d 100644 --- a/src/ARMeilleure/Decoders/Block.cs +++ b/src/ARMeilleure/Decoders/Block.cs @@ -5,10 +5,10 @@ namespace ARMeilleure.Decoders { class Block { - public ulong Address { get; set; } + public ulong Address { get; set; } public ulong EndAddress { get; set; } - public Block Next { get; set; } + public Block Next { get; set; } public Block Branch { get; set; } public bool Exit { get; set; } @@ -43,14 +43,14 @@ namespace ARMeilleure.Decoders rightBlock.EndAddress = EndAddress; - rightBlock.Next = Next; + rightBlock.Next = Next; rightBlock.Branch = Branch; rightBlock.OpCodes.AddRange(OpCodes.GetRange(splitIndex, splitCount)); EndAddress = rightBlock.Address; - Next = rightBlock; + Next = rightBlock; Branch = null; OpCodes.RemoveRange(splitIndex, splitCount); @@ -58,9 +58,9 @@ namespace ARMeilleure.Decoders private static int BinarySearch(List opCodes, ulong address) { - int left = 0; + int left = 0; int middle = 0; - int right = opCodes.Count - 1; + int right = opCodes.Count - 1; while (left <= right) { @@ -92,10 +92,10 @@ namespace ARMeilleure.Decoders { if (OpCodes.Count > 0) { - return OpCodes[OpCodes.Count - 1]; + return OpCodes[^1]; } return null; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/Condition.cs b/src/ARMeilleure/Decoders/Condition.cs index 727f897d..961825a1 100644 --- a/src/ARMeilleure/Decoders/Condition.cs +++ b/src/ARMeilleure/Decoders/Condition.cs @@ -2,22 +2,22 @@ namespace ARMeilleure.Decoders { enum Condition { - Eq = 0, - Ne = 1, + Eq = 0, + Ne = 1, GeUn = 2, LtUn = 3, - Mi = 4, - Pl = 5, - Vs = 6, - Vc = 7, + Mi = 4, + Pl = 5, + Vs = 6, + Vc = 7, GtUn = 8, LeUn = 9, - Ge = 10, - Lt = 11, - Gt = 12, - Le = 13, - Al = 14, - Nv = 15 + Ge = 10, + Lt = 11, + Gt = 12, + Le = 13, + Al = 14, + Nv = 15, } static class ConditionExtensions @@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders return (Condition)((int)cond ^ 1); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/DataOp.cs b/src/ARMeilleure/Decoders/DataOp.cs index 464d0089..f99fd5e7 100644 --- a/src/ARMeilleure/Decoders/DataOp.cs +++ b/src/ARMeilleure/Decoders/DataOp.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { enum DataOp { - Adr = 0, + Adr = 0, Arithmetic = 1, - Logical = 2, - BitField = 3 + Logical = 2, + BitField = 3, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/Decoder.cs b/src/ARMeilleure/Decoders/Decoder.cs index 426465aa..d8abeb9c 100644 --- a/src/ARMeilleure/Decoders/Decoder.cs +++ b/src/ARMeilleure/Decoders/Decoder.cs @@ -20,11 +20,11 @@ namespace ARMeilleure.Decoders public static Block[] Decode(IMemoryManager memory, ulong address, ExecutionMode mode, bool highCq, DecoderMode dMode) { - List blocks = new List(); + List blocks = new(); - Queue workQueue = new Queue(); + Queue workQueue = new(); - Dictionary visited = new Dictionary(); + Dictionary visited = new(); Debug.Assert(MaxInstsPerFunctionLowCq <= MaxInstsPerFunction); @@ -163,7 +163,7 @@ namespace ARMeilleure.Decoders { index = 0; - int left = 0; + int left = 0; int right = blocks.Count - 1; while (left <= right) @@ -196,9 +196,9 @@ namespace ARMeilleure.Decoders private static void FillBlock( IMemoryManager memory, - ExecutionMode mode, - Block block, - ulong limitAddress) + ExecutionMode mode, + Block block, + ulong limitAddress) { ulong address = block.Address; int itBlockSize = 0; @@ -241,12 +241,12 @@ namespace ARMeilleure.Decoders private static bool IsUnconditionalBranch(OpCode opCode) { return opCode is OpCodeBImmAl || - opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode); + opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode); } private static bool IsAarch32UnconditionalBranch(OpCode opCode) { - if (!(opCode is OpCode32 op)) + if (opCode is not OpCode32 op) { return false; } @@ -290,9 +290,9 @@ namespace ARMeilleure.Decoders if (opCode is IOpCode32Mem opMem) { - rt = opMem.Rt; - rn = opMem.Rn; - wBack = opMem.WBack; + rt = opMem.Rt; + rn = opMem.Rn; + wBack = opMem.WBack; isLoad = opMem.IsLoad; // For the dual load, we also need to take into account the @@ -306,10 +306,10 @@ namespace ARMeilleure.Decoders { const int pcMask = 1 << RegisterAlias.Aarch32Pc; - rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0; - rn = opMemMult.Rn; - wBack = opMemMult.PostOffset != 0; - isLoad = opMemMult.IsLoad; + rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0; + rn = opMemMult.Rn; + wBack = opMemMult.PostOffset != 0; + isLoad = opMemMult.IsLoad; } else { @@ -388,4 +388,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/DecoderHelper.cs b/src/ARMeilleure/Decoders/DecoderHelper.cs index 5227e6a1..35e57395 100644 --- a/src/ARMeilleure/Decoders/DecoderHelper.cs +++ b/src/ARMeilleure/Decoders/DecoderHelper.cs @@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders Imm8ToFP64Table = BuildImm8ToFP64Table(); } - public static readonly uint[] Imm8ToFP32Table; + public static readonly uint[] Imm8ToFP32Table; public static readonly ulong[] Imm8ToFP64Table; private static uint[] BuildImm8ToFP32Table() @@ -40,47 +40,47 @@ namespace ARMeilleure.Decoders // abcdefgh -> aBbbbbbc defgh000 00000000 00000000 (B = ~b) private static uint ExpandImm8ToFP32(uint imm) { - uint MoveBit(uint bits, int from, int to) + static uint MoveBit(uint bits, int from, int to) { return ((bits >> from) & 1U) << to; } return MoveBit(imm, 7, 31) | MoveBit(~imm, 6, 30) | - MoveBit(imm, 6, 29) | MoveBit( imm, 6, 28) | - MoveBit(imm, 6, 27) | MoveBit( imm, 6, 26) | - MoveBit(imm, 6, 25) | MoveBit( imm, 5, 24) | - MoveBit(imm, 4, 23) | MoveBit( imm, 3, 22) | - MoveBit(imm, 2, 21) | MoveBit( imm, 1, 20) | + MoveBit(imm, 6, 29) | MoveBit(imm, 6, 28) | + MoveBit(imm, 6, 27) | MoveBit(imm, 6, 26) | + MoveBit(imm, 6, 25) | MoveBit(imm, 5, 24) | + MoveBit(imm, 4, 23) | MoveBit(imm, 3, 22) | + MoveBit(imm, 2, 21) | MoveBit(imm, 1, 20) | MoveBit(imm, 0, 19); } // abcdefgh -> aBbbbbbb bbcdefgh 00000000 00000000 00000000 00000000 00000000 00000000 (B = ~b) private static ulong ExpandImm8ToFP64(ulong imm) { - ulong MoveBit(ulong bits, int from, int to) + static ulong MoveBit(ulong bits, int from, int to) { return ((bits >> from) & 1UL) << to; } return MoveBit(imm, 7, 63) | MoveBit(~imm, 6, 62) | - MoveBit(imm, 6, 61) | MoveBit( imm, 6, 60) | - MoveBit(imm, 6, 59) | MoveBit( imm, 6, 58) | - MoveBit(imm, 6, 57) | MoveBit( imm, 6, 56) | - MoveBit(imm, 6, 55) | MoveBit( imm, 6, 54) | - MoveBit(imm, 5, 53) | MoveBit( imm, 4, 52) | - MoveBit(imm, 3, 51) | MoveBit( imm, 2, 50) | - MoveBit(imm, 1, 49) | MoveBit( imm, 0, 48); + MoveBit(imm, 6, 61) | MoveBit(imm, 6, 60) | + MoveBit(imm, 6, 59) | MoveBit(imm, 6, 58) | + MoveBit(imm, 6, 57) | MoveBit(imm, 6, 56) | + MoveBit(imm, 6, 55) | MoveBit(imm, 6, 54) | + MoveBit(imm, 5, 53) | MoveBit(imm, 4, 52) | + MoveBit(imm, 3, 51) | MoveBit(imm, 2, 50) | + MoveBit(imm, 1, 49) | MoveBit(imm, 0, 48); } public struct BitMask { public long WMask; public long TMask; - public int Pos; - public int Shift; + public int Pos; + public int Shift; public bool IsUndefined; - public static BitMask Invalid => new BitMask { IsUndefined = true }; + public static BitMask Invalid => new() { IsUndefined = true }; } public static BitMask DecodeBitMask(int opCode, bool immediate) @@ -88,7 +88,7 @@ namespace ARMeilleure.Decoders int immS = (opCode >> 10) & 0x3f; int immR = (opCode >> 16) & 0x3f; - int n = (opCode >> 22) & 1; + int n = (opCode >> 22) & 1; int sf = (opCode >> 31) & 1; int length = BitUtils.HighestBitSet((~immS & 0x3f) | (n << 6)); @@ -115,7 +115,7 @@ namespace ARMeilleure.Decoders if (r > 0) { - wMask = BitUtils.RotateRight(wMask, r, size); + wMask = BitUtils.RotateRight(wMask, r, size); wMask &= BitUtils.FillWithOnes(size); } @@ -124,8 +124,8 @@ namespace ARMeilleure.Decoders WMask = BitUtils.Replicate(wMask, size), TMask = BitUtils.Replicate(tMask, size), - Pos = immS, - Shift = immR + Pos = immS, + Shift = immR, }; } @@ -164,4 +164,4 @@ namespace ARMeilleure.Decoders return false; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/DecoderMode.cs b/src/ARMeilleure/Decoders/DecoderMode.cs index 55362084..280ebb64 100644 --- a/src/ARMeilleure/Decoders/DecoderMode.cs +++ b/src/ARMeilleure/Decoders/DecoderMode.cs @@ -6,4 +6,4 @@ SingleBlock, SingleInstruction, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode.cs b/src/ARMeilleure/Decoders/IOpCode.cs index 37ba7a4c..9d5e3bf7 100644 --- a/src/ARMeilleure/Decoders/IOpCode.cs +++ b/src/ARMeilleure/Decoders/IOpCode.cs @@ -14,4 +14,4 @@ namespace ARMeilleure.Decoders OperandType GetOperandType(); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32.cs b/src/ARMeilleure/Decoders/IOpCode32.cs index 126c1069..578925de 100644 --- a/src/ARMeilleure/Decoders/IOpCode32.cs +++ b/src/ARMeilleure/Decoders/IOpCode32.cs @@ -6,4 +6,4 @@ namespace ARMeilleure.Decoders uint GetPc(); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32Alu.cs b/src/ARMeilleure/Decoders/IOpCode32Alu.cs index 69fee164..a85ef44a 100644 --- a/src/ARMeilleure/Decoders/IOpCode32Alu.cs +++ b/src/ARMeilleure/Decoders/IOpCode32Alu.cs @@ -5,4 +5,4 @@ namespace ARMeilleure.Decoders int Rd { get; } int Rn { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluImm.cs b/src/ARMeilleure/Decoders/IOpCode32AluImm.cs index 342fb8f6..9d49a440 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluImm.cs @@ -6,4 +6,4 @@ bool IsRotated { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs b/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs index cd128f65..dd42a70b 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { int Immediate { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs b/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs index e899a659..8b976b58 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs @@ -7,4 +7,4 @@ ShiftType ShiftType { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs b/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs index 879db059..e8c33c2b 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs @@ -7,4 +7,4 @@ ShiftType ShiftType { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32BImm.cs b/src/ARMeilleure/Decoders/IOpCode32BImm.cs index ec7db2c2..8d22d5c4 100644 --- a/src/ARMeilleure/Decoders/IOpCode32BImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32BImm.cs @@ -1,4 +1,4 @@ namespace ARMeilleure.Decoders { interface IOpCode32BImm : IOpCode32, IOpCodeBImm { } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32BReg.cs b/src/ARMeilleure/Decoders/IOpCode32BReg.cs index 097ab427..9badc985 100644 --- a/src/ARMeilleure/Decoders/IOpCode32BReg.cs +++ b/src/ARMeilleure/Decoders/IOpCode32BReg.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { int Rm { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32Exception.cs b/src/ARMeilleure/Decoders/IOpCode32Exception.cs index 8f0fb81a..4c1fc231 100644 --- a/src/ARMeilleure/Decoders/IOpCode32Exception.cs +++ b/src/ARMeilleure/Decoders/IOpCode32Exception.cs @@ -4,4 +4,4 @@ { int Id { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs b/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs index 71ca6d19..772e1080 100644 --- a/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs +++ b/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs @@ -4,4 +4,4 @@ { bool? SetFlags { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32Mem.cs b/src/ARMeilleure/Decoders/IOpCode32Mem.cs index 6664ddff..a34bc0e2 100644 --- a/src/ARMeilleure/Decoders/IOpCode32Mem.cs +++ b/src/ARMeilleure/Decoders/IOpCode32Mem.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders int Immediate { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32MemMult.cs b/src/ARMeilleure/Decoders/IOpCode32MemMult.cs index 4b891bc1..0c5e48f2 100644 --- a/src/ARMeilleure/Decoders/IOpCode32MemMult.cs +++ b/src/ARMeilleure/Decoders/IOpCode32MemMult.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders int Offset { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32MemReg.cs b/src/ARMeilleure/Decoders/IOpCode32MemReg.cs index 7fe1b022..f356e4d7 100644 --- a/src/ARMeilleure/Decoders/IOpCode32MemReg.cs +++ b/src/ARMeilleure/Decoders/IOpCode32MemReg.cs @@ -4,4 +4,4 @@ { int Rm { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs b/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs index 65b7ee0b..3407e98a 100644 --- a/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs @@ -5,4 +5,4 @@ namespace ARMeilleure.Decoders int Rm { get; } ShiftType ShiftType { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAlu.cs b/src/ARMeilleure/Decoders/IOpCodeAlu.cs index b8c28513..059769ba 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAlu.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAlu.cs @@ -7,4 +7,4 @@ namespace ARMeilleure.Decoders DataOp DataOp { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAluImm.cs b/src/ARMeilleure/Decoders/IOpCodeAluImm.cs index 02f4c997..40a69cc9 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAluImm.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAluImm.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { long Immediate { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAluRs.cs b/src/ARMeilleure/Decoders/IOpCodeAluRs.cs index 22540b11..eec95698 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAluRs.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAluRs.cs @@ -3,8 +3,8 @@ namespace ARMeilleure.Decoders interface IOpCodeAluRs : IOpCodeAlu { int Shift { get; } - int Rm { get; } + int Rm { get; } ShiftType ShiftType { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAluRx.cs b/src/ARMeilleure/Decoders/IOpCodeAluRx.cs index 9d16be78..e5a8559d 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAluRx.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAluRx.cs @@ -3,8 +3,8 @@ namespace ARMeilleure.Decoders interface IOpCodeAluRx : IOpCodeAlu { int Shift { get; } - int Rm { get; } + int Rm { get; } IntType IntType { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeBImm.cs b/src/ARMeilleure/Decoders/IOpCodeBImm.cs index 958bff28..9ce7512a 100644 --- a/src/ARMeilleure/Decoders/IOpCodeBImm.cs +++ b/src/ARMeilleure/Decoders/IOpCodeBImm.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { long Immediate { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeCond.cs b/src/ARMeilleure/Decoders/IOpCodeCond.cs index 9808f7c0..6604f19a 100644 --- a/src/ARMeilleure/Decoders/IOpCodeCond.cs +++ b/src/ARMeilleure/Decoders/IOpCodeCond.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { Condition Cond { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeLit.cs b/src/ARMeilleure/Decoders/IOpCodeLit.cs index 74084a45..434e4da8 100644 --- a/src/ARMeilleure/Decoders/IOpCodeLit.cs +++ b/src/ARMeilleure/Decoders/IOpCodeLit.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders { interface IOpCodeLit : IOpCode { - int Rt { get; } + int Rt { get; } long Immediate { get; } - int Size { get; } - bool Signed { get; } - bool Prefetch { get; } + int Size { get; } + bool Signed { get; } + bool Prefetch { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeSimd.cs b/src/ARMeilleure/Decoders/IOpCodeSimd.cs index 056ef045..598d9d7f 100644 --- a/src/ARMeilleure/Decoders/IOpCodeSimd.cs +++ b/src/ARMeilleure/Decoders/IOpCodeSimd.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { int Size { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/InstDescriptor.cs b/src/ARMeilleure/Decoders/InstDescriptor.cs index 577ff394..c35c754a 100644 --- a/src/ARMeilleure/Decoders/InstDescriptor.cs +++ b/src/ARMeilleure/Decoders/InstDescriptor.cs @@ -4,15 +4,15 @@ namespace ARMeilleure.Decoders { readonly struct InstDescriptor { - public static InstDescriptor Undefined => new InstDescriptor(InstName.Und, InstEmit.Und); + public static InstDescriptor Undefined => new(InstName.Und, InstEmit.Und); - public InstName Name { get; } + public InstName Name { get; } public InstEmitter Emitter { get; } public InstDescriptor(InstName name, InstEmitter emitter) { - Name = name; + Name = name; Emitter = emitter; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/InstEmitter.cs b/src/ARMeilleure/Decoders/InstEmitter.cs index a8b52656..43bfcdca 100644 --- a/src/ARMeilleure/Decoders/InstEmitter.cs +++ b/src/ARMeilleure/Decoders/InstEmitter.cs @@ -3,4 +3,4 @@ using ARMeilleure.Translation; namespace ARMeilleure.Decoders { delegate void InstEmitter(ArmEmitterContext context); -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IntType.cs b/src/ARMeilleure/Decoders/IntType.cs index 244e9680..937a569a 100644 --- a/src/ARMeilleure/Decoders/IntType.cs +++ b/src/ARMeilleure/Decoders/IntType.cs @@ -2,13 +2,13 @@ namespace ARMeilleure.Decoders { enum IntType { - UInt8 = 0, + UInt8 = 0, UInt16 = 1, UInt32 = 2, UInt64 = 3, - Int8 = 4, - Int16 = 5, - Int32 = 6, - Int64 = 7 + Int8 = 4, + Int16 = 5, + Int32 = 6, + Int64 = 7, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode.cs b/src/ARMeilleure/Decoders/OpCode.cs index f9aed792..c8123308 100644 --- a/src/ARMeilleure/Decoders/OpCode.cs +++ b/src/ARMeilleure/Decoders/OpCode.cs @@ -5,8 +5,8 @@ namespace ARMeilleure.Decoders { class OpCode : IOpCode { - public ulong Address { get; } - public int RawOpCode { get; } + public ulong Address { get; } + public int RawOpCode { get; } public int OpCodeSizeInBytes { get; protected set; } = 4; @@ -14,13 +14,13 @@ namespace ARMeilleure.Decoders public RegisterSize RegisterSize { get; protected set; } - public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode); + public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new(inst, address, opCode); public OpCode(InstDescriptor inst, ulong address, int opCode) { Instruction = inst; - Address = address; - RawOpCode = opCode; + Address = address; + RawOpCode = opCode; RegisterSize = RegisterSize.Int64; } @@ -30,15 +30,14 @@ namespace ARMeilleure.Decoders public int GetBitsCount() { - switch (RegisterSize) + return RegisterSize switch { - case RegisterSize.Int32: return 32; - case RegisterSize.Int64: return 64; - case RegisterSize.Simd64: return 64; - case RegisterSize.Simd128: return 128; - } - - throw new InvalidOperationException(); + RegisterSize.Int32 => 32, + RegisterSize.Int64 => 64, + RegisterSize.Simd64 => 64, + RegisterSize.Simd128 => 128, + _ => throw new InvalidOperationException(), + }; } public OperandType GetOperandType() @@ -46,4 +45,4 @@ namespace ARMeilleure.Decoders return RegisterSize == RegisterSize.Int32 ? OperandType.I32 : OperandType.I64; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32.cs b/src/ARMeilleure/Decoders/OpCode32.cs index c2f14145..a2be01e9 100644 --- a/src/ARMeilleure/Decoders/OpCode32.cs +++ b/src/ARMeilleure/Decoders/OpCode32.cs @@ -31,4 +31,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Alu.cs b/src/ARMeilleure/Decoders/OpCode32Alu.cs index 1625aee0..8634f5ce 100644 --- a/src/ARMeilleure/Decoders/OpCode32Alu.cs +++ b/src/ARMeilleure/Decoders/OpCode32Alu.cs @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders SetFlags = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32AluImm.cs b/src/ARMeilleure/Decoders/OpCode32AluImm.cs index b5435aaf..c8b05e6b 100644 --- a/src/ARMeilleure/Decoders/OpCode32AluImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32AluImm.cs @@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders IsRotated = shift != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs b/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs index c2dee6c9..4b2c5897 100644 --- a/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs @@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders { class OpCode32AluRsImm : OpCode32Alu, IOpCode32AluRsImm { - public int Rm { get; } + public int Rm { get; } public int Immediate { get; } public ShiftType ShiftType { get; } @@ -11,10 +11,10 @@ namespace ARMeilleure.Decoders public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rm = (opCode >> 0) & 0xf; + Rm = (opCode >> 0) & 0xf; Immediate = (opCode >> 7) & 0x1f; ShiftType = (ShiftType)((opCode >> 5) & 3); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32BImm.cs b/src/ARMeilleure/Decoders/OpCode32BImm.cs index f2959b33..e7f5d6db 100644 --- a/src/ARMeilleure/Decoders/OpCode32BImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32BImm.cs @@ -26,4 +26,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32BReg.cs b/src/ARMeilleure/Decoders/OpCode32BReg.cs index d4f5f760..8939c0de 100644 --- a/src/ARMeilleure/Decoders/OpCode32BReg.cs +++ b/src/ARMeilleure/Decoders/OpCode32BReg.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Rm = opCode & 0xf; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Mem.cs b/src/ARMeilleure/Decoders/OpCode32Mem.cs index ceb1e49f..8a242199 100644 --- a/src/ARMeilleure/Decoders/OpCode32Mem.cs +++ b/src/ARMeilleure/Decoders/OpCode32Mem.cs @@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders public int Immediate { get; protected set; } - public bool Index { get; } - public bool Add { get; } - public bool WBack { get; } + public bool Index { get; } + public bool Add { get; } + public bool WBack { get; } public bool Unprivileged { get; } public bool IsLoad { get; } @@ -24,16 +24,16 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; bool isLoad = (opCode & (1 << 20)) != 0; - bool w = (opCode & (1 << 21)) != 0; - bool u = (opCode & (1 << 23)) != 0; - bool p = (opCode & (1 << 24)) != 0; + bool w = (opCode & (1 << 21)) != 0; + bool u = (opCode & (1 << 23)) != 0; + bool p = (opCode & (1 << 24)) != 0; - Index = p; - Add = u; - WBack = !p || w; + Index = p; + Add = u; + WBack = !p || w; Unprivileged = !p && w; IsLoad = isLoad || inst.Name == InstName.Ldrd; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32MemImm.cs b/src/ARMeilleure/Decoders/OpCode32MemImm.cs index 3af4b6f7..fa10e04e 100644 --- a/src/ARMeilleure/Decoders/OpCode32MemImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32MemImm.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders Immediate = opCode & 0xfff; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32MemImm8.cs b/src/ARMeilleure/Decoders/OpCode32MemImm8.cs index 1b8a57de..248ee8e6 100644 --- a/src/ARMeilleure/Decoders/OpCode32MemImm8.cs +++ b/src/ARMeilleure/Decoders/OpCode32MemImm8.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders Immediate = imm4L | (imm4H << 4); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32MemMult.cs b/src/ARMeilleure/Decoders/OpCode32MemMult.cs index 522b96bb..6e39e347 100644 --- a/src/ARMeilleure/Decoders/OpCode32MemMult.cs +++ b/src/ARMeilleure/Decoders/OpCode32MemMult.cs @@ -7,8 +7,8 @@ namespace ARMeilleure.Decoders public int Rn { get; } public int RegisterMask { get; } - public int Offset { get; } - public int PostOffset { get; } + public int Offset { get; } + public int PostOffset { get; } public bool IsLoad { get; } @@ -19,9 +19,9 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; bool isLoad = (opCode & (1 << 20)) != 0; - bool w = (opCode & (1 << 21)) != 0; - bool u = (opCode & (1 << 23)) != 0; - bool p = (opCode & (1 << 24)) != 0; + bool w = (opCode & (1 << 21)) != 0; + bool u = (opCode & (1 << 23)) != 0; + bool p = (opCode & (1 << 24)) != 0; RegisterMask = opCode & 0xffff; @@ -49,4 +49,4 @@ namespace ARMeilleure.Decoders IsLoad = isLoad; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Mrs.cs b/src/ARMeilleure/Decoders/OpCode32Mrs.cs index c34a8b99..b681b54c 100644 --- a/src/ARMeilleure/Decoders/OpCode32Mrs.cs +++ b/src/ARMeilleure/Decoders/OpCode32Mrs.cs @@ -2,8 +2,8 @@ namespace ARMeilleure.Decoders { class OpCode32Mrs : OpCode32 { - public bool R { get; } - public int Rd { get; } + public bool R { get; } + public int Rd { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mrs(inst, address, opCode); diff --git a/src/ARMeilleure/Decoders/OpCode32MsrReg.cs b/src/ARMeilleure/Decoders/OpCode32MsrReg.cs index d897ffd8..7186ebf7 100644 --- a/src/ARMeilleure/Decoders/OpCode32MsrReg.cs +++ b/src/ARMeilleure/Decoders/OpCode32MsrReg.cs @@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders { class OpCode32MsrReg : OpCode32 { - public bool R { get; } - public int Mask { get; } - public int Rd { get; } + public bool R { get; } + public int Mask { get; } + public int Rd { get; } public bool Banked { get; } - public int Rn { get; } + public int Rn { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MsrReg(inst, address, opCode); diff --git a/src/ARMeilleure/Decoders/OpCode32Sat.cs b/src/ARMeilleure/Decoders/OpCode32Sat.cs index 621def27..35c5cf47 100644 --- a/src/ARMeilleure/Decoders/OpCode32Sat.cs +++ b/src/ARMeilleure/Decoders/OpCode32Sat.cs @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders ShiftType = (ShiftType)((opCode >> 5) & 2); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Sat16.cs b/src/ARMeilleure/Decoders/OpCode32Sat16.cs index 51061b07..01f4d3b2 100644 --- a/src/ARMeilleure/Decoders/OpCode32Sat16.cs +++ b/src/ARMeilleure/Decoders/OpCode32Sat16.cs @@ -15,4 +15,4 @@ namespace ARMeilleure.Decoders SatImm = (opCode >> 16) & 0xf; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32SimdBase.cs b/src/ARMeilleure/Decoders/OpCode32SimdBase.cs index 4382fc2a..2361ac1e 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdBase.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdBase.cs @@ -24,27 +24,21 @@ namespace ARMeilleure.Decoders protected int GetQuadwordIndex(int index) { - switch (RegisterSize) + return RegisterSize switch { - case RegisterSize.Simd128: - case RegisterSize.Simd64: - return index >> 1; - } - - throw new InvalidOperationException(); + RegisterSize.Simd128 or RegisterSize.Simd64 => index >> 1, + _ => throw new InvalidOperationException(), + }; } protected int GetQuadwordSubindex(int index) { - switch (RegisterSize) + return RegisterSize switch { - case RegisterSize.Simd128: - return 0; - case RegisterSize.Simd64: - return index & 1; - } - - throw new InvalidOperationException(); + RegisterSize.Simd128 => 0, + RegisterSize.Simd64 => index & 1, + _ => throw new InvalidOperationException(), + }; } protected OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode) diff --git a/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs b/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs index a95b32ab..d3beb4bf 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs @@ -15,8 +15,8 @@ namespace ARMeilleure.Decoders { IsThumb = isThumb; - Op = ((opCode >> 16) & 0x1) != 0; - T = ((opCode >> 7) & 0x1) != 0; + Op = ((opCode >> 16) & 0x1) != 0; + T = ((opCode >> 7) & 0x1) != 0; Size = ((opCode >> 8) & 0x1); RegisterSize = Size == 1 ? RegisterSize.Int64 : RegisterSize.Int32; @@ -41,4 +41,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32SimdLong.cs b/src/ARMeilleure/Decoders/OpCode32SimdLong.cs index 8d64d673..558771a3 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdLong.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdLong.cs @@ -14,9 +14,15 @@ // The value must be a power of 2, otherwise it is the encoding of another instruction. switch (imm3h) { - case 1: Size = 0; break; - case 2: Size = 1; break; - case 4: Size = 2; break; + case 1: + Size = 0; + break; + case 2: + Size = 1; + break; + case 4: + Size = 2; + break; } U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0; diff --git a/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs b/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs index da88eed2..325be4ec 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs @@ -4,12 +4,12 @@ namespace ARMeilleure.Decoders { class OpCode32SimdMemPair : OpCode32, IOpCode32Simd { - private static int[] _regsMap = + private static readonly int[] _regsMap = { 1, 1, 4, 2, 1, 1, 3, 1, 1, 1, 2, 1, - 1, 1, 1, 1 + 1, 1, 1, 1, }; public int Vd { get; } diff --git a/src/ARMeilleure/Decoders/OpCode32SimdSel.cs b/src/ARMeilleure/Decoders/OpCode32SimdSel.cs index bd4865ea..cb28418c 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdSel.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdSel.cs @@ -18,6 +18,6 @@ Eq = 0, Vs, Ge, - Gt + Gt, } } diff --git a/src/ARMeilleure/Decoders/OpCodeAdr.cs b/src/ARMeilleure/Decoders/OpCodeAdr.cs index 9655c766..08028040 100644 --- a/src/ARMeilleure/Decoders/OpCodeAdr.cs +++ b/src/ARMeilleure/Decoders/OpCodeAdr.cs @@ -6,14 +6,14 @@ namespace ARMeilleure.Decoders public long Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode); public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = opCode & 0x1f; - Immediate = DecoderHelper.DecodeImmS19_2(opCode); + Immediate = DecoderHelper.DecodeImmS19_2(opCode); Immediate |= ((long)opCode >> 29) & 3; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAlu.cs b/src/ARMeilleure/Decoders/OpCodeAlu.cs index 4d7f03a7..1619ecd8 100644 --- a/src/ARMeilleure/Decoders/OpCodeAlu.cs +++ b/src/ARMeilleure/Decoders/OpCodeAlu.cs @@ -11,8 +11,8 @@ namespace ARMeilleure.Decoders public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x1f; - Rn = (opCode >> 5) & 0x1f; + Rd = (opCode >> 0) & 0x1f; + Rn = (opCode >> 5) & 0x1f; DataOp = (DataOp)((opCode >> 24) & 0x3); RegisterSize = (opCode >> 31) != 0 @@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluBinary.cs b/src/ARMeilleure/Decoders/OpCodeAluBinary.cs index e8b10656..4413581c 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluBinary.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluBinary.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluImm.cs b/src/ARMeilleure/Decoders/OpCodeAluImm.cs index 91aa9553..0d2f7202 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluImm.cs @@ -33,8 +33,8 @@ namespace ARMeilleure.Decoders } else { - throw new ArgumentException(nameof(opCode)); + throw new ArgumentException($"Invalid data operation: {DataOp}", nameof(opCode)); } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluRs.cs b/src/ARMeilleure/Decoders/OpCodeAluRs.cs index 94983336..47a47e7d 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluRs.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluRs.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs { public int Shift { get; } - public int Rm { get; } + public int Rm { get; } public ShiftType ShiftType { get; } @@ -22,8 +22,8 @@ namespace ARMeilleure.Decoders Shift = shift; - Rm = (opCode >> 16) & 0x1f; + Rm = (opCode >> 16) & 0x1f; ShiftType = (ShiftType)((opCode >> 22) & 0x3); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluRx.cs b/src/ARMeilleure/Decoders/OpCodeAluRx.cs index d39da9e7..c2148678 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluRx.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluRx.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx { public int Shift { get; } - public int Rm { get; } + public int Rm { get; } public IntType IntType { get; } @@ -11,9 +11,9 @@ namespace ARMeilleure.Decoders public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Shift = (opCode >> 10) & 0x7; + Shift = (opCode >> 10) & 0x7; IntType = (IntType)((opCode >> 13) & 0x7); - Rm = (opCode >> 16) & 0x1f; + Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImm.cs b/src/ARMeilleure/Decoders/OpCodeBImm.cs index e302516e..2848c140 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImm.cs @@ -8,4 +8,4 @@ namespace ARMeilleure.Decoders public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmAl.cs b/src/ARMeilleure/Decoders/OpCodeBImmAl.cs index 47ae5f56..6c4b28c6 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmAl.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmAl.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs b/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs index a5246569..c477ddec 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmCond.cs b/src/ARMeilleure/Decoders/OpCodeBImmCond.cs index b57a7ea8..7a51a072 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmCond.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmCond.cs @@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders Immediate = (long)address + DecoderHelper.DecodeImmS19_2(opCode); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmTest.cs b/src/ARMeilleure/Decoders/OpCodeBImmTest.cs index bad98405..f989e59e 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmTest.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmTest.cs @@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders { class OpCodeBImmTest : OpCodeBImm { - public int Rt { get; } + public int Rt { get; } public int Bit { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode); @@ -13,8 +13,8 @@ namespace ARMeilleure.Decoders Immediate = (long)address + DecoderHelper.DecodeImmS14_2(opCode); - Bit = (opCode >> 19) & 0x1f; + Bit = (opCode >> 19) & 0x1f; Bit |= (opCode >> 26) & 0x20; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBReg.cs b/src/ARMeilleure/Decoders/OpCodeBReg.cs index b5dcbfd8..3b84cf5c 100644 --- a/src/ARMeilleure/Decoders/OpCodeBReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeBReg.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Decoders public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - int op4 = (opCode >> 0) & 0x1f; + int op4 = (opCode >> 0) & 0x1f; int op2 = (opCode >> 16) & 0x1f; if (op2 != 0b11111 || op4 != 0b00000) @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 5) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBfm.cs b/src/ARMeilleure/Decoders/OpCodeBfm.cs index 8e1c7836..d51efade 100644 --- a/src/ARMeilleure/Decoders/OpCodeBfm.cs +++ b/src/ARMeilleure/Decoders/OpCodeBfm.cs @@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders { public long WMask { get; } public long TMask { get; } - public int Pos { get; } - public int Shift { get; } + public int Pos { get; } + public int Shift { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode); @@ -22,8 +22,8 @@ namespace ARMeilleure.Decoders WMask = bm.WMask; TMask = bm.TMask; - Pos = bm.Pos; + Pos = bm.Pos; Shift = bm.Shift; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCcmp.cs b/src/ARMeilleure/Decoders/OpCodeCcmp.cs index aa47146f..d4035348 100644 --- a/src/ARMeilleure/Decoders/OpCodeCcmp.cs +++ b/src/ARMeilleure/Decoders/OpCodeCcmp.cs @@ -4,7 +4,7 @@ namespace ARMeilleure.Decoders { class OpCodeCcmp : OpCodeAlu, IOpCodeCond { - public int Nzcv { get; } + public int Nzcv { get; } protected int RmImm; public Condition Cond { get; } @@ -22,11 +22,11 @@ namespace ARMeilleure.Decoders return; } - Nzcv = (opCode >> 0) & 0xf; - Cond = (Condition)((opCode >> 12) & 0xf); - RmImm = (opCode >> 16) & 0x1f; + Nzcv = (opCode >> 0) & 0xf; + Cond = (Condition)((opCode >> 12) & 0xf); + RmImm = (opCode >> 16) & 0x1f; Rd = RegisterAlias.Zr; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs b/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs index 3548f2da..9d6acf19 100644 --- a/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs @@ -8,4 +8,4 @@ namespace ARMeilleure.Decoders public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs b/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs index d5df3b10..349afa12 100644 --- a/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCsel.cs b/src/ARMeilleure/Decoders/OpCodeCsel.cs index 4b8dc7fd..418962e0 100644 --- a/src/ARMeilleure/Decoders/OpCodeCsel.cs +++ b/src/ARMeilleure/Decoders/OpCodeCsel.cs @@ -10,8 +10,8 @@ namespace ARMeilleure.Decoders public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rm = (opCode >> 16) & 0x1f; + Rm = (opCode >> 16) & 0x1f; Cond = (Condition)((opCode >> 12) & 0xf); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeException.cs b/src/ARMeilleure/Decoders/OpCodeException.cs index 6b72138e..eee63640 100644 --- a/src/ARMeilleure/Decoders/OpCodeException.cs +++ b/src/ARMeilleure/Decoders/OpCodeException.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Id = (opCode >> 5) & 0xffff; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMem.cs b/src/ARMeilleure/Decoders/OpCodeMem.cs index 0ba2bcd1..9b4e5ff3 100644 --- a/src/ARMeilleure/Decoders/OpCodeMem.cs +++ b/src/ARMeilleure/Decoders/OpCodeMem.cs @@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders { class OpCodeMem : OpCode { - public int Rt { get; protected set; } - public int Rn { get; protected set; } - public int Size { get; protected set; } + public int Rt { get; protected set; } + public int Rn { get; protected set; } + public int Size { get; protected set; } public bool Extend64 { get; protected set; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode); public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rt = (opCode >> 0) & 0x1f; - Rn = (opCode >> 5) & 0x1f; + Rt = (opCode >> 0) & 0x1f; + Rn = (opCode >> 5) & 0x1f; Size = (opCode >> 30) & 0x3; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemEx.cs b/src/ARMeilleure/Decoders/OpCodeMemEx.cs index 89902485..1dc73140 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemEx.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemEx.cs @@ -3,14 +3,14 @@ namespace ARMeilleure.Decoders class OpCodeMemEx : OpCodeMem { public int Rt2 { get; } - public int Rs { get; } + public int Rs { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode); public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt2 = (opCode >> 10) & 0x1f; - Rs = (opCode >> 16) & 0x1f; + Rs = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemImm.cs b/src/ARMeilleure/Decoders/OpCodeMemImm.cs index d6ed2282..4d5eeb1e 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemImm.cs @@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders { class OpCodeMemImm : OpCodeMem { - public long Immediate { get; protected set; } - public bool WBack { get; protected set; } - public bool PostIdx { get; protected set; } - protected bool Unscaled { get; } + public long Immediate { get; protected set; } + public bool WBack { get; protected set; } + public bool PostIdx { get; protected set; } + protected bool Unscaled { get; } private enum MemOp { - Unscaled = 0, - PostIndexed = 1, + Unscaled = 0, + PostIndexed = 1, Unprivileged = 2, - PreIndexed = 3, - Unsigned + PreIndexed = 3, + Unsigned, } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode); @@ -21,13 +21,13 @@ namespace ARMeilleure.Decoders public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Extend64 = ((opCode >> 22) & 3) == 2; - WBack = ((opCode >> 24) & 1) == 0; + WBack = ((opCode >> 24) & 1) == 0; // The type is not valid for the Unsigned Immediate 12-bits encoding, // because the bits 11:10 are used for the larger Immediate offset. MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned; - PostIdx = type == MemOp.PostIndexed; + PostIdx = type == MemOp.PostIndexed; Unscaled = type == MemOp.Unscaled || type == MemOp.Unprivileged; @@ -50,4 +50,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemLit.cs b/src/ARMeilleure/Decoders/OpCodeMemLit.cs index 986d6634..8712a78e 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemLit.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemLit.cs @@ -2,11 +2,11 @@ namespace ARMeilleure.Decoders { class OpCodeMemLit : OpCode, IOpCodeLit { - public int Rt { get; } + public int Rt { get; } public long Immediate { get; } - public int Size { get; } - public bool Signed { get; } - public bool Prefetch { get; } + public int Size { get; } + public bool Signed { get; } + public bool Prefetch { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode); @@ -18,11 +18,27 @@ namespace ARMeilleure.Decoders switch ((opCode >> 30) & 3) { - case 0: Size = 2; Signed = false; Prefetch = false; break; - case 1: Size = 3; Signed = false; Prefetch = false; break; - case 2: Size = 2; Signed = true; Prefetch = false; break; - case 3: Size = 0; Signed = false; Prefetch = true; break; + case 0: + Size = 2; + Signed = false; + Prefetch = false; + break; + case 1: + Size = 3; + Signed = false; + Prefetch = false; + break; + case 2: + Size = 2; + Signed = true; + Prefetch = false; + break; + case 3: + Size = 0; + Signed = false; + Prefetch = true; + break; } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemPair.cs b/src/ARMeilleure/Decoders/OpCodeMemPair.cs index 21018033..eb696cfe 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemPair.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemPair.cs @@ -8,11 +8,11 @@ namespace ARMeilleure.Decoders public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rt2 = (opCode >> 10) & 0x1f; - WBack = ((opCode >> 23) & 0x1) != 0; - PostIdx = ((opCode >> 23) & 0x3) == 1; + Rt2 = (opCode >> 10) & 0x1f; + WBack = ((opCode >> 23) & 0x1) != 0; + PostIdx = ((opCode >> 23) & 0x3) == 1; Extend64 = ((opCode >> 30) & 0x3) == 1; - Size = ((opCode >> 31) & 0x1) | 2; + Size = ((opCode >> 31) & 0x1) | 2; DecodeImm(opCode); } @@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders Immediate = ((long)(opCode >> 15) << 57) >> (57 - Size); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemReg.cs b/src/ARMeilleure/Decoders/OpCodeMemReg.cs index 73d6c5d2..9b0d1595 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemReg.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders class OpCodeMemReg : OpCodeMem { public bool Shift { get; } - public int Rm { get; } + public int Rm { get; } public IntType IntType { get; } @@ -11,10 +11,10 @@ namespace ARMeilleure.Decoders public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Shift = ((opCode >> 12) & 0x1) != 0; - IntType = (IntType)((opCode >> 13) & 0x7); - Rm = (opCode >> 16) & 0x1f; - Extend64 = ((opCode >> 22) & 0x3) == 2; + Shift = ((opCode >> 12) & 0x1) != 0; + IntType = (IntType)((opCode >> 13) & 0x7); + Rm = (opCode >> 16) & 0x1f; + Extend64 = ((opCode >> 22) & 0x3) == 2; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMov.cs b/src/ARMeilleure/Decoders/OpCodeMov.cs index 50af88cb..a2914b71 100644 --- a/src/ARMeilleure/Decoders/OpCodeMov.cs +++ b/src/ARMeilleure/Decoders/OpCodeMov.cs @@ -22,9 +22,9 @@ namespace ARMeilleure.Decoders return; } - Rd = (opCode >> 0) & 0x1f; - Immediate = (opCode >> 5) & 0xffff; - Bit = (opCode >> 21) & 0x3; + Rd = (opCode >> 0) & 0x1f; + Immediate = (opCode >> 5) & 0xffff; + Bit = (opCode >> 21) & 0x3; Bit <<= 4; @@ -35,4 +35,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMul.cs b/src/ARMeilleure/Decoders/OpCodeMul.cs index 31d140a6..9b1dd37b 100644 --- a/src/ARMeilleure/Decoders/OpCodeMul.cs +++ b/src/ARMeilleure/Decoders/OpCodeMul.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimd.cs b/src/ARMeilleure/Decoders/OpCodeSimd.cs index 85713690..bd34d74d 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimd.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimd.cs @@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders { class OpCodeSimd : OpCode, IOpCodeSimd { - public int Rd { get; } - public int Rn { get; } - public int Opc { get; } + public int Rd { get; } + public int Rn { get; } + public int Opc { get; } public int Size { get; protected set; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode); public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x1f; - Rn = (opCode >> 5) & 0x1f; - Opc = (opCode >> 15) & 0x3; + Rd = (opCode >> 0) & 0x1f; + Rn = (opCode >> 5) & 0x1f; + Opc = (opCode >> 15) & 0x3; Size = (opCode >> 22) & 0x3; RegisterSize = ((opCode >> 30) & 1) != 0 @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Simd64; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs b/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs index 05b32941..e50cf12e 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs @@ -9,7 +9,7 @@ namespace ARMeilleure.Decoders public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int scale = (opCode >> 10) & 0x3f; - int sf = (opCode >> 31) & 0x1; + int sf = (opCode >> 31) & 0x1; FBits = 64 - scale; @@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdExt.cs b/src/ARMeilleure/Decoders/OpCodeSimdExt.cs index a0e264d9..0a3359e1 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdExt.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdExt.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Imm4 = (opCode >> 11) & 0xf; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs b/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs index aa16e0c1..510cd310 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs @@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Nzcv = (opCode >> 0) & 0xf; + Nzcv = (opCode >> 0) & 0xf; Cond = (Condition)((opCode >> 12) & 0xf); } } diff --git a/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs b/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs index 9f9062b8..662abe28 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { class OpCodeSimdFmov : OpCode, IOpCodeSimd { - public int Rd { get; } + public int Rd { get; } public long Immediate { get; } - public int Size { get; } + public int Size { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode); @@ -16,7 +16,7 @@ namespace ARMeilleure.Decoders long imm; - Rd = (opCode >> 0) & 0x1f; + Rd = (opCode >> 0) & 0x1f; imm = (opCode >> 13) & 0xff; if (type == 0) @@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs b/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs index 02f74d03..d900ed9b 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs @@ -52,17 +52,20 @@ else if ((modeHigh & 0b110) == 0b100) { // 16-bits shifted Immediate. - size = 1; imm <<= (modeHigh & 1) << 3; + size = 1; + imm <<= (modeHigh & 1) << 3; } else if ((modeHigh & 0b100) == 0b000) { // 32-bits shifted Immediate. - size = 2; imm <<= modeHigh << 3; + size = 2; + imm <<= modeHigh << 3; } else if ((modeHigh & 0b111) == 0b110) { // 32-bits shifted Immediate (fill with ones). - size = 2; imm = ShlOnes(imm, 8 << modeLow); + size = 2; + imm = ShlOnes(imm, 8 << modeLow); } else { diff --git a/src/ARMeilleure/Decoders/OpCodeSimdImm.cs b/src/ARMeilleure/Decoders/OpCodeSimdImm.cs index eeca7709..3f4bad7f 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdImm.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { class OpCodeSimdImm : OpCode, IOpCodeSimd { - public int Rd { get; } + public int Rd { get; } public long Immediate { get; } - public int Size { get; } + public int Size { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode); @@ -13,14 +13,14 @@ namespace ARMeilleure.Decoders Rd = opCode & 0x1f; int cMode = (opCode >> 12) & 0xf; - int op = (opCode >> 29) & 0x1; + int op = (opCode >> 29) & 0x1; - int modeLow = cMode & 1; + int modeLow = cMode & 1; int modeHigh = cMode >> 1; long imm; - imm = ((uint)opCode >> 5) & 0x1f; + imm = ((uint)opCode >> 5) & 0x1f; imm |= ((uint)opCode >> 11) & 0xe0; if (modeHigh == 0b111) @@ -67,17 +67,20 @@ namespace ARMeilleure.Decoders else if ((modeHigh & 0b110) == 0b100) { // 16-bits shifted Immediate. - Size = 1; imm <<= (modeHigh & 1) << 3; + Size = 1; + imm <<= (modeHigh & 1) << 3; } else if ((modeHigh & 0b100) == 0b000) { // 32-bits shifted Immediate. - Size = 2; imm <<= modeHigh << 3; + Size = 2; + imm <<= modeHigh << 3; } else if ((modeHigh & 0b111) == 0b110) { // 32-bits shifted Immediate (fill with ones). - Size = 2; imm = ShlOnes(imm, 8 << modeLow); + Size = 2; + imm = ShlOnes(imm, 8 << modeLow); } else { @@ -104,4 +107,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdIns.cs b/src/ARMeilleure/Decoders/OpCodeSimdIns.cs index f6f9249d..95436879 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdIns.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdIns.cs @@ -23,14 +23,22 @@ namespace ARMeilleure.Decoders switch (Size) { - case 1: Size = 0; break; - case 2: Size = 1; break; - case 4: Size = 2; break; - case 8: Size = 3; break; + case 1: + Size = 0; + break; + case 2: + Size = 1; + break; + case 4: + Size = 2; + break; + case 8: + Size = 3; + break; } - SrcIndex = imm4 >> Size; + SrcIndex = imm4 >> Size; DstIndex = imm5 >> (Size + 1); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs index c11594cb..14a9d7c9 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs @@ -25,4 +25,4 @@ namespace ARMeilleure.Decoders Extend64 = false; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs index 8e212966..efa558bf 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemLit : OpCode, IOpCodeSimd, IOpCodeLit { - public int Rt { get; } + public int Rt { get; } public long Immediate { get; } - public int Size { get; } - public bool Signed => false; + public int Size { get; } + public bool Signed => false; public bool Prefetch => false; public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode); @@ -28,4 +28,4 @@ namespace ARMeilleure.Decoders Size = opc + 2; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs index 8922c18f..c05b5249 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd { - public int Reps { get; } - public int SElems { get; } - public int Elems { get; } - public bool WBack { get; } + public int Reps { get; } + public int SElems { get; } + public int Elems { get; } + public bool WBack { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode); @@ -13,18 +13,41 @@ namespace ARMeilleure.Decoders { switch ((opCode >> 12) & 0xf) { - case 0b0000: Reps = 1; SElems = 4; break; - case 0b0010: Reps = 4; SElems = 1; break; - case 0b0100: Reps = 1; SElems = 3; break; - case 0b0110: Reps = 3; SElems = 1; break; - case 0b0111: Reps = 1; SElems = 1; break; - case 0b1000: Reps = 1; SElems = 2; break; - case 0b1010: Reps = 2; SElems = 1; break; + case 0b0000: + Reps = 1; + SElems = 4; + break; + case 0b0010: + Reps = 4; + SElems = 1; + break; + case 0b0100: + Reps = 1; + SElems = 3; + break; + case 0b0110: + Reps = 3; + SElems = 1; + break; + case 0b0111: + Reps = 1; + SElems = 1; + break; + case 0b1000: + Reps = 1; + SElems = 2; + break; + case 0b1010: + Reps = 2; + SElems = 1; + break; - default: Instruction = InstDescriptor.Undefined; return; + default: + Instruction = InstDescriptor.Undefined; + return; } - Size = (opCode >> 10) & 3; + Size = (opCode >> 10) & 3; WBack = ((opCode >> 23) & 1) != 0; bool q = ((opCode >> 30) & 1) != 0; @@ -45,4 +68,4 @@ namespace ARMeilleure.Decoders Elems = (GetBitsCount() >> 3) >> Size; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs index 1ab95367..69716389 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders DecodeImm(opCode); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs index 9ea6dda3..be7b25b9 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs @@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders Extend64 = false; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs index 44abdd38..5bc614e1 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs @@ -2,21 +2,21 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd { - public int SElems { get; } - public int Index { get; } + public int SElems { get; } + public int Index { get; } public bool Replicate { get; } - public bool WBack { get; } + public bool WBack { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode); public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - int size = (opCode >> 10) & 3; - int s = (opCode >> 12) & 1; + int size = (opCode >> 10) & 3; + int s = (opCode >> 12) & 1; int sElems = (opCode >> 12) & 2; - int scale = (opCode >> 14) & 3; - int l = (opCode >> 22) & 1; - int q = (opCode >> 30) & 1; + int scale = (opCode >> 14) & 3; + int l = (opCode >> 22) & 1; + int q = (opCode >> 30) & 1; sElems |= (opCode >> 21) & 1; @@ -27,63 +27,63 @@ namespace ARMeilleure.Decoders switch (scale) { case 1: - { - if ((size & 1) != 0) { - Instruction = InstDescriptor.Undefined; + if ((size & 1) != 0) + { + Instruction = InstDescriptor.Undefined; - return; + return; + } + + index >>= 1; + + break; } - index >>= 1; - - break; - } - case 2: - { - if ((size & 2) != 0 || - ((size & 1) != 0 && s != 0)) { - Instruction = InstDescriptor.Undefined; + if ((size & 2) != 0 || + ((size & 1) != 0 && s != 0)) + { + Instruction = InstDescriptor.Undefined; - return; + return; + } + + if ((size & 1) != 0) + { + index >>= 3; + + scale = 3; + } + else + { + index >>= 2; + } + + break; } - if ((size & 1) != 0) - { - index >>= 3; - - scale = 3; - } - else - { - index >>= 2; - } - - break; - } - case 3: - { - if (l == 0 || s != 0) { - Instruction = InstDescriptor.Undefined; + if (l == 0 || s != 0) + { + Instruction = InstDescriptor.Undefined; - return; + return; + } + + scale = size; + + Replicate = true; + + break; } - - scale = size; - - Replicate = true; - - break; - } } - Index = index; + Index = index; SElems = sElems; - Size = scale; + Size = scale; Extend64 = false; @@ -94,4 +94,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Simd64; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdReg.cs b/src/ARMeilleure/Decoders/OpCodeSimdReg.cs index ac4f71da..40f9b1c5 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdReg.cs @@ -3,16 +3,16 @@ namespace ARMeilleure.Decoders class OpCodeSimdReg : OpCodeSimd { public bool Bit3 { get; } - public int Ra { get; } - public int Rm { get; protected set; } + public int Ra { get; } + public int Rm { get; protected set; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdReg(inst, address, opCode); public OpCodeSimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Bit3 = ((opCode >> 3) & 0x1) != 0; - Ra = (opCode >> 10) & 0x1f; - Rm = (opCode >> 16) & 0x1f; + Bit3 = ((opCode >> 3) & 0x1) != 0; + Ra = (opCode >> 10) & 0x1f; + Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs b/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs index 92368dee..bb248ab6 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs @@ -12,7 +12,7 @@ namespace ARMeilleure.Decoders { case 1: Index = (opCode >> 20) & 3 | - (opCode >> 9) & 4; + (opCode >> 9) & 4; Rm &= 0xf; @@ -24,8 +24,10 @@ namespace ARMeilleure.Decoders break; - default: Instruction = InstDescriptor.Undefined; break; + default: + Instruction = InstDescriptor.Undefined; + break; } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs b/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs index d46dd57e..c97bd787 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs @@ -26,7 +26,9 @@ namespace ARMeilleure.Decoders break; - default: Instruction = InstDescriptor.Undefined; break; + default: + Instruction = InstDescriptor.Undefined; + break; } } } diff --git a/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs b/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs index 9c631e48..3a7ef6ab 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders Size = ((opCode >> 13) & 3) + 1; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSystem.cs b/src/ARMeilleure/Decoders/OpCodeSystem.cs index 4d79421a..21513415 100644 --- a/src/ARMeilleure/Decoders/OpCodeSystem.cs +++ b/src/ARMeilleure/Decoders/OpCodeSystem.cs @@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders { class OpCodeSystem : OpCode { - public int Rt { get; } + public int Rt { get; } public int Op2 { get; } public int CRm { get; } public int CRn { get; } @@ -13,12 +13,12 @@ namespace ARMeilleure.Decoders public OpCodeSystem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rt = (opCode >> 0) & 0x1f; - Op2 = (opCode >> 5) & 0x7; - CRm = (opCode >> 8) & 0xf; - CRn = (opCode >> 12) & 0xf; - Op1 = (opCode >> 16) & 0x7; + Rt = (opCode >> 0) & 0x1f; + Op2 = (opCode >> 5) & 0x7; + CRm = (opCode >> 8) & 0xf; + CRn = (opCode >> 12) & 0xf; + Op1 = (opCode >> 16) & 0x7; Op0 = ((opCode >> 19) & 0x1) | 2; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT16.cs b/src/ARMeilleure/Decoders/OpCodeT16.cs index 9c3d6b00..de946b96 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders OpCodeSizeInBytes = 2; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs b/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs index 95f18054..cefb50e4 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs @@ -1,6 +1,6 @@ namespace ARMeilleure.Decoders { - class OpCodeT16AddSubImm3: OpCodeT16, IOpCode32AluImm + class OpCodeT16AddSubImm3 : OpCodeT16, IOpCode32AluImm { public int Rd { get; } public int Rn { get; } @@ -15,8 +15,8 @@ public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x7; - Rn = (opCode >> 3) & 0x7; + Rd = (opCode >> 0) & 0x7; + Rn = (opCode >> 3) & 0x7; Immediate = (opCode >> 6) & 0x7; IsRotated = false; } diff --git a/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs b/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs index f230b20e..fab098a8 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs @@ -8,7 +8,7 @@ public OpCodeT16BImm11(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - int imm = (opCode << 21) >> 20; + int imm = (opCode << 21) >> 20; Immediate = GetPc() + imm; } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs b/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs index 5f684298..edfa86ba 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs @@ -10,7 +10,7 @@ { Cond = (Condition)((opCode >> 8) & 0xf); - int imm = (opCode << 24) >> 23; + int imm = (opCode << 24) >> 23; Immediate = GetPc() + imm; } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs b/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs index 20ef31e2..873c63b9 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs @@ -36,23 +36,13 @@ namespace ARMeilleure.Decoders break; } - switch (inst.Name) + Immediate = inst.Name switch { - case InstName.Str: - case InstName.Ldr: - Immediate = ((opCode >> 6) & 0x1f) << 2; - break; - case InstName.Strb: - case InstName.Ldrb: - Immediate = ((opCode >> 6) & 0x1f); - break; - case InstName.Strh: - case InstName.Ldrh: - Immediate = ((opCode >> 6) & 0x1f) << 1; - break; - default: - throw new InvalidOperationException(); - } + InstName.Str or InstName.Ldr => ((opCode >> 6) & 0x1f) << 2, + InstName.Strb or InstName.Ldrb => ((opCode >> 6) & 0x1f), + InstName.Strh or InstName.Ldrh => ((opCode >> 6) & 0x1f) << 1, + _ => throw new InvalidOperationException(), + }; } } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs b/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs index f4185cfc..3f3057ac 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs @@ -27,7 +27,7 @@ namespace ARMeilleure.Decoders { InstName.Ldm => true, InstName.Stm => false, - _ => throw new InvalidOperationException() + _ => throw new InvalidOperationException(), }; } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs b/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs index a540026e..8f35e439 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs @@ -15,8 +15,8 @@ public OpCodeT16ShiftImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x7; - Rm = (opCode >> 3) & 0x7; + Rd = (opCode >> 0) & 0x7; + Rm = (opCode >> 3) & 0x7; Immediate = (opCode >> 6) & 0x1F; ShiftType = (ShiftType)((opCode >> 11) & 3); } diff --git a/src/ARMeilleure/Decoders/OpCodeT32.cs b/src/ARMeilleure/Decoders/OpCodeT32.cs index cf43d429..5ccbd6a2 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32.cs @@ -12,4 +12,4 @@ OpCodeSizeInBytes = 4; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32Alu.cs b/src/ARMeilleure/Decoders/OpCodeT32Alu.cs index a81b3b3d..1f92f755 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32Alu.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32Alu.cs @@ -17,4 +17,4 @@ SetFlags = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs b/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs index 0895c29b..863d14bd 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs @@ -35,4 +35,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs b/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs index 31de63dd..12b65a10 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs b/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs index a487f55a..4ac98347 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Rm = (opCode >> 0) & 0xf; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs b/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs index 1c9ba7a2..edf0298d 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs @@ -2,7 +2,7 @@ { class OpCodeT32AluRsImm : OpCodeT32Alu, IOpCode32AluRsImm { - public int Rm { get; } + public int Rm { get; } public int Immediate { get; } public ShiftType ShiftType { get; } @@ -11,10 +11,10 @@ public OpCodeT32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rm = (opCode >> 0) & 0xf; + Rm = (opCode >> 0) & 0xf; Immediate = ((opCode >> 6) & 3) | ((opCode >> 10) & 0x1c); ShiftType = (ShiftType)((opCode >> 4) & 3); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs b/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs index b6da8abd..13256ee5 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs @@ -24,4 +24,4 @@ Cond = (Condition)((opCode >> 22) & 0xf); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs b/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs index 774ec3a6..d7c60661 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs @@ -32,4 +32,4 @@ namespace ARMeilleure.Decoders Immediate = pc + imm32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs index 7838604b..4977cdf5 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs @@ -22,4 +22,4 @@ IsLoad = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs index d8b7763c..f84e4140 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs @@ -18,7 +18,7 @@ Rn = (opCode >> 16) & 0xf; Index = ((opCode >> 10) & 1) != 0; - Add = ((opCode >> 9) & 1) != 0; + Add = ((opCode >> 9) & 1) != 0; WBack = ((opCode >> 8) & 1) != 0; Immediate = opCode & 0xff; @@ -26,4 +26,4 @@ IsLoad = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs index 7a078c48..51f5042f 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs @@ -20,7 +20,7 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; Index = ((opCode >> 24) & 1) != 0; - Add = ((opCode >> 23) & 1) != 0; + Add = ((opCode >> 23) & 1) != 0; WBack = ((opCode >> 21) & 1) != 0; Immediate = (opCode & 0xff) << 2; @@ -28,4 +28,4 @@ namespace ARMeilleure.Decoders IsLoad = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs b/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs index a9ba306d..d155842a 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs @@ -7,8 +7,8 @@ namespace ARMeilleure.Decoders public int Rn { get; } public int RegisterMask { get; } - public int Offset { get; } - public int PostOffset { get; } + public int Offset { get; } + public int PostOffset { get; } public bool IsLoad { get; } @@ -19,9 +19,9 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; bool isLoad = (opCode & (1 << 20)) != 0; - bool w = (opCode & (1 << 21)) != 0; - bool u = (opCode & (1 << 23)) != 0; - bool p = (opCode & (1 << 24)) != 0; + bool w = (opCode & (1 << 21)) != 0; + bool u = (opCode & (1 << 23)) != 0; + bool p = (opCode & (1 << 24)) != 0; RegisterMask = opCode & 0xffff; @@ -49,4 +49,4 @@ namespace ARMeilleure.Decoders IsLoad = isLoad; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs b/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs index 5161892b..2f871c74 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs @@ -4,8 +4,6 @@ namespace ARMeilleure.Decoders { public int Immediate { get; } - public bool IsRotated => false; - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MovImm16(inst, address, opCode); public OpCodeT32MovImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) @@ -13,4 +11,4 @@ namespace ARMeilleure.Decoders Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800) | ((opCode >> 4) & 0xf000); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32Tb.cs b/src/ARMeilleure/Decoders/OpCodeT32Tb.cs index 527754b1..0a4d2a6c 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32Tb.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32Tb.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeTable.cs b/src/ARMeilleure/Decoders/OpCodeTable.cs index 4f359958..d3fc4ca0 100644 --- a/src/ARMeilleure/Decoders/OpCodeTable.cs +++ b/src/ARMeilleure/Decoders/OpCodeTable.cs @@ -13,7 +13,7 @@ namespace ARMeilleure.Decoders private readonly struct InstInfo { - public int Mask { get; } + public int Mask { get; } public int Value { get; } public InstDescriptor Inst { get; } @@ -22,24 +22,25 @@ namespace ARMeilleure.Decoders public InstInfo(int mask, int value, InstDescriptor inst, MakeOp makeOp) { - Mask = mask; - Value = value; - Inst = inst; + Mask = mask; + Value = value; + Inst = inst; MakeOp = makeOp; } } - private static List AllInstA32 = new(); - private static List AllInstT32 = new(); - private static List AllInstA64 = new(); + private static readonly List _allInstA32 = new(); + private static readonly List _allInstT32 = new(); + private static readonly List _allInstA64 = new(); - private static InstInfo[][] InstA32FastLookup = new InstInfo[FastLookupSize][]; - private static InstInfo[][] InstT32FastLookup = new InstInfo[FastLookupSize][]; - private static InstInfo[][] InstA64FastLookup = new InstInfo[FastLookupSize][]; + private static readonly InstInfo[][] _instA32FastLookup = new InstInfo[FastLookupSize][]; + private static readonly InstInfo[][] _instT32FastLookup = new InstInfo[FastLookupSize][]; + private static readonly InstInfo[][] _instA64FastLookup = new InstInfo[FastLookupSize][]; static OpCodeTable() { -#region "OpCode Table (AArch64)" +#pragma warning disable IDE0055 // Disable formatting + #region "OpCode Table (AArch64)" // Base SetA64("x0011010000xxxxx000000xxxxxxxxxx", InstName.Adc, InstEmit.Adc, OpCodeAluRs.Create); SetA64("x0111010000xxxxx000000xxxxxxxxxx", InstName.Adcs, InstEmit.Adcs, OpCodeAluRs.Create); @@ -638,9 +639,9 @@ namespace ARMeilleure.Decoders SetA64("0x001110<<100001001010xxxxxxxxxx", InstName.Xtn_V, InstEmit.Xtn_V, OpCodeSimd.Create); SetA64("0>001110<<0xxxxx001110xxxxxxxxxx", InstName.Zip1_V, InstEmit.Zip1_V, OpCodeSimdReg.Create); SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", InstName.Zip2_V, InstEmit.Zip2_V, OpCodeSimdReg.Create); -#endregion + #endregion -#region "OpCode Table (AArch32, A32)" + #region "OpCode Table (AArch32, A32)" // Base SetA32("<<<<0010101xxxxxxxxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluImm.Create); SetA32("<<<<0000101xxxxxxxxxxxxxxxx0xxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluRsImm.Create); @@ -1050,9 +1051,9 @@ namespace ARMeilleure.Decoders SetAsimd("111100100x< allInsts, Func ToFastLookupIndex) + private static void FillFastLookupTable(InstInfo[][] table, List allInsts, Func toFastLookupIndex) { List[] temp = new List[FastLookupSize]; @@ -1315,8 +1317,8 @@ namespace ARMeilleure.Decoders foreach (InstInfo inst in allInsts) { - int mask = ToFastLookupIndex(inst.Mask); - int value = ToFastLookupIndex(inst.Value); + int mask = toFastLookupIndex(inst.Mask); + int value = toFastLookupIndex(inst.Value); for (int index = 0; index < temp.Length; index++) { @@ -1335,22 +1337,21 @@ namespace ARMeilleure.Decoders private static void SetA32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { - Set(encoding, AllInstA32, new InstDescriptor(name, emitter), makeOp); + Set(encoding, _allInstA32, new InstDescriptor(name, emitter), makeOp); } private static void SetT16(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { encoding = "xxxxxxxxxxxxxxxx" + encoding; - Set(encoding, AllInstT32, new InstDescriptor(name, emitter), makeOp); + Set(encoding, _allInstT32, new InstDescriptor(name, emitter), makeOp); } private static void SetT32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { string reversedEncoding = $"{encoding.AsSpan(16)}{encoding.AsSpan(0, 16)}"; - MakeOp reversedMakeOp = - (inst, address, opCode) + OpCode ReversedMakeOp(InstDescriptor inst, ulong address, int opCode) => makeOp(inst, address, (int)BitOperations.RotateRight((uint)opCode, 16)); - Set(reversedEncoding, AllInstT32, new InstDescriptor(name, emitter), reversedMakeOp); + Set(reversedEncoding, _allInstT32, new InstDescriptor(name, emitter), ReversedMakeOp); } private static void SetVfp(string encoding, InstName name, InstEmitter emitter, MakeOp makeOpA32, MakeOp makeOpT32) @@ -1395,12 +1396,12 @@ namespace ARMeilleure.Decoders private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { - Set(encoding, AllInstA64, new InstDescriptor(name, emitter), makeOp); + Set(encoding, _allInstA64, new InstDescriptor(name, emitter), makeOp); } private static void Set(string encoding, List list, InstDescriptor inst, MakeOp makeOp) { - int bit = encoding.Length - 1; + int bit = encoding.Length - 1; int value = 0; int xMask = 0; int xBits = 0; @@ -1439,7 +1440,7 @@ namespace ARMeilleure.Decoders } else if (chr != '0') { - throw new ArgumentException(nameof(encoding)); + throw new ArgumentException($"Invalid encoding: {encoding}", nameof(encoding)); } } @@ -1470,17 +1471,17 @@ namespace ARMeilleure.Decoders public static (InstDescriptor inst, MakeOp makeOp) GetInstA32(int opCode) { - return GetInstFromList(InstA32FastLookup[ToFastLookupIndexA(opCode)], opCode); + return GetInstFromList(_instA32FastLookup[ToFastLookupIndexA(opCode)], opCode); } public static (InstDescriptor inst, MakeOp makeOp) GetInstT32(int opCode) { - return GetInstFromList(InstT32FastLookup[ToFastLookupIndexT(opCode)], opCode); + return GetInstFromList(_instT32FastLookup[ToFastLookupIndexT(opCode)], opCode); } public static (InstDescriptor inst, MakeOp makeOp) GetInstA64(int opCode) { - return GetInstFromList(InstA64FastLookup[ToFastLookupIndexA(opCode)], opCode); + return GetInstFromList(_instA64FastLookup[ToFastLookupIndexA(opCode)], opCode); } private static (InstDescriptor inst, MakeOp makeOp) GetInstFromList(InstInfo[] insts, int opCode) diff --git a/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs b/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs index 17c17812..ff9a6f27 100644 --- a/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs +++ b/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs @@ -22,10 +22,10 @@ namespace ARMeilleure.Decoders.Optimizations Block entryBlock = blocks[entryBlockId]; Block startBlock = entryBlock; - Block endBlock = entryBlock; + Block endBlock = entryBlock; int startBlockIndex = entryBlockId; - int endBlockIndex = entryBlockId; + int endBlockIndex = entryBlockId; for (int i = entryBlockId + 1; i < blocks.Count; i++) // Search forwards. { @@ -36,7 +36,7 @@ namespace ARMeilleure.Decoders.Optimizations break; // End of contiguous function. } - endBlock = block; + endBlock = block; endBlockIndex = i; } @@ -49,7 +49,7 @@ namespace ARMeilleure.Decoders.Optimizations break; // End of contiguous function. } - startBlock = block; + startBlock = block; startBlockIndex = i; } @@ -57,7 +57,7 @@ namespace ARMeilleure.Decoders.Optimizations { return blocks.ToArray(); // Nothing to do here. } - + // Mark branches whose target is outside of the contiguous region as an exit block. for (int i = startBlockIndex; i <= endBlockIndex; i++) { @@ -69,7 +69,7 @@ namespace ARMeilleure.Decoders.Optimizations } } - var newBlocks = new List(blocks.Count); + var newBlocks = new List(blocks.Count); // Finally, rebuild decoded block list, ignoring blocks outside the contiguous range. for (int i = 0; i < blocks.Count; i++) diff --git a/src/ARMeilleure/Decoders/RegisterSize.cs b/src/ARMeilleure/Decoders/RegisterSize.cs index c9cea03e..7c00984e 100644 --- a/src/ARMeilleure/Decoders/RegisterSize.cs +++ b/src/ARMeilleure/Decoders/RegisterSize.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.Decoders Int32, Int64, Simd64, - Simd128 + Simd128, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/ShiftType.cs b/src/ARMeilleure/Decoders/ShiftType.cs index 8583f16a..43b738f3 100644 --- a/src/ARMeilleure/Decoders/ShiftType.cs +++ b/src/ARMeilleure/Decoders/ShiftType.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.Decoders Lsl = 0, Lsr = 1, Asr = 2, - Ror = 3 + Ror = 3, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Diagnostics/IRDumper.cs b/src/ARMeilleure/Diagnostics/IRDumper.cs index 3d1a60e5..16833d08 100644 --- a/src/ARMeilleure/Diagnostics/IRDumper.cs +++ b/src/ARMeilleure/Diagnostics/IRDumper.cs @@ -34,7 +34,9 @@ namespace ARMeilleure.Diagnostics for (int index = 0; index < _indentLevel; index++) { +#pragma warning disable CA1834 // Use StringBuilder.Append(char) for single character strings _builder.Append(Indentation); +#pragma warning restore CA1834 } } @@ -110,10 +112,18 @@ namespace ARMeilleure.Diagnostics switch (reg.Type) { - case RegisterType.Flag: _builder.Append('b'); break; - case RegisterType.FpFlag: _builder.Append('f'); break; - case RegisterType.Integer: _builder.Append('r'); break; - case RegisterType.Vector: _builder.Append('v'); break; + case RegisterType.Flag: + _builder.Append('b'); + break; + case RegisterType.FpFlag: + _builder.Append('f'); + break; + case RegisterType.Integer: + _builder.Append('r'); + break; + case RegisterType.Vector: + _builder.Append('v'); + break; } _builder.Append(reg.Index); @@ -145,9 +155,15 @@ namespace ARMeilleure.Diagnostics switch (memOp.Scale) { - case Multiplier.x2: _builder.Append("*2"); break; - case Multiplier.x4: _builder.Append("*4"); break; - case Multiplier.x8: _builder.Append("*8"); break; + case Multiplier.x2: + _builder.Append("*2"); + break; + case Multiplier.x4: + _builder.Append("*4"); + break; + case Multiplier.x8: + _builder.Append("*8"); + break; } } @@ -308,4 +324,4 @@ namespace ARMeilleure.Diagnostics }; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Diagnostics/Logger.cs b/src/ARMeilleure/Diagnostics/Logger.cs index 07a60667..d7f61230 100644 --- a/src/ARMeilleure/Diagnostics/Logger.cs +++ b/src/ARMeilleure/Diagnostics/Logger.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Diagnostics { private static long _startTime; - private static long[] _accumulatedTime; + private static readonly long[] _accumulatedTime; static Logger() { @@ -53,4 +53,4 @@ namespace ARMeilleure.Diagnostics Console.WriteLine(text); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Diagnostics/PassName.cs b/src/ARMeilleure/Diagnostics/PassName.cs index e34bf0d2..2d87659f 100644 --- a/src/ARMeilleure/Diagnostics/PassName.cs +++ b/src/ARMeilleure/Diagnostics/PassName.cs @@ -14,6 +14,6 @@ namespace ARMeilleure.Diagnostics RegisterAllocation, CodeGeneration, - Count + Count, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Diagnostics/Symbols.cs b/src/ARMeilleure/Diagnostics/Symbols.cs index 6bde62f5..86469d8b 100644 --- a/src/ARMeilleure/Diagnostics/Symbols.cs +++ b/src/ARMeilleure/Diagnostics/Symbols.cs @@ -33,9 +33,8 @@ namespace ARMeilleure.Diagnostics public static string Get(ulong address) { - string result; - if (_symbols.TryGetValue(address, out result)) + if (_symbols.TryGetValue(address, out string result)) { return result; } diff --git a/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs b/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs index a4f17844..6452bf0a 100644 --- a/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs +++ b/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs @@ -19,19 +19,19 @@ namespace ARMeilleure.Diagnostics { _rejitQueueCounter = new PollingCounter("rejit-queue-length", this, () => _rejitQueue) { - DisplayName = "Rejit Queue Length" + DisplayName = "Rejit Queue Length", }; _funcTabSizeCounter = new PollingCounter("addr-tab-alloc", this, () => _funcTabSize / 1024d / 1024d) { DisplayName = "AddressTable Total Bytes Allocated", - DisplayUnits = "MiB" + DisplayUnits = "MiB", }; _funcTabLeafSizeCounter = new PollingCounter("addr-tab-leaf-alloc", this, () => _funcTabLeafSize / 1024d / 1024d) { DisplayName = "AddressTable Total Leaf Bytes Allocated", - DisplayUnits = "MiB" + DisplayUnits = "MiB", }; } diff --git a/src/ARMeilleure/Instructions/CryptoHelper.cs b/src/ARMeilleure/Instructions/CryptoHelper.cs index e517c75d..ba68cebb 100644 --- a/src/ARMeilleure/Instructions/CryptoHelper.cs +++ b/src/ARMeilleure/Instructions/CryptoHelper.cs @@ -7,7 +7,8 @@ namespace ARMeilleure.Instructions { static class CryptoHelper { -#region "LookUp Tables" + #region "LookUp Tables" +#pragma warning disable IDE1006 // Naming rule violation private static ReadOnlySpan _sBox => new byte[] { 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, @@ -25,7 +26,7 @@ namespace ARMeilleure.Instructions 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, - 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16, }; private static ReadOnlySpan _invSBox => new byte[] @@ -45,7 +46,7 @@ namespace ARMeilleure.Instructions 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, - 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d + 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d, }; private static ReadOnlySpan _gfMul02 => new byte[] @@ -65,7 +66,7 @@ namespace ARMeilleure.Instructions 0x9b, 0x99, 0x9f, 0x9d, 0x93, 0x91, 0x97, 0x95, 0x8b, 0x89, 0x8f, 0x8d, 0x83, 0x81, 0x87, 0x85, 0xbb, 0xb9, 0xbf, 0xbd, 0xb3, 0xb1, 0xb7, 0xb5, 0xab, 0xa9, 0xaf, 0xad, 0xa3, 0xa1, 0xa7, 0xa5, 0xdb, 0xd9, 0xdf, 0xdd, 0xd3, 0xd1, 0xd7, 0xd5, 0xcb, 0xc9, 0xcf, 0xcd, 0xc3, 0xc1, 0xc7, 0xc5, - 0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, 0xe3, 0xe1, 0xe7, 0xe5 + 0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, 0xe3, 0xe1, 0xe7, 0xe5, }; private static ReadOnlySpan _gfMul03 => new byte[] @@ -85,7 +86,7 @@ namespace ARMeilleure.Instructions 0x5b, 0x58, 0x5d, 0x5e, 0x57, 0x54, 0x51, 0x52, 0x43, 0x40, 0x45, 0x46, 0x4f, 0x4c, 0x49, 0x4a, 0x6b, 0x68, 0x6d, 0x6e, 0x67, 0x64, 0x61, 0x62, 0x73, 0x70, 0x75, 0x76, 0x7f, 0x7c, 0x79, 0x7a, 0x3b, 0x38, 0x3d, 0x3e, 0x37, 0x34, 0x31, 0x32, 0x23, 0x20, 0x25, 0x26, 0x2f, 0x2c, 0x29, 0x2a, - 0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, 0x1f, 0x1c, 0x19, 0x1a + 0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, 0x1f, 0x1c, 0x19, 0x1a, }; private static ReadOnlySpan _gfMul09 => new byte[] @@ -105,7 +106,7 @@ namespace ARMeilleure.Instructions 0x9a, 0x93, 0x88, 0x81, 0xbe, 0xb7, 0xac, 0xa5, 0xd2, 0xdb, 0xc0, 0xc9, 0xf6, 0xff, 0xe4, 0xed, 0x0a, 0x03, 0x18, 0x11, 0x2e, 0x27, 0x3c, 0x35, 0x42, 0x4b, 0x50, 0x59, 0x66, 0x6f, 0x74, 0x7d, 0xa1, 0xa8, 0xb3, 0xba, 0x85, 0x8c, 0x97, 0x9e, 0xe9, 0xe0, 0xfb, 0xf2, 0xcd, 0xc4, 0xdf, 0xd6, - 0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, 0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46 + 0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, 0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46, }; private static ReadOnlySpan _gfMul0B => new byte[] @@ -125,7 +126,7 @@ namespace ARMeilleure.Instructions 0x01, 0x0a, 0x17, 0x1c, 0x2d, 0x26, 0x3b, 0x30, 0x59, 0x52, 0x4f, 0x44, 0x75, 0x7e, 0x63, 0x68, 0xb1, 0xba, 0xa7, 0xac, 0x9d, 0x96, 0x8b, 0x80, 0xe9, 0xe2, 0xff, 0xf4, 0xc5, 0xce, 0xd3, 0xd8, 0x7a, 0x71, 0x6c, 0x67, 0x56, 0x5d, 0x40, 0x4b, 0x22, 0x29, 0x34, 0x3f, 0x0e, 0x05, 0x18, 0x13, - 0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, 0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3 + 0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, 0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3, }; private static ReadOnlySpan _gfMul0D => new byte[] @@ -145,7 +146,7 @@ namespace ARMeilleure.Instructions 0xb7, 0xba, 0xad, 0xa0, 0x83, 0x8e, 0x99, 0x94, 0xdf, 0xd2, 0xc5, 0xc8, 0xeb, 0xe6, 0xf1, 0xfc, 0x67, 0x6a, 0x7d, 0x70, 0x53, 0x5e, 0x49, 0x44, 0x0f, 0x02, 0x15, 0x18, 0x3b, 0x36, 0x21, 0x2c, 0x0c, 0x01, 0x16, 0x1b, 0x38, 0x35, 0x22, 0x2f, 0x64, 0x69, 0x7e, 0x73, 0x50, 0x5d, 0x4a, 0x47, - 0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, 0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97 + 0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, 0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97, }; private static ReadOnlySpan _gfMul0E => new byte[] @@ -165,23 +166,24 @@ namespace ARMeilleure.Instructions 0xec, 0xe2, 0xf0, 0xfe, 0xd4, 0xda, 0xc8, 0xc6, 0x9c, 0x92, 0x80, 0x8e, 0xa4, 0xaa, 0xb8, 0xb6, 0x0c, 0x02, 0x10, 0x1e, 0x34, 0x3a, 0x28, 0x26, 0x7c, 0x72, 0x60, 0x6e, 0x44, 0x4a, 0x58, 0x56, 0x37, 0x39, 0x2b, 0x25, 0x0f, 0x01, 0x13, 0x1d, 0x47, 0x49, 0x5b, 0x55, 0x7f, 0x71, 0x63, 0x6d, - 0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, 0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d + 0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, 0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d, }; private static ReadOnlySpan _srPerm => new byte[] { - 0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3 + 0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3, }; private static ReadOnlySpan _isrPerm => new byte[] { - 0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11 + 0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11, }; -#endregion +#pragma warning restore IDE1006 + #endregion public static V128 AesInvMixColumns(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int columns = 0; columns <= 3; columns++) @@ -204,7 +206,7 @@ namespace ARMeilleure.Instructions public static V128 AesInvShiftRows(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int idx = 0; idx <= 15; idx++) @@ -217,7 +219,7 @@ namespace ARMeilleure.Instructions public static V128 AesInvSubBytes(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int idx = 0; idx <= 15; idx++) @@ -230,7 +232,7 @@ namespace ARMeilleure.Instructions public static V128 AesMixColumns(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int columns = 0; columns <= 3; columns++) @@ -253,7 +255,7 @@ namespace ARMeilleure.Instructions public static V128 AesShiftRows(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int idx = 0; idx <= 15; idx++) @@ -266,7 +268,7 @@ namespace ARMeilleure.Instructions public static V128 AesSubBytes(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int idx = 0; idx <= 15; idx++) diff --git a/src/ARMeilleure/Instructions/InstEmitAlu.cs b/src/ARMeilleure/Instructions/InstEmitAlu.cs index e0d10e77..ac17c32a 100644 --- a/src/ARMeilleure/Instructions/InstEmitAlu.cs +++ b/src/ARMeilleure/Instructions/InstEmitAlu.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; using System.Diagnostics; - using static ARMeilleure.Instructions.InstEmitAluHelper; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -12,7 +11,7 @@ namespace ARMeilleure.Instructions { static partial class InstEmit { - public static void Adc(ArmEmitterContext context) => EmitAdc(context, setFlags: false); + public static void Adc(ArmEmitterContext context) => EmitAdc(context, setFlags: false); public static void Adcs(ArmEmitterContext context) => EmitAdc(context, setFlags: true); private static void EmitAdc(ArmEmitterContext context, bool setFlags) @@ -87,7 +86,7 @@ namespace ARMeilleure.Instructions SetAluDOrZR(context, context.ShiftRightSI(GetAluN(context), GetAluMShift(context))); } - public static void Bic(ArmEmitterContext context) => EmitBic(context, setFlags: false); + public static void Bic(ArmEmitterContext context) => EmitBic(context, setFlags: false); public static void Bics(ArmEmitterContext context) => EmitBic(context, setFlags: true); private static void EmitBic(ArmEmitterContext context, bool setFlags) @@ -190,7 +189,7 @@ namespace ARMeilleure.Instructions SetAluDOrZR(context, context.ShiftRightUI(GetAluN(context), GetAluMShift(context))); } - public static void Sbc(ArmEmitterContext context) => EmitSbc(context, setFlags: false); + public static void Sbc(ArmEmitterContext context) => EmitSbc(context, setFlags: false); public static void Sbcs(ArmEmitterContext context) => EmitSbc(context, setFlags: true); private static void EmitSbc(ArmEmitterContext context, bool setFlags) @@ -281,16 +280,16 @@ namespace ARMeilleure.Instructions Debug.Assert(op.Type == OperandType.I64); Operand val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xaaaaaaaaaaaaaaaaul)), Const(1)), - context.ShiftLeft (context.BitwiseAnd(op, Const(0x5555555555555555ul)), Const(1))); + context.ShiftLeft(context.BitwiseAnd(op, Const(0x5555555555555555ul)), Const(1))); val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xccccccccccccccccul)), Const(2)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x3333333333333333ul)), Const(2))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x3333333333333333ul)), Const(2))); val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xf0f0f0f0f0f0f0f0ul)), Const(4)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x0f0f0f0f0f0f0f0ful)), Const(4))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x0f0f0f0f0f0f0f0ful)), Const(4))); val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xff00ff00ff00ff00ul)), Const(8)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x00ff00ff00ff00fful)), Const(8))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x00ff00ff00ff00fful)), Const(8))); val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xffff0000ffff0000ul)), Const(16)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16))); return context.BitwiseOr(context.ShiftRightUI(val, Const(32)), context.ShiftLeft(val, Const(32))); } @@ -340,7 +339,7 @@ namespace ARMeilleure.Instructions Operand val = EmitReverseBytes16_64Op(context, op); return context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xffff0000ffff0000ul)), Const(16)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16))); } public static void Rev64(ArmEmitterContext context) diff --git a/src/ARMeilleure/Instructions/InstEmitAlu32.cs b/src/ARMeilleure/Instructions/InstEmitAlu32.cs index 584ada7e..3a5e71bc 100644 --- a/src/ARMeilleure/Instructions/InstEmitAlu32.cs +++ b/src/ARMeilleure/Instructions/InstEmitAlu32.cs @@ -2,13 +2,14 @@ using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; - +using System.Diagnostics.CodeAnalysis; using static ARMeilleure.Instructions.InstEmitAluHelper; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; namespace ARMeilleure.Instructions { + [SuppressMessage("Style", "IDE0059: Remove unnecessary value assignment")] static partial class InstEmit32 { public static void Add(ArmEmitterContext context) diff --git a/src/ARMeilleure/Instructions/InstEmitAluHelper.cs b/src/ARMeilleure/Instructions/InstEmitAluHelper.cs index 994878ad..4d4a31f7 100644 --- a/src/ARMeilleure/Instructions/InstEmitAluHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitAluHelper.cs @@ -26,7 +26,7 @@ namespace ARMeilleure.Instructions public static void EmitNZFlagsCheck(ArmEmitterContext context, Operand d) { - SetFlag(context, PState.NFlag, context.ICompareLess (d, Const(d.Type, 0))); + SetFlag(context, PState.NFlag, context.ICompareLess(d, Const(d.Type, 0))); SetFlag(context, PState.ZFlag, context.ICompareEqual(d, Const(d.Type, 0))); } @@ -196,60 +196,73 @@ namespace ARMeilleure.Instructions { // ARM32. case IOpCode32AluImm op: - { - if (ShouldSetFlags(context) && op.IsRotated && setCarry) { - SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31)); + if (ShouldSetFlags(context) && op.IsRotated && setCarry) + { + SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31)); + } + + return Const(op.Immediate); } + case IOpCode32AluImm16 op: return Const(op.Immediate); - } - case IOpCode32AluImm16 op: return Const(op.Immediate); + case IOpCode32AluRsImm op: + return GetMShiftedByImmediate(context, op, setCarry); + case IOpCode32AluRsReg op: + return GetMShiftedByReg(context, op, setCarry); - case IOpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry); - case IOpCode32AluRsReg op: return GetMShiftedByReg(context, op, setCarry); - - case IOpCode32AluReg op: return GetIntA32(context, op.Rm); + case IOpCode32AluReg op: + return GetIntA32(context, op.Rm); // ARM64. case IOpCodeAluImm op: - { - if (op.GetOperandType() == OperandType.I32) { - return Const((int)op.Immediate); + if (op.GetOperandType() == OperandType.I32) + { + return Const((int)op.Immediate); + } + else + { + return Const(op.Immediate); + } } - else - { - return Const(op.Immediate); - } - } case IOpCodeAluRs op: - { - Operand value = GetIntOrZR(context, op.Rm); - - switch (op.ShiftType) { - case ShiftType.Lsl: value = context.ShiftLeft (value, Const(op.Shift)); break; - case ShiftType.Lsr: value = context.ShiftRightUI(value, Const(op.Shift)); break; - case ShiftType.Asr: value = context.ShiftRightSI(value, Const(op.Shift)); break; - case ShiftType.Ror: value = context.RotateRight (value, Const(op.Shift)); break; + Operand value = GetIntOrZR(context, op.Rm); + + switch (op.ShiftType) + { + case ShiftType.Lsl: + value = context.ShiftLeft(value, Const(op.Shift)); + break; + case ShiftType.Lsr: + value = context.ShiftRightUI(value, Const(op.Shift)); + break; + case ShiftType.Asr: + value = context.ShiftRightSI(value, Const(op.Shift)); + break; + case ShiftType.Ror: + value = context.RotateRight(value, Const(op.Shift)); + break; + } + + return value; } - return value; - } - case IOpCodeAluRx op: - { - Operand value = GetExtendedM(context, op.Rm, op.IntType); + { + Operand value = GetExtendedM(context, op.Rm, op.IntType); - value = context.ShiftLeft(value, Const(op.Shift)); + value = context.ShiftLeft(value, Const(op.Shift)); - return value; - } + return value; + } - default: throw InvalidOpCodeType(context.CurrOp); + default: + throw InvalidOpCodeType(context.CurrOp); } } @@ -269,9 +282,15 @@ namespace ARMeilleure.Instructions { switch (op.ShiftType) { - case ShiftType.Lsr: shift = 32; break; - case ShiftType.Asr: shift = 32; break; - case ShiftType.Ror: shift = 1; break; + case ShiftType.Lsr: + shift = 32; + break; + case ShiftType.Asr: + shift = 32; + break; + case ShiftType.Ror: + shift = 1; + break; } } @@ -281,9 +300,15 @@ namespace ARMeilleure.Instructions switch (op.ShiftType) { - case ShiftType.Lsl: m = GetLslC(context, m, setCarry, shift); break; - case ShiftType.Lsr: m = GetLsrC(context, m, setCarry, shift); break; - case ShiftType.Asr: m = GetAsrC(context, m, setCarry, shift); break; + case ShiftType.Lsl: + m = GetLslC(context, m, setCarry, shift); + break; + case ShiftType.Lsr: + m = GetLsrC(context, m, setCarry, shift); + break; + case ShiftType.Asr: + m = GetAsrC(context, m, setCarry, shift); + break; case ShiftType.Ror: if (op.Immediate != 0) { @@ -306,9 +331,15 @@ namespace ARMeilleure.Instructions { switch (shiftType) { - case ShiftType.Lsr: shift = 32; break; - case ShiftType.Asr: shift = 32; break; - case ShiftType.Ror: shift = 1; break; + case ShiftType.Lsr: + shift = 32; + break; + case ShiftType.Asr: + shift = 32; + break; + case ShiftType.Ror: + shift = 1; + break; } } @@ -328,10 +359,18 @@ namespace ARMeilleure.Instructions switch (op.ShiftType) { - case ShiftType.Lsl: shiftResult = EmitLslC(context, m, setCarry, s, shiftIsZero); break; - case ShiftType.Lsr: shiftResult = EmitLsrC(context, m, setCarry, s, shiftIsZero); break; - case ShiftType.Asr: shiftResult = EmitAsrC(context, m, setCarry, s, shiftIsZero); break; - case ShiftType.Ror: shiftResult = EmitRorC(context, m, setCarry, s, shiftIsZero); break; + case ShiftType.Lsl: + shiftResult = EmitLslC(context, m, setCarry, s, shiftIsZero); + break; + case ShiftType.Lsr: + shiftResult = EmitLsrC(context, m, setCarry, s, shiftIsZero); + break; + case ShiftType.Asr: + shiftResult = EmitAsrC(context, m, setCarry, s, shiftIsZero); + break; + case ShiftType.Ror: + shiftResult = EmitRorC(context, m, setCarry, s, shiftIsZero); + break; } return context.ConditionalSelect(shiftIsZero, zeroResult, shiftResult); diff --git a/src/ARMeilleure/Instructions/InstEmitBfm.cs b/src/ARMeilleure/Instructions/InstEmitBfm.cs index 46a7dddd..aaf22875 100644 --- a/src/ARMeilleure/Instructions/InstEmitBfm.cs +++ b/src/ARMeilleure/Instructions/InstEmitBfm.cs @@ -84,9 +84,9 @@ namespace ARMeilleure.Instructions { Operand res = GetIntOrZR(context, op.Rn); - res = context.ShiftLeft (res, Const(bitsCount - 1 - op.Pos)); + res = context.ShiftLeft(res, Const(bitsCount - 1 - op.Pos)); res = context.ShiftRightSI(res, Const(bitsCount - 1)); - res = context.BitwiseAnd (res, Const(res.Type, ~op.TMask)); + res = context.BitwiseAnd(res, Const(res.Type, ~op.TMask)); Operand n2 = GetBfmN(context); @@ -193,4 +193,4 @@ namespace ARMeilleure.Instructions return context.BitwiseAnd(context.RotateRight(res, Const(op.Shift)), Const(res.Type, mask)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitCcmp.cs b/src/ARMeilleure/Instructions/InstEmitCcmp.cs index 7f0beb6c..a71fc268 100644 --- a/src/ARMeilleure/Instructions/InstEmitCcmp.cs +++ b/src/ARMeilleure/Instructions/InstEmitCcmp.cs @@ -2,7 +2,6 @@ using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; - using static ARMeilleure.Instructions.InstEmitAluHelper; using static ARMeilleure.Instructions.InstEmitFlowHelper; using static ARMeilleure.Instructions.InstEmitHelper; @@ -20,7 +19,7 @@ namespace ARMeilleure.Instructions OpCodeCcmp op = (OpCodeCcmp)context.CurrOp; Operand lblTrue = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); EmitCondBranch(context, lblTrue, op.Cond); @@ -58,4 +57,4 @@ namespace ARMeilleure.Instructions context.MarkLabel(lblEnd); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitCsel.cs b/src/ARMeilleure/Instructions/InstEmitCsel.cs index 926b9a9e..1cd936b3 100644 --- a/src/ARMeilleure/Instructions/InstEmitCsel.cs +++ b/src/ARMeilleure/Instructions/InstEmitCsel.cs @@ -1,7 +1,6 @@ using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; - using static ARMeilleure.Instructions.InstEmitFlowHelper; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -15,10 +14,10 @@ namespace ARMeilleure.Instructions None, Increment, Invert, - Negate + Negate, } - public static void Csel(ArmEmitterContext context) => EmitCsel(context, CselOperation.None); + public static void Csel(ArmEmitterContext context) => EmitCsel(context, CselOperation.None); public static void Csinc(ArmEmitterContext context) => EmitCsel(context, CselOperation.Increment); public static void Csinv(ArmEmitterContext context) => EmitCsel(context, CselOperation.Invert); public static void Csneg(ArmEmitterContext context) => EmitCsel(context, CselOperation.Negate); @@ -50,4 +49,4 @@ namespace ARMeilleure.Instructions SetIntOrZR(context, op.Rd, d); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitDiv.cs b/src/ARMeilleure/Instructions/InstEmitDiv.cs index 39a5c32e..728462ed 100644 --- a/src/ARMeilleure/Instructions/InstEmitDiv.cs +++ b/src/ARMeilleure/Instructions/InstEmitDiv.cs @@ -1,7 +1,6 @@ using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -23,7 +22,7 @@ namespace ARMeilleure.Instructions Operand divisorIsZero = context.ICompareEqual(m, Const(m.Type, 0)); Operand lblBadDiv = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); context.BranchIfTrue(lblBadDiv, divisorIsZero); @@ -33,7 +32,7 @@ namespace ARMeilleure.Instructions bool is32Bits = op.RegisterSize == RegisterSize.Int32; Operand intMin = is32Bits ? Const(int.MinValue) : Const(long.MinValue); - Operand minus1 = is32Bits ? Const(-1) : Const(-1L); + Operand minus1 = is32Bits ? Const(-1) : Const(-1L); Operand nIsIntMin = context.ICompareEqual(n, intMin); Operand mIsMinus1 = context.ICompareEqual(m, minus1); @@ -51,7 +50,7 @@ namespace ARMeilleure.Instructions Operand d = unsigned ? context.DivideUI(n, m) - : context.Divide (n, m); + : context.Divide(n, m); SetAluDOrZR(context, d); diff --git a/src/ARMeilleure/Instructions/InstEmitException.cs b/src/ARMeilleure/Instructions/InstEmitException.cs index 0baaa87d..d30fb2fb 100644 --- a/src/ARMeilleure/Instructions/InstEmitException.cs +++ b/src/ARMeilleure/Instructions/InstEmitException.cs @@ -52,4 +52,4 @@ namespace ARMeilleure.Instructions context.Return(Const(op.Address)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitFlow.cs b/src/ARMeilleure/Instructions/InstEmitFlow.cs index c40eb55c..a986bf66 100644 --- a/src/ARMeilleure/Instructions/InstEmitFlow.cs +++ b/src/ARMeilleure/Instructions/InstEmitFlow.cs @@ -53,7 +53,7 @@ namespace ARMeilleure.Instructions } public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true); - public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false); + public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false); private static void EmitCb(ArmEmitterContext context, bool onNotZero) { @@ -70,7 +70,7 @@ namespace ARMeilleure.Instructions } public static void Tbnz(ArmEmitterContext context) => EmitTb(context, onNotZero: true); - public static void Tbz(ArmEmitterContext context) => EmitTb(context, onNotZero: false); + public static void Tbz(ArmEmitterContext context) => EmitTb(context, onNotZero: false); private static void EmitTb(ArmEmitterContext context, bool onNotZero) { @@ -104,4 +104,4 @@ namespace ARMeilleure.Instructions } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitFlow32.cs b/src/ARMeilleure/Instructions/InstEmitFlow32.cs index 3a7707ee..289d3f48 100644 --- a/src/ARMeilleure/Instructions/InstEmitFlow32.cs +++ b/src/ARMeilleure/Instructions/InstEmitFlow32.cs @@ -82,7 +82,7 @@ namespace ARMeilleure.Instructions } public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true); - public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false); + public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false); private static void EmitCb(ArmEmitterContext context, bool onNotZero) { @@ -109,7 +109,7 @@ namespace ARMeilleure.Instructions } public static void Tbb(ArmEmitterContext context) => EmitTb(context, halfword: false); - public static void Tbh(ArmEmitterContext context) => EmitTb(context, halfword: true); + public static void Tbh(ArmEmitterContext context) => EmitTb(context, halfword: true); private static void EmitTb(ArmEmitterContext context, bool halfword) { @@ -133,4 +133,4 @@ namespace ARMeilleure.Instructions EmitVirtualJump(context, targetAddress, isReturn: false); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs b/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs index 6ac32908..2009bafd 100644 --- a/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs @@ -75,66 +75,66 @@ namespace ARMeilleure.Instructions break; case Condition.GtUn: - { - Operand c = GetFlag(PState.CFlag); - Operand z = GetFlag(PState.ZFlag); + { + Operand c = GetFlag(PState.CFlag); + Operand z = GetFlag(PState.ZFlag); - value = context.BitwiseAnd(c, Inverse(z)); + value = context.BitwiseAnd(c, Inverse(z)); - break; - } + break; + } case Condition.LeUn: - { - Operand c = GetFlag(PState.CFlag); - Operand z = GetFlag(PState.ZFlag); + { + Operand c = GetFlag(PState.CFlag); + Operand z = GetFlag(PState.ZFlag); - value = context.BitwiseOr(Inverse(c), z); + value = context.BitwiseOr(Inverse(c), z); - break; - } + break; + } case Condition.Ge: - { - Operand n = GetFlag(PState.NFlag); - Operand v = GetFlag(PState.VFlag); + { + Operand n = GetFlag(PState.NFlag); + Operand v = GetFlag(PState.VFlag); - value = context.ICompareEqual(n, v); + value = context.ICompareEqual(n, v); - break; - } + break; + } case Condition.Lt: - { - Operand n = GetFlag(PState.NFlag); - Operand v = GetFlag(PState.VFlag); + { + Operand n = GetFlag(PState.NFlag); + Operand v = GetFlag(PState.VFlag); - value = context.ICompareNotEqual(n, v); + value = context.ICompareNotEqual(n, v); - break; - } + break; + } case Condition.Gt: - { - Operand n = GetFlag(PState.NFlag); - Operand z = GetFlag(PState.ZFlag); - Operand v = GetFlag(PState.VFlag); + { + Operand n = GetFlag(PState.NFlag); + Operand z = GetFlag(PState.ZFlag); + Operand v = GetFlag(PState.VFlag); - value = context.BitwiseAnd(Inverse(z), context.ICompareEqual(n, v)); + value = context.BitwiseAnd(Inverse(z), context.ICompareEqual(n, v)); - break; - } + break; + } case Condition.Le: - { - Operand n = GetFlag(PState.NFlag); - Operand z = GetFlag(PState.ZFlag); - Operand v = GetFlag(PState.VFlag); + { + Operand n = GetFlag(PState.NFlag); + Operand z = GetFlag(PState.ZFlag); + Operand v = GetFlag(PState.VFlag); - value = context.BitwiseOr(z, context.ICompareNotEqual(n, v)); + value = context.BitwiseOr(z, context.ICompareNotEqual(n, v)); - break; - } + break; + } } return value; diff --git a/src/ARMeilleure/Instructions/InstEmitHashHelper.cs b/src/ARMeilleure/Instructions/InstEmitHashHelper.cs index 55a03a4f..9218e1ae 100644 --- a/src/ARMeilleure/Instructions/InstEmitHashHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitHashHelper.cs @@ -45,7 +45,7 @@ namespace ARMeilleure.Instructions } else { - string name = (size, castagnoli) switch + string name = (size, castagnoli) switch { (0, false) => nameof(SoftFallback.Crc32b), (1, false) => nameof(SoftFallback.Crc32h), @@ -55,7 +55,7 @@ namespace ARMeilleure.Instructions (1, true) => nameof(SoftFallback.Crc32ch), (2, true) => nameof(SoftFallback.Crc32cw), (3, true) => nameof(SoftFallback.Crc32cx), - _ => throw new ArgumentOutOfRangeException(nameof(size)) + _ => throw new ArgumentOutOfRangeException(nameof(size)), }; return context.Call(typeof(SoftFallback).GetMethod(name), crc, value); @@ -71,9 +71,15 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: data = context.VectorInsert8(context.VectorZero(), data, 0); break; - case 1: data = context.VectorInsert16(context.VectorZero(), data, 0); break; - case 2: data = context.VectorInsert(context.VectorZero(), data, 0); break; + case 0: + data = context.VectorInsert8(context.VectorZero(), data, 0); + break; + case 1: + data = context.VectorInsert16(context.VectorZero(), data, 0); + break; + case 2: + data = context.VectorInsert(context.VectorZero(), data, 0); + break; } int bitsize = 8 << size; diff --git a/src/ARMeilleure/Instructions/InstEmitHelper.cs b/src/ARMeilleure/Instructions/InstEmitHelper.cs index a22bb3fb..7a515f94 100644 --- a/src/ARMeilleure/Instructions/InstEmitHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitHelper.cs @@ -16,13 +16,25 @@ namespace ARMeilleure.Instructions switch (type) { - case IntType.UInt8: value = context.ZeroExtend8 (value.Type, value); break; - case IntType.UInt16: value = context.ZeroExtend16(value.Type, value); break; - case IntType.UInt32: value = context.ZeroExtend32(value.Type, value); break; + case IntType.UInt8: + value = context.ZeroExtend8(value.Type, value); + break; + case IntType.UInt16: + value = context.ZeroExtend16(value.Type, value); + break; + case IntType.UInt32: + value = context.ZeroExtend32(value.Type, value); + break; - case IntType.Int8: value = context.SignExtend8 (value.Type, value); break; - case IntType.Int16: value = context.SignExtend16(value.Type, value); break; - case IntType.Int32: value = context.SignExtend32(value.Type, value); break; + case IntType.Int8: + value = context.SignExtend8(value.Type, value); + break; + case IntType.Int16: + value = context.SignExtend16(value.Type, value); + break; + case IntType.Int32: + value = context.SignExtend32(value.Type, value); + break; } return value; @@ -100,78 +112,51 @@ namespace ARMeilleure.Instructions public static int GetBankedRegisterAlias(Aarch32Mode mode, int regIndex) { - switch (regIndex) + return regIndex switch { - case 8: return mode == Aarch32Mode.Fiq - ? RegisterAlias.R8Fiq - : RegisterAlias.R8Usr; - - case 9: return mode == Aarch32Mode.Fiq - ? RegisterAlias.R9Fiq - : RegisterAlias.R9Usr; - - case 10: return mode == Aarch32Mode.Fiq - ? RegisterAlias.R10Fiq - : RegisterAlias.R10Usr; - - case 11: return mode == Aarch32Mode.Fiq - ? RegisterAlias.R11Fiq - : RegisterAlias.R11Usr; - - case 12: return mode == Aarch32Mode.Fiq - ? RegisterAlias.R12Fiq - : RegisterAlias.R12Usr; - - case 13: - switch (mode) - { - case Aarch32Mode.User: - case Aarch32Mode.System: return RegisterAlias.SpUsr; - case Aarch32Mode.Fiq: return RegisterAlias.SpFiq; - case Aarch32Mode.Irq: return RegisterAlias.SpIrq; - case Aarch32Mode.Supervisor: return RegisterAlias.SpSvc; - case Aarch32Mode.Abort: return RegisterAlias.SpAbt; - case Aarch32Mode.Hypervisor: return RegisterAlias.SpHyp; - case Aarch32Mode.Undefined: return RegisterAlias.SpUnd; - - default: throw new ArgumentException(nameof(mode)); - } - - case 14: - switch (mode) - { - case Aarch32Mode.User: - case Aarch32Mode.Hypervisor: - case Aarch32Mode.System: return RegisterAlias.LrUsr; - case Aarch32Mode.Fiq: return RegisterAlias.LrFiq; - case Aarch32Mode.Irq: return RegisterAlias.LrIrq; - case Aarch32Mode.Supervisor: return RegisterAlias.LrSvc; - case Aarch32Mode.Abort: return RegisterAlias.LrAbt; - case Aarch32Mode.Undefined: return RegisterAlias.LrUnd; - - default: throw new ArgumentException(nameof(mode)); - } - - default: throw new ArgumentOutOfRangeException(nameof(regIndex)); - } +#pragma warning disable IDE0055 // Disable formatting + 8 => mode == Aarch32Mode.Fiq ? RegisterAlias.R8Fiq : RegisterAlias.R8Usr, + 9 => mode == Aarch32Mode.Fiq ? RegisterAlias.R9Fiq : RegisterAlias.R9Usr, + 10 => mode == Aarch32Mode.Fiq ? RegisterAlias.R10Fiq : RegisterAlias.R10Usr, + 11 => mode == Aarch32Mode.Fiq ? RegisterAlias.R11Fiq : RegisterAlias.R11Usr, + 12 => mode == Aarch32Mode.Fiq ? RegisterAlias.R12Fiq : RegisterAlias.R12Usr, + 13 => mode switch + { + Aarch32Mode.User or Aarch32Mode.System => RegisterAlias.SpUsr, + Aarch32Mode.Fiq => RegisterAlias.SpFiq, + Aarch32Mode.Irq => RegisterAlias.SpIrq, + Aarch32Mode.Supervisor => RegisterAlias.SpSvc, + Aarch32Mode.Abort => RegisterAlias.SpAbt, + Aarch32Mode.Hypervisor => RegisterAlias.SpHyp, + Aarch32Mode.Undefined => RegisterAlias.SpUnd, + _ => throw new ArgumentException($"No such AArch32Mode: {mode}", nameof(mode)), + }, + 14 => mode switch + { + Aarch32Mode.User or Aarch32Mode.Hypervisor or Aarch32Mode.System => RegisterAlias.LrUsr, + Aarch32Mode.Fiq => RegisterAlias.LrFiq, + Aarch32Mode.Irq => RegisterAlias.LrIrq, + Aarch32Mode.Supervisor => RegisterAlias.LrSvc, + Aarch32Mode.Abort => RegisterAlias.LrAbt, + Aarch32Mode.Undefined => RegisterAlias.LrUnd, + _ => throw new ArgumentException($"No such AArch32Mode: {mode}", nameof(mode)), + }, + _ => throw new ArgumentOutOfRangeException(nameof(regIndex), regIndex, null), +#pragma warning restore IDE0055 + }; } public static bool IsA32Return(ArmEmitterContext context) { - switch (context.CurrOp) + return context.CurrOp switch { - case IOpCode32MemMult op: - return true; // Setting PC using LDM is nearly always a return. - case OpCode32AluRsImm op: - return op.Rm == RegisterAlias.Aarch32Lr; - case OpCode32AluRsReg op: - return op.Rm == RegisterAlias.Aarch32Lr; - case OpCode32AluReg op: - return op.Rm == RegisterAlias.Aarch32Lr; - case OpCode32Mem op: - return op.Rn == RegisterAlias.Aarch32Sp && op.WBack && !op.Index; // Setting PC to an address stored on the stack is nearly always a return. - } - return false; + IOpCode32MemMult => true, // Setting PC using LDM is nearly always a return. + OpCode32AluRsImm op => op.Rm == RegisterAlias.Aarch32Lr, + OpCode32AluRsReg op => op.Rm == RegisterAlias.Aarch32Lr, + OpCode32AluReg op => op.Rm == RegisterAlias.Aarch32Lr, + OpCode32Mem op => op.Rn == RegisterAlias.Aarch32Sp && op.WBack && !op.Index, // Setting PC to an address stored on the stack is nearly always a return. + _ => false, + }; } public static void EmitBxWritePc(ArmEmitterContext context, Operand pc, int sourceRegister = 0) diff --git a/src/ARMeilleure/Instructions/InstEmitMemory.cs b/src/ARMeilleure/Instructions/InstEmitMemory.cs index 7baed14c..840099f9 100644 --- a/src/ARMeilleure/Instructions/InstEmitMemory.cs +++ b/src/ARMeilleure/Instructions/InstEmitMemory.cs @@ -26,7 +26,7 @@ namespace ARMeilleure.Instructions SetIntOrZR(context, op.Rd, Const(address)); } - public static void Ldr(ArmEmitterContext context) => EmitLdr(context, signed: false); + public static void Ldr(ArmEmitterContext context) => EmitLdr(context, signed: false); public static void Ldrs(ArmEmitterContext context) => EmitLdr(context, signed: true); private static void EmitLdr(ArmEmitterContext context, bool signed) @@ -89,7 +89,7 @@ namespace ARMeilleure.Instructions Operand address = GetAddress(context); Operand address2 = GetAddress(context, 1L << op.Size); - EmitLoad(op.Rt, address); + EmitLoad(op.Rt, address); EmitLoad(op.Rt2, address2); EmitWBackIfNeeded(context, address); @@ -113,7 +113,7 @@ namespace ARMeilleure.Instructions Operand address = GetAddress(context); Operand address2 = GetAddress(context, 1L << op.Size); - EmitStore(context, address, op.Rt, op.Size); + EmitStore(context, address, op.Rt, op.Size); EmitStore(context, address2, op.Rt2, op.Size); EmitWBackIfNeeded(context, address); @@ -126,42 +126,42 @@ namespace ARMeilleure.Instructions switch (context.CurrOp) { case OpCodeMemImm op: - { - address = context.Copy(GetIntOrSP(context, op.Rn)); - - // Pre-indexing. - if (!op.PostIdx) { - address = context.Add(address, Const(op.Immediate + addend)); - } - else if (addend != 0) - { - address = context.Add(address, Const(addend)); - } + address = context.Copy(GetIntOrSP(context, op.Rn)); - break; - } + // Pre-indexing. + if (!op.PostIdx) + { + address = context.Add(address, Const(op.Immediate + addend)); + } + else if (addend != 0) + { + address = context.Add(address, Const(addend)); + } + + break; + } case OpCodeMemReg op: - { - Operand n = GetIntOrSP(context, op.Rn); - - Operand m = GetExtendedM(context, op.Rm, op.IntType); - - if (op.Shift) { - m = context.ShiftLeft(m, Const(op.Size)); + Operand n = GetIntOrSP(context, op.Rn); + + Operand m = GetExtendedM(context, op.Rm, op.IntType); + + if (op.Shift) + { + m = context.ShiftLeft(m, Const(op.Size)); + } + + address = context.Add(n, m); + + if (addend != 0) + { + address = context.Add(address, Const(addend)); + } + + break; } - - address = context.Add(n, m); - - if (addend != 0) - { - address = context.Add(address, Const(addend)); - } - - break; - } } return address; @@ -181,4 +181,4 @@ namespace ARMeilleure.Instructions } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitMemory32.cs b/src/ARMeilleure/Instructions/InstEmitMemory32.cs index 17ec97aa..cee06700 100644 --- a/src/ARMeilleure/Instructions/InstEmitMemory32.cs +++ b/src/ARMeilleure/Instructions/InstEmitMemory32.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; using System; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitMemoryHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -12,18 +11,18 @@ namespace ARMeilleure.Instructions { static partial class InstEmit32 { - private const int ByteSizeLog2 = 0; + private const int ByteSizeLog2 = 0; private const int HWordSizeLog2 = 1; - private const int WordSizeLog2 = 2; + private const int WordSizeLog2 = 2; private const int DWordSizeLog2 = 3; [Flags] enum AccessType { - Store = 0, - Signed = 1, - Load = 2, - Ordered = 4, + Store = 0, + Signed = 1, + Load = 2, + Ordered = 4, Exclusive = 8, LoadZx = Load, @@ -47,7 +46,7 @@ namespace ARMeilleure.Instructions SetIntA32(context, op.Rn, context.Add(n, Const(op.PostOffset))); } - int mask = op.RegisterMask; + int mask = op.RegisterMask; int offset = 0; for (int register = 0; mask != 0; mask >>= 1, register++) @@ -101,7 +100,7 @@ namespace ARMeilleure.Instructions Operand baseAddress = context.Add(n, Const(op.Offset)); - int mask = op.RegisterMask; + int mask = op.RegisterMask; int offset = 0; for (int register = 0; mask != 0; mask >>= 1, register++) @@ -161,7 +160,7 @@ namespace ARMeilleure.Instructions if (op.Index || op.WBack) { temp = op.Add - ? context.Add (n, m) + ? context.Add(n, m) : context.Subtract(n, m); } @@ -200,7 +199,7 @@ namespace ARMeilleure.Instructions if (size == DWordSizeLog2) { Operand lblBigEndian = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag)); @@ -233,7 +232,7 @@ namespace ARMeilleure.Instructions if (size == DWordSizeLog2) { Operand lblBigEndian = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag)); @@ -262,4 +261,4 @@ namespace ARMeilleure.Instructions SetIntA32(context, op.Rd, Const(op.Immediate)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs b/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs index c7ed01e3..8c95b33c 100644 --- a/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs +++ b/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; using System.Diagnostics; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitMemoryExHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -15,10 +14,10 @@ namespace ARMeilleure.Instructions [Flags] private enum AccessType { - None = 0, - Ordered = 1, + None = 0, + Ordered = 1, Exclusive = 2, - OrderedEx = Ordered | Exclusive + OrderedEx = Ordered | Exclusive, } public static void Clrex(ArmEmitterContext context) @@ -34,10 +33,10 @@ namespace ARMeilleure.Instructions public static void Dmb(ArmEmitterContext context) => EmitBarrier(context); public static void Dsb(ArmEmitterContext context) => EmitBarrier(context); - public static void Ldar(ArmEmitterContext context) => EmitLdr(context, AccessType.Ordered); + public static void Ldar(ArmEmitterContext context) => EmitLdr(context, AccessType.Ordered); public static void Ldaxr(ArmEmitterContext context) => EmitLdr(context, AccessType.OrderedEx); - public static void Ldxr(ArmEmitterContext context) => EmitLdr(context, AccessType.Exclusive); - public static void Ldxp(ArmEmitterContext context) => EmitLdp(context, AccessType.Exclusive); + public static void Ldxr(ArmEmitterContext context) => EmitLdr(context, AccessType.Exclusive); + public static void Ldxp(ArmEmitterContext context) => EmitLdp(context, AccessType.Exclusive); public static void Ldaxp(ArmEmitterContext context) => EmitLdp(context, AccessType.OrderedEx); private static void EmitLdr(ArmEmitterContext context, AccessType accType) @@ -54,7 +53,7 @@ namespace ARMeilleure.Instructions { OpCodeMemEx op = (OpCodeMemEx)context.CurrOp; - bool ordered = (accType & AccessType.Ordered) != 0; + bool ordered = (accType & AccessType.Ordered) != 0; bool exclusive = (accType & AccessType.Exclusive) != 0; if (ordered) @@ -80,17 +79,17 @@ namespace ARMeilleure.Instructions Operand valueHigh = context.ShiftRightUI(value, Const(32)); - SetIntOrZR(context, op.Rt, valueLow); + SetIntOrZR(context, op.Rt, valueLow); SetIntOrZR(context, op.Rt2, valueHigh); } else if (op.Size == 3) { Operand value = EmitLoadExclusive(context, address, exclusive, 4); - Operand valueLow = context.VectorExtract(OperandType.I64, value, 0); + Operand valueLow = context.VectorExtract(OperandType.I64, value, 0); Operand valueHigh = context.VectorExtract(OperandType.I64, value, 1); - SetIntOrZR(context, op.Rt, valueLow); + SetIntOrZR(context, op.Rt, valueLow); SetIntOrZR(context, op.Rt2, valueHigh); } else @@ -112,10 +111,10 @@ namespace ARMeilleure.Instructions // Memory Prefetch, execute as no-op. } - public static void Stlr(ArmEmitterContext context) => EmitStr(context, AccessType.Ordered); + public static void Stlr(ArmEmitterContext context) => EmitStr(context, AccessType.Ordered); public static void Stlxr(ArmEmitterContext context) => EmitStr(context, AccessType.OrderedEx); - public static void Stxr(ArmEmitterContext context) => EmitStr(context, AccessType.Exclusive); - public static void Stxp(ArmEmitterContext context) => EmitStp(context, AccessType.Exclusive); + public static void Stxr(ArmEmitterContext context) => EmitStr(context, AccessType.Exclusive); + public static void Stxp(ArmEmitterContext context) => EmitStp(context, AccessType.Exclusive); public static void Stlxp(ArmEmitterContext context) => EmitStp(context, AccessType.OrderedEx); private static void EmitStr(ArmEmitterContext context, AccessType accType) @@ -132,7 +131,7 @@ namespace ARMeilleure.Instructions { OpCodeMemEx op = (OpCodeMemEx)context.CurrOp; - bool ordered = (accType & AccessType.Ordered) != 0; + bool ordered = (accType & AccessType.Ordered) != 0; bool exclusive = (accType & AccessType.Exclusive) != 0; Operand address = context.Copy(GetIntOrSP(context, op.Rn)); @@ -153,8 +152,8 @@ namespace ARMeilleure.Instructions } else /* if (op.Size == 3) */ { - value = context.VectorInsert(context.VectorZero(), t, 0); - value = context.VectorInsert(value, t2, 1); + value = context.VectorInsert(context.VectorZero(), t, 0); + value = context.VectorInsert(value, t2, 1); } EmitStoreExclusive(context, address, value, exclusive, op.Size + 1, op.Rs, a32: false); @@ -175,4 +174,4 @@ namespace ARMeilleure.Instructions context.MemoryBarrier(); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs b/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs index 9a69442a..c9a99a3b 100644 --- a/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs @@ -1,7 +1,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -33,7 +32,7 @@ namespace ARMeilleure.Instructions Operand arg0 = context.LoadArgument(OperandType.I64, 0); - Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset())); + Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset())); Operand exValuePtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveValueOffset())); context.Store(exAddrPtr, context.BitwiseAnd(address, Const(address.Type, GetExclusiveAddressMask()))); @@ -118,14 +117,14 @@ namespace ARMeilleure.Instructions 1 => context.Load16(exValuePtr), 2 => context.Load(OperandType.I32, exValuePtr), 3 => context.Load(OperandType.I64, exValuePtr), - _ => context.Load(OperandType.V128, exValuePtr) + _ => context.Load(OperandType.V128, exValuePtr), }; Operand currValue = size switch { 0 => context.CompareAndSwap8(physAddr, exValue, value), 1 => context.CompareAndSwap16(physAddr, exValue, value), - _ => context.CompareAndSwap(physAddr, exValue, value) + _ => context.CompareAndSwap(physAddr, exValue, value), }; // STEP 3: Check if we succeeded by comparing expected and in-memory values. @@ -133,14 +132,14 @@ namespace ARMeilleure.Instructions if (size == 4) { - Operand currValueLow = context.VectorExtract(OperandType.I64, currValue, 0); + Operand currValueLow = context.VectorExtract(OperandType.I64, currValue, 0); Operand currValueHigh = context.VectorExtract(OperandType.I64, currValue, 1); - Operand exValueLow = context.VectorExtract(OperandType.I64, exValue, 0); + Operand exValueLow = context.VectorExtract(OperandType.I64, exValue, 0); Operand exValueHigh = context.VectorExtract(OperandType.I64, exValue, 1); storeFailed = context.BitwiseOr( - context.ICompareNotEqual(currValueLow, exValueLow), + context.ICompareNotEqual(currValueLow, exValueLow), context.ICompareNotEqual(currValueHigh, exValueHigh)); } else diff --git a/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs b/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs index f97e395c..a807eed5 100644 --- a/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs @@ -5,7 +5,6 @@ using ARMeilleure.Translation; using ARMeilleure.Translation.PTC; using System; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -20,7 +19,7 @@ namespace ARMeilleure.Instructions { Zx, Sx32, - Sx64 + Sx64, } public static void EmitLoadZx(ArmEmitterContext context, Operand address, int rt, int size) @@ -66,9 +65,15 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: value = context.SignExtend8 (destType, value); break; - case 1: value = context.SignExtend16(destType, value); break; - case 2: value = context.SignExtend32(destType, value); break; + case 0: + value = context.SignExtend8(destType, value); + break; + case 1: + value = context.SignExtend16(destType, value); + break; + case 2: + value = context.SignExtend32(destType, value); + break; } } @@ -128,7 +133,7 @@ namespace ARMeilleure.Instructions Operand temp = context.AllocateLocal(size == 3 ? OperandType.I64 : OperandType.I32); Operand lblSlowPath = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size); @@ -136,10 +141,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: value = context.Load8 (physAddr); break; - case 1: value = context.Load16(physAddr); break; - case 2: value = context.Load (OperandType.I32, physAddr); break; - case 3: value = context.Load (OperandType.I64, physAddr); break; + case 0: + value = context.Load8(physAddr); + break; + case 1: + value = context.Load16(physAddr); + break; + case 2: + value = context.Load(OperandType.I32, physAddr); + break; + case 3: + value = context.Load(OperandType.I64, physAddr); + break; } context.Copy(temp, value); @@ -161,7 +174,7 @@ namespace ARMeilleure.Instructions private static void EmitReadInt(ArmEmitterContext context, Operand address, int rt, int size) { Operand lblSlowPath = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size); @@ -169,10 +182,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: value = context.Load8 (physAddr); break; - case 1: value = context.Load16(physAddr); break; - case 2: value = context.Load (OperandType.I32, physAddr); break; - case 3: value = context.Load (OperandType.I64, physAddr); break; + case 0: + value = context.Load8(physAddr); + break; + case 1: + value = context.Load16(physAddr); + break; + case 2: + value = context.Load(OperandType.I32, physAddr); + break; + case 3: + value = context.Load(OperandType.I64, physAddr); + break; } SetInt(context, rt, value); @@ -204,7 +225,7 @@ namespace ARMeilleure.Instructions 1 => context.Load16(physAddr), 2 => context.Load(OperandType.I32, physAddr), 3 => context.Load(OperandType.I64, physAddr), - _ => context.Load(OperandType.V128, physAddr) + _ => context.Load(OperandType.V128, physAddr), }; } @@ -217,7 +238,7 @@ namespace ARMeilleure.Instructions int size) { Operand lblSlowPath = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size); @@ -225,11 +246,21 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: value = context.VectorInsert8 (vector, context.Load8(physAddr), elem); break; - case 1: value = context.VectorInsert16(vector, context.Load16(physAddr), elem); break; - case 2: value = context.VectorInsert (vector, context.Load(OperandType.I32, physAddr), elem); break; - case 3: value = context.VectorInsert (vector, context.Load(OperandType.I64, physAddr), elem); break; - case 4: value = context.Load (OperandType.V128, physAddr); break; + case 0: + value = context.VectorInsert8(vector, context.Load8(physAddr), elem); + break; + case 1: + value = context.VectorInsert16(vector, context.Load16(physAddr), elem); + break; + case 2: + value = context.VectorInsert(vector, context.Load(OperandType.I32, physAddr), elem); + break; + case 3: + value = context.VectorInsert(vector, context.Load(OperandType.I64, physAddr), elem); + break; + case 4: + value = context.Load(OperandType.V128, physAddr); + break; } context.Copy(GetVec(rt), value); @@ -254,7 +285,7 @@ namespace ARMeilleure.Instructions private static void EmitWriteInt(ArmEmitterContext context, Operand address, int rt, int size) { Operand lblSlowPath = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true, size); @@ -267,10 +298,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: context.Store8 (physAddr, value); break; - case 1: context.Store16(physAddr, value); break; - case 2: context.Store (physAddr, value); break; - case 3: context.Store (physAddr, value); break; + case 0: + context.Store8(physAddr, value); + break; + case 1: + context.Store16(physAddr, value); + break; + case 2: + context.Store(physAddr, value); + break; + case 3: + context.Store(physAddr, value); + break; } if (!context.Memory.Type.IsHostMapped()) @@ -321,7 +360,7 @@ namespace ARMeilleure.Instructions int size) { Operand lblSlowPath = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true, size); @@ -329,11 +368,21 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: context.Store8 (physAddr, context.VectorExtract8(value, elem)); break; - case 1: context.Store16(physAddr, context.VectorExtract16(value, elem)); break; - case 2: context.Store (physAddr, context.VectorExtract(OperandType.I32, value, elem)); break; - case 3: context.Store (physAddr, context.VectorExtract(OperandType.I64, value, elem)); break; - case 4: context.Store (physAddr, value); break; + case 0: + context.Store8(physAddr, context.VectorExtract8(value, elem)); + break; + case 1: + context.Store16(physAddr, context.VectorExtract16(value, elem)); + break; + case 2: + context.Store(physAddr, context.VectorExtract(OperandType.I32, value, elem)); + break; + case 3: + context.Store(physAddr, context.VectorExtract(OperandType.I64, value, elem)); + break; + case 4: + context.Store(physAddr, value); + break; } if (!context.Memory.Type.IsHostMapped()) @@ -464,10 +513,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); break; - case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); break; - case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); break; - case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break; + case 0: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); + break; + case 1: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); + break; + case 2: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); + break; + case 3: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); + break; } return context.Call(info, address); @@ -485,21 +542,39 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); break; - case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); break; - case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); break; - case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break; - case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadVector128)); break; + case 0: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); + break; + case 1: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); + break; + case 2: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); + break; + case 3: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); + break; + case 4: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadVector128)); + break; } Operand value = context.Call(info, address); switch (size) { - case 0: value = context.VectorInsert8 (vector, value, elem); break; - case 1: value = context.VectorInsert16(vector, value, elem); break; - case 2: value = context.VectorInsert (vector, value, elem); break; - case 3: value = context.VectorInsert (vector, value, elem); break; + case 0: + value = context.VectorInsert8(vector, value, elem); + break; + case 1: + value = context.VectorInsert16(vector, value, elem); + break; + case 2: + value = context.VectorInsert(vector, value, elem); + break; + case 3: + value = context.VectorInsert(vector, value, elem); + break; } context.Copy(GetVec(rt), value); @@ -511,10 +586,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); break; - case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); break; - case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); break; - case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); break; + case 0: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); + break; + case 1: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); + break; + case 2: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); + break; + case 3: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); + break; } Operand value = GetInt(context, rt); @@ -538,11 +621,21 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); break; - case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); break; - case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); break; - case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); break; - case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128)); break; + case 0: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); + break; + case 1: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); + break; + case 2: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); + break; + case 3: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); + break; + case 4: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128)); + break; } Operand value = default; @@ -551,10 +644,18 @@ namespace ARMeilleure.Instructions { switch (size) { - case 0: value = context.VectorExtract8 (GetVec(rt), elem); break; - case 1: value = context.VectorExtract16(GetVec(rt), elem); break; - case 2: value = context.VectorExtract (OperandType.I32, GetVec(rt), elem); break; - case 3: value = context.VectorExtract (OperandType.I64, GetVec(rt), elem); break; + case 0: + value = context.VectorExtract8(GetVec(rt), elem); + break; + case 1: + value = context.VectorExtract16(GetVec(rt), elem); + break; + case 2: + value = context.VectorExtract(OperandType.I32, GetVec(rt), elem); + break; + case 3: + value = context.VectorExtract(OperandType.I64, GetVec(rt), elem); + break; } } else @@ -585,18 +686,14 @@ namespace ARMeilleure.Instructions // ARM32 helpers. public static Operand GetMemM(ArmEmitterContext context, bool setCarry = true) { - switch (context.CurrOp) + return context.CurrOp switch { - case IOpCode32MemRsImm op: return GetMShiftedByImmediate(context, op, setCarry); - - case IOpCode32MemReg op: return GetIntA32(context, op.Rm); - - case IOpCode32Mem op: return Const(op.Immediate); - - case OpCode32SimdMemImm op: return Const(op.Immediate); - - default: throw InvalidOpCodeType(context.CurrOp); - } + IOpCode32MemRsImm op => GetMShiftedByImmediate(context, op, setCarry), + IOpCode32MemReg op => GetIntA32(context, op.Rm), + IOpCode32Mem op => Const(op.Immediate), + OpCode32SimdMemImm op => Const(op.Immediate), + _ => throw InvalidOpCodeType(context.CurrOp), + }; } private static Exception InvalidOpCodeType(OpCode opCode) @@ -614,9 +711,15 @@ namespace ARMeilleure.Instructions { switch (op.ShiftType) { - case ShiftType.Lsr: shift = 32; break; - case ShiftType.Asr: shift = 32; break; - case ShiftType.Ror: shift = 1; break; + case ShiftType.Lsr: + shift = 32; + break; + case ShiftType.Asr: + shift = 32; + break; + case ShiftType.Ror: + shift = 1; + break; } } @@ -626,9 +729,15 @@ namespace ARMeilleure.Instructions switch (op.ShiftType) { - case ShiftType.Lsl: m = InstEmitAluHelper.GetLslC(context, m, setCarry, shift); break; - case ShiftType.Lsr: m = InstEmitAluHelper.GetLsrC(context, m, setCarry, shift); break; - case ShiftType.Asr: m = InstEmitAluHelper.GetAsrC(context, m, setCarry, shift); break; + case ShiftType.Lsl: + m = InstEmitAluHelper.GetLslC(context, m, setCarry, shift); + break; + case ShiftType.Lsr: + m = InstEmitAluHelper.GetLsrC(context, m, setCarry, shift); + break; + case ShiftType.Asr: + m = InstEmitAluHelper.GetAsrC(context, m, setCarry, shift); + break; case ShiftType.Ror: if (op.Immediate != 0) { diff --git a/src/ARMeilleure/Instructions/InstEmitMove.cs b/src/ARMeilleure/Instructions/InstEmitMove.cs index d551bf2d..f23ac333 100644 --- a/src/ARMeilleure/Instructions/InstEmitMove.cs +++ b/src/ARMeilleure/Instructions/InstEmitMove.cs @@ -38,4 +38,4 @@ namespace ARMeilleure.Instructions SetIntOrZR(context, op.Rd, Const(op.GetOperandType(), op.Immediate)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitMul.cs b/src/ARMeilleure/Instructions/InstEmitMul.cs index 65d11b30..89dc0993 100644 --- a/src/ARMeilleure/Instructions/InstEmitMul.cs +++ b/src/ARMeilleure/Instructions/InstEmitMul.cs @@ -2,7 +2,7 @@ using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; - +using System.Diagnostics.CodeAnalysis; using static ARMeilleure.Instructions.InstEmitHelper; namespace ARMeilleure.Instructions @@ -33,14 +33,15 @@ namespace ARMeilleure.Instructions public static void Umsubl(ArmEmitterContext context) => EmitMull(context, MullFlags.Subtract); [Flags] + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] private enum MullFlags { Subtract = 0, - Add = 1 << 0, - Signed = 1 << 1, + Add = 1 << 0, + Signed = 1 << 1, - SignedAdd = Signed | Add, - SignedSubtract = Signed | Subtract + SignedAdd = Signed | Add, + SignedSubtract = Signed | Subtract, } private static void EmitMull(ArmEmitterContext context, MullFlags flags) @@ -97,4 +98,4 @@ namespace ARMeilleure.Instructions SetIntOrZR(context, op.Rd, d); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitMul32.cs b/src/ARMeilleure/Instructions/InstEmitMul32.cs index 0822f92c..b9680fb6 100644 --- a/src/ARMeilleure/Instructions/InstEmitMul32.cs +++ b/src/ARMeilleure/Instructions/InstEmitMul32.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; using System; - using static ARMeilleure.Instructions.InstEmitAluHelper; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -20,7 +19,7 @@ namespace ARMeilleure.Instructions Signed = 1 << 2, SignedAdd = Signed | Add, - SignedSubtract = Signed | Subtract + SignedSubtract = Signed | Subtract, } public static void Mla(ArmEmitterContext context) @@ -287,14 +286,14 @@ namespace ARMeilleure.Instructions { IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp; - Operand n = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn)); - Operand m = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm)); + Operand n = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn)); + Operand m = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm)); Operand dHi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.RdHi)); Operand dLo = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.RdLo)); Operand res = context.Multiply(n, m); - res = context.Add(res, dHi); - res = context.Add(res, dLo); + res = context.Add(res, dHi); + res = context.Add(res, dLo); Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32))); Operand lo = context.ConvertI64ToI32(res); diff --git a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs index 7e7f26b1..7b308fa9 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs @@ -7,7 +7,6 @@ using ARMeilleure.State; using ARMeilleure.Translation; using System; using System.Diagnostics; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper32; @@ -185,11 +184,12 @@ namespace ARMeilleure.Instructions int eSize = 8 << op.Size; - Operand res = eSize switch { - 8 => Clz_V_I8 (context, GetVec(op.Rn)), + Operand res = eSize switch + { + 8 => Clz_V_I8(context, GetVec(op.Rn)), 16 => Clz_V_I16(context, GetVec(op.Rn)), 32 => Clz_V_I32(context, GetVec(op.Rn)), - _ => default + _ => default, }; if (res != default) @@ -230,14 +230,14 @@ namespace ARMeilleure.Instructions Operand clzTable = X86GetScalar(context, 0x01_01_01_01_02_02_03_04); Operand maskLow = X86GetAllElements(context, 0x0f_0f_0f_0f); - Operand c04 = X86GetAllElements(context, 0x04_04_04_04); + Operand c04 = X86GetAllElements(context, 0x04_04_04_04); // CLZ of low 4 bits of elements in arg. Operand loClz = context.AddIntrinsic(Intrinsic.X86Pshufb, clzTable, arg); // Get the high 4 bits of elements in arg. Operand hiArg = context.AddIntrinsic(Intrinsic.X86Psrlw, arg, Const(4)); - hiArg = context.AddIntrinsic(Intrinsic.X86Pand, hiArg, maskLow); + hiArg = context.AddIntrinsic(Intrinsic.X86Pand, hiArg, maskLow); // CLZ of high 4 bits of elements in arg. Operand hiClz = context.AddIntrinsic(Intrinsic.X86Pshufb, clzTable, hiArg); @@ -257,8 +257,8 @@ namespace ARMeilleure.Instructions } Operand maskSwap = X86GetElements(context, 0x80_0f_80_0d_80_0b_80_09, 0x80_07_80_05_80_03_80_01); - Operand maskLow = X86GetAllElements(context, 0x00ff_00ff); - Operand c0008 = X86GetAllElements(context, 0x0008_0008); + Operand maskLow = X86GetAllElements(context, 0x00ff_00ff); + Operand c0008 = X86GetAllElements(context, 0x0008_0008); // CLZ pair of high 8 and low 8 bits of elements in arg. Operand hiloClz = Clz_V_I8(context, arg); @@ -282,12 +282,14 @@ namespace ARMeilleure.Instructions return default; } +#pragma warning disable IDE0055 // Disable formatting Operand AddVectorI32(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Paddd, op0, op1); Operand SubVectorI32(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Psubd, op0, op1); Operand ShiftRightVectorUI32(Operand op0, int imm8) => context.AddIntrinsic(Intrinsic.X86Psrld, op0, Const(imm8)); Operand OrVector(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Por, op0, op1); Operand AndVector(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Pand, op0, op1); Operand NotVector(Operand op0) => context.AddIntrinsic(Intrinsic.X86Pandn, op0, context.VectorOne()); +#pragma warning restore IDE0055 Operand c55555555 = X86GetAllElements(context, 0x55555555); Operand c33333333 = X86GetAllElements(context, 0x33333333); @@ -311,24 +313,24 @@ namespace ARMeilleure.Instructions // Count leading 1s, which is the population count. tmp0 = ShiftRightVectorUI32(res, 1); tmp0 = AndVector(tmp0, c55555555); - res = SubVectorI32(res, tmp0); + res = SubVectorI32(res, tmp0); tmp0 = ShiftRightVectorUI32(res, 2); tmp0 = AndVector(tmp0, c33333333); tmp1 = AndVector(res, c33333333); - res = AddVectorI32(tmp0, tmp1); + res = AddVectorI32(tmp0, tmp1); tmp0 = ShiftRightVectorUI32(res, 4); tmp0 = AddVectorI32(tmp0, res); - res = AndVector(tmp0, c0f0f0f0f); + res = AndVector(tmp0, c0f0f0f0f); tmp0 = ShiftRightVectorUI32(res, 8); - res = AddVectorI32(tmp0, res); + res = AddVectorI32(tmp0, res); tmp0 = ShiftRightVectorUI32(res, 16); - res = AddVectorI32(tmp0, res); + res = AddVectorI32(tmp0, res); - res = AndVector(res, c0000003f); + res = AndVector(res, c0000003f); return res; } @@ -2436,8 +2438,8 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { - Operand maskHalf = X86GetScalar(context, 0.5f); - Operand maskThree = X86GetScalar(context, 3f); + Operand maskHalf = X86GetScalar(context, 0.5f); + Operand maskThree = X86GetScalar(context, 3f); Operand maskOneHalf = X86GetScalar(context, 1.5f); if (Optimizations.UseFma) @@ -2457,8 +2459,8 @@ namespace ARMeilleure.Instructions } else /* if (sizeF == 1) */ { - Operand maskHalf = X86GetScalar(context, 0.5d); - Operand maskThree = X86GetScalar(context, 3d); + Operand maskHalf = X86GetScalar(context, 0.5d); + Operand maskThree = X86GetScalar(context, 3d); Operand maskOneHalf = X86GetScalar(context, 1.5d); if (Optimizations.UseFma) @@ -2505,8 +2507,8 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { - Operand maskHalf = X86GetAllElements(context, 0.5f); - Operand maskThree = X86GetAllElements(context, 3f); + Operand maskHalf = X86GetAllElements(context, 0.5f); + Operand maskThree = X86GetAllElements(context, 3f); Operand maskOneHalf = X86GetAllElements(context, 1.5f); if (Optimizations.UseFma) @@ -2519,7 +2521,7 @@ namespace ARMeilleure.Instructions res = context.AddIntrinsic(Intrinsic.X86Subps, maskThree, res); } - res = context.AddIntrinsic(Intrinsic.X86Mulps, maskHalf, res); + res = context.AddIntrinsic(Intrinsic.X86Mulps, maskHalf, res); res = EmitSse41RecipStepSelectOpF(context, n, m, res, maskOneHalf, scalar: false, sizeF); if (op.RegisterSize == RegisterSize.Simd64) @@ -2531,8 +2533,8 @@ namespace ARMeilleure.Instructions } else /* if (sizeF == 1) */ { - Operand maskHalf = X86GetAllElements(context, 0.5d); - Operand maskThree = X86GetAllElements(context, 3d); + Operand maskHalf = X86GetAllElements(context, 0.5d); + Operand maskThree = X86GetAllElements(context, 3d); Operand maskOneHalf = X86GetAllElements(context, 1.5d); if (Optimizations.UseFma) @@ -2545,7 +2547,7 @@ namespace ARMeilleure.Instructions res = context.AddIntrinsic(Intrinsic.X86Subpd, maskThree, res); } - res = context.AddIntrinsic(Intrinsic.X86Mulpd, maskHalf, res); + res = context.AddIntrinsic(Intrinsic.X86Mulpd, maskHalf, res); res = EmitSse41RecipStepSelectOpF(context, n, m, res, maskOneHalf, scalar: false, sizeF); context.Copy(GetVec(op.Rd), res); @@ -2824,10 +2826,10 @@ namespace ARMeilleure.Instructions for (int i = 0; i < 8; i++) { Operand mask = context.AddIntrinsic(Intrinsic.X86Psllw, n, Const(15 - i)); - mask = context.AddIntrinsic(Intrinsic.X86Psraw, mask, Const(15)); + mask = context.AddIntrinsic(Intrinsic.X86Psraw, mask, Const(15)); Operand tmp = context.AddIntrinsic(Intrinsic.X86Psllw, m, Const(i)); - tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask); + tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask); res = context.AddIntrinsic(Intrinsic.X86Pxor, res, tmp); } @@ -2839,12 +2841,12 @@ namespace ARMeilleure.Instructions for (int i = 0; i < 64; i++) { Operand mask = context.AddIntrinsic(Intrinsic.X86Movlhps, n, n); - mask = context.AddIntrinsic(Intrinsic.X86Psllq, mask, Const(63 - i)); - mask = context.AddIntrinsic(Intrinsic.X86Psrlq, mask, Const(63)); - mask = context.AddIntrinsic(Intrinsic.X86Psubq, zero, mask); + mask = context.AddIntrinsic(Intrinsic.X86Psllq, mask, Const(63 - i)); + mask = context.AddIntrinsic(Intrinsic.X86Psrlq, mask, Const(63)); + mask = context.AddIntrinsic(Intrinsic.X86Psubq, zero, mask); Operand tmp = EmitSse2Sll_128(context, m, i); - tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask); + tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask); res = context.AddIntrinsic(Intrinsic.X86Pxor, res, tmp); } @@ -3119,7 +3121,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand m = GetVec(op.Rm); - Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m); + Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m); Operand res2 = context.AddIntrinsic(Intrinsic.X86Pxor, n, m); Intrinsic shiftInst = op.Size == 1 ? Intrinsic.X86Psraw : Intrinsic.X86Psrad; @@ -4058,7 +4060,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand m = GetVec(op.Rm); - Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m); + Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m); Operand res2 = context.AddIntrinsic(Intrinsic.X86Pxor, n, m); Intrinsic shiftInst = op.Size == 1 ? Intrinsic.X86Psrlw : Intrinsic.X86Psrld; @@ -4594,7 +4596,7 @@ namespace ARMeilleure.Instructions { int pairIndex = index << 1; - Operand ne0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed); + Operand ne0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed); Operand ne1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed); Operand e = context.Add(ne0, ne1); @@ -4686,7 +4688,7 @@ namespace ARMeilleure.Instructions Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64); Operand cmp = signed - ? context.ICompareGreaterOrEqual (op1, op2) + ? context.ICompareGreaterOrEqual(op1, op2) : context.ICompareGreaterOrEqualUI(op1, op2); return context.ConditionalSelect(cmp, op1, op2); @@ -4697,7 +4699,7 @@ namespace ARMeilleure.Instructions Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64); Operand cmp = signed - ? context.ICompareLessOrEqual (op1, op2) + ? context.ICompareLessOrEqual(op1, op2) : context.ICompareLessOrEqualUI(op1, op2); return context.ConditionalSelect(cmp, op1, op2); @@ -4852,10 +4854,10 @@ namespace ARMeilleure.Instructions Operand mask1 = context.AddIntrinsic(Intrinsic.X86Cmpps, opF, opF, Const((int)CmpCondition.UnorderedQ)); - Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask); - mask2 = context.AddIntrinsic(Intrinsic.X86Cmpps, mask2, qMask, Const((int)CmpCondition.Equal)); + Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask); + mask2 = context.AddIntrinsic(Intrinsic.X86Cmpps, mask2, qMask, Const((int)CmpCondition.Equal)); - qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andps, mask2, mask1) : default; + qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andps, mask2, mask1) : default; sNaNMask = isQNaN == null || !(bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andnps, mask2, mask1) : default; } else /* if ((op.Size & 1) == 1) */ @@ -4866,10 +4868,10 @@ namespace ARMeilleure.Instructions Operand mask1 = context.AddIntrinsic(Intrinsic.X86Cmppd, opF, opF, Const((int)CmpCondition.UnorderedQ)); - Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask); - mask2 = context.AddIntrinsic(Intrinsic.X86Cmppd, mask2, qMask, Const((int)CmpCondition.Equal)); + Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask); + mask2 = context.AddIntrinsic(Intrinsic.X86Cmppd, mask2, qMask, Const((int)CmpCondition.Equal)); - qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andpd, mask2, mask1) : default; + qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andpd, mask2, mask1) : default; sNaNMask = isQNaN == null || !(bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andnpd, mask2, mask1) : default; } } @@ -4895,11 +4897,11 @@ namespace ARMeilleure.Instructions Operand qMask = scalar ? X86GetScalar(context, 1 << QBit) : X86GetAllElements(context, 1 << QBit); - Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask); - resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask); + Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask); + resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask); Operand resNaN = context.AddIntrinsic(Intrinsic.X86Blendvps, mCopy, nCopy, resNaNMask); - resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask); + resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask); Operand resMask = context.AddIntrinsic(Intrinsic.X86Cmpps, nCopy, mCopy, Const((int)CmpCondition.OrderedQ)); @@ -4929,11 +4931,11 @@ namespace ARMeilleure.Instructions Operand qMask = scalar ? X86GetScalar(context, 1L << QBit) : X86GetAllElements(context, 1L << QBit); - Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask); - resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask); + Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask); + resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask); Operand resNaN = context.AddIntrinsic(Intrinsic.X86Blendvpd, mCopy, nCopy, resNaNMask); - resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask); + resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask); Operand resMask = context.AddIntrinsic(Intrinsic.X86Cmppd, nCopy, mCopy, Const((int)CmpCondition.OrderedQ)); @@ -4964,10 +4966,10 @@ namespace ARMeilleure.Instructions Operand mask = X86GetAllElements(context, -0f); Operand res = context.AddIntrinsic(isMax ? Intrinsic.X86Maxps : Intrinsic.X86Minps, n, m); - res = context.AddIntrinsic(Intrinsic.X86Andnps, mask, res); + res = context.AddIntrinsic(Intrinsic.X86Andnps, mask, res); Operand resSign = context.AddIntrinsic(isMax ? Intrinsic.X86Pand : Intrinsic.X86Por, n, m); - resSign = context.AddIntrinsic(Intrinsic.X86Andps, mask, resSign); + resSign = context.AddIntrinsic(Intrinsic.X86Andps, mask, resSign); return context.AddIntrinsic(Intrinsic.X86Por, res, resSign); } @@ -4976,10 +4978,10 @@ namespace ARMeilleure.Instructions Operand mask = X86GetAllElements(context, -0d); Operand res = context.AddIntrinsic(isMax ? Intrinsic.X86Maxpd : Intrinsic.X86Minpd, n, m); - res = context.AddIntrinsic(Intrinsic.X86Andnpd, mask, res); + res = context.AddIntrinsic(Intrinsic.X86Andnpd, mask, res); Operand resSign = context.AddIntrinsic(isMax ? Intrinsic.X86Pand : Intrinsic.X86Por, n, m); - resSign = context.AddIntrinsic(Intrinsic.X86Andpd, mask, resSign); + resSign = context.AddIntrinsic(Intrinsic.X86Andpd, mask, resSign); return context.AddIntrinsic(Intrinsic.X86Por, res, resSign); } @@ -5003,7 +5005,7 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { Operand negInfMask = scalar - ? X86GetScalar (context, isMaxNum ? float.NegativeInfinity : float.PositiveInfinity) + ? X86GetScalar(context, isMaxNum ? float.NegativeInfinity : float.PositiveInfinity) : X86GetAllElements(context, isMaxNum ? float.NegativeInfinity : float.PositiveInfinity); Operand nMask = context.AddIntrinsic(Intrinsic.X86Andnps, mQNaNMask, nQNaNMask); @@ -5038,7 +5040,7 @@ namespace ARMeilleure.Instructions else /* if (sizeF == 1) */ { Operand negInfMask = scalar - ? X86GetScalar (context, isMaxNum ? double.NegativeInfinity : double.PositiveInfinity) + ? X86GetScalar(context, isMaxNum ? double.NegativeInfinity : double.PositiveInfinity) : X86GetAllElements(context, isMaxNum ? double.NegativeInfinity : double.PositiveInfinity); Operand nMask = context.AddIntrinsic(Intrinsic.X86Andnpd, mQNaNMask, nQNaNMask); @@ -5072,7 +5074,7 @@ namespace ARMeilleure.Instructions { None, Add, - Subtract + Subtract, } private static void EmitSse41VectorMul_AddSub(ArmEmitterContext context, AddSub addSub) @@ -5187,10 +5189,10 @@ namespace ARMeilleure.Instructions Intrinsic subInst = X86PsubInstruction[size]; - Operand res = context.AddIntrinsic(subInst, n, m); + Operand res = context.AddIntrinsic(subInst, n, m); Operand res2 = context.AddIntrinsic(subInst, m, n); - res = context.AddIntrinsic(Intrinsic.X86Pand, cmpMask, res); + res = context.AddIntrinsic(Intrinsic.X86Pand, cmpMask, res); res2 = context.AddIntrinsic(Intrinsic.X86Pandn, cmpMask, res2); res = context.AddIntrinsic(Intrinsic.X86Por, res, res2); @@ -5214,7 +5216,7 @@ namespace ARMeilleure.Instructions } Operand high = context.AddIntrinsic(Intrinsic.X86Pslldq, op, Const(8)); - high = context.AddIntrinsic(Intrinsic.X86Psrlq, high, Const(64 - shift)); + high = context.AddIntrinsic(Intrinsic.X86Psrlq, high, Const(64 - shift)); Operand low = context.AddIntrinsic(Intrinsic.X86Psllq, op, Const(shift)); diff --git a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs index a9994e41..1d99cbc3 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs @@ -2,7 +2,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; - using static ARMeilleure.Instructions.InstEmitFlowHelper; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; @@ -190,7 +189,7 @@ namespace ARMeilleure.Instructions 2 => context.Multiply(context.ZeroExtend32(OperandType.I64, insert), Const(0x0000000100000001u)), 1 => context.Multiply(context.ZeroExtend16(OperandType.I64, insert), Const(0x0001000100010001u)), 0 => context.Multiply(context.ZeroExtend8(OperandType.I64, insert), Const(0x0101010101010101u)), - _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\".") + _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\"."), }; InsertScalar(context, op.Vd, insert); @@ -212,7 +211,7 @@ namespace ARMeilleure.Instructions 2 => context.Multiply(context.ZeroExtend32(OperandType.I64, insert), Const(0x0000000100000001u)), 1 => context.Multiply(context.ZeroExtend16(OperandType.I64, insert), Const(0x0001000100010001u)), 0 => context.Multiply(context.ZeroExtend8(OperandType.I64, insert), Const(0x0101010101010101u)), - _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\".") + _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\"."), }; InsertScalar(context, op.Vd, insert); @@ -1654,7 +1653,7 @@ namespace ARMeilleure.Instructions { IOpCode32Simd op = (IOpCode32Simd)context.CurrOp; - Func genericEmit = (n, m) => + Operand genericEmit(Operand n, Operand m) { Operand nNum = context.Copy(n); Operand mNum = context.Copy(m); @@ -1688,7 +1687,7 @@ namespace ARMeilleure.Instructions return context.AddIntrinsic(isMaxNum ? Intrinsic.X86Maxpd : Intrinsic.X86Minpd, nNum, mNum); } - }; + } if (scalar) { diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs b/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs index c32b64ba..aab67786 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; using System; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -493,7 +492,7 @@ namespace ARMeilleure.Instructions OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp; Operand lblTrue = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); context.BranchIfTrue(lblTrue, InstEmitFlowHelper.GetCondTrue(context, op.Cond)); @@ -510,7 +509,7 @@ namespace ARMeilleure.Instructions private static void EmitSetNzcv(ArmEmitterContext context, int nzcv) { - Operand Extract(int value, int bit) + static Operand Extract(int value, int bit) { if (bit != 0) { @@ -532,7 +531,7 @@ namespace ARMeilleure.Instructions { OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - bool cmpWithZero = !(op is OpCodeSimdFcond) ? op.Bit3 : false; + bool cmpWithZero = op is not OpCodeSimdFcond && op.Bit3; if (Optimizations.FastFP && (signalNaNs ? Optimizations.UseAvx : Optimizations.UseSse2)) { diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs b/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs index 652ad397..3363a7c7 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs @@ -5,7 +5,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -67,8 +66,8 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest))); - res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112() - res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14)); + res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112() + res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14)); context.Copy(GetVec(op.Rd), res); } @@ -92,7 +91,7 @@ namespace ARMeilleure.Instructions Debug.Assert(!Optimizations.ForceLegacySse); Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn)); - res = context.VectorZeroUpper96(res); + res = context.VectorZeroUpper96(res); context.Copy(GetVec(op.Rd), res); } @@ -116,7 +115,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n); - res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest))); + res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest))); context.Copy(GetVec(op.Rd), res); } @@ -140,8 +139,8 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn)); - res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res); - res = context.VectorZeroUpper64(res); + res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res); + res = context.VectorZeroUpper64(res); context.Copy(GetVec(op.Rd), res); } @@ -273,7 +272,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n; - res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res); + res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res); context.Copy(GetVec(op.Rd), res); } @@ -284,7 +283,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n; - res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res); + res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res); context.Copy(GetVec(op.Rd), res); } @@ -387,10 +386,10 @@ namespace ARMeilleure.Instructions Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps; Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn)); - nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt); + nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt); Operand res = context.VectorZeroUpper64(d); - res = context.AddIntrinsic(movInst, res, nInt); + res = context.AddIntrinsic(movInst, res, nInt); context.Copy(d, res); } @@ -404,10 +403,10 @@ namespace ARMeilleure.Instructions Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps; Operand nInt = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest))); - nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt); + nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt); Operand res = context.VectorZeroUpper64(d); - res = context.AddIntrinsic(movInst, res, nInt); + res = context.AddIntrinsic(movInst, res, nInt); context.Copy(d, res); } @@ -1225,15 +1224,15 @@ namespace ARMeilleure.Instructions { Debug.Assert(opF.Type == OperandType.V128); - Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL - Operand res = context.VectorCreateScalar(longL); + Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, opF); // opFL + Operand res = context.VectorCreateScalar(longL); if (!scalar) { - Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter. - Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH); - Operand resH = context.VectorCreateScalar(longH); - res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH); + Operand opFH = context.AddIntrinsic(Intrinsic.X86Movhlps, res, opF); // res doesn't matter. + Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, opFH); + Operand resH = context.VectorCreateScalar(longH); + res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, resH); } return res; @@ -1244,14 +1243,14 @@ namespace ARMeilleure.Instructions Debug.Assert(op.Type == OperandType.V128); Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL - Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL); + Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL); if (!scalar) { - Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter. + Operand opH = context.AddIntrinsic(Intrinsic.X86Movhlps, res, op); // res doesn't matter. Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH); - Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter. - res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH); + Operand resH = context.AddIntrinsic(Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter. + res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, resH); } return res; @@ -1278,7 +1277,7 @@ namespace ARMeilleure.Instructions int fpScaled = 0x3F800000 - fBits * 0x800000; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask); @@ -1307,7 +1306,7 @@ namespace ARMeilleure.Instructions long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask); @@ -1334,16 +1333,16 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { Operand mask = scalar // 65536.000f (1 << 16) - ? X86GetScalar (context, 0x47800000) + ? X86GetScalar(context, 0x47800000) : X86GetAllElements(context, 0x47800000); Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16)); - res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res); - res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask); + res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res); + res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask); Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16)); - res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16)); - res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2); + res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16)); + res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2); res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2); @@ -1355,7 +1354,7 @@ namespace ARMeilleure.Instructions int fpScaled = 0x3F800000 - fBits * 0x800000; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask); @@ -1375,16 +1374,16 @@ namespace ARMeilleure.Instructions else /* if (sizeF == 1) */ { Operand mask = scalar // 4294967296.0000000d (1L << 32) - ? X86GetScalar (context, 0x41F0000000000000L) + ? X86GetScalar(context, 0x41F0000000000000L) : X86GetAllElements(context, 0x41F0000000000000L); - Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32)); - res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar); - res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask); + Operand res = context.AddIntrinsic(Intrinsic.X86Psrlq, n, Const(32)); + res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar); + res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, mask); - Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32)); - res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32)); - res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar); + Operand res2 = context.AddIntrinsic(Intrinsic.X86Psllq, n, Const(32)); + res2 = context.AddIntrinsic(Intrinsic.X86Psrlq, res2, Const(32)); + res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar); res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2); @@ -1396,7 +1395,7 @@ namespace ARMeilleure.Instructions long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask); @@ -1423,7 +1422,7 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (op is OpCodeSimdShImm fixedOp) { @@ -1433,7 +1432,7 @@ namespace ARMeilleure.Instructions int fpScaled = 0x3F800000 + fBits * 0x800000; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask); @@ -1451,7 +1450,7 @@ namespace ARMeilleure.Instructions Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes); Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648) - ? X86GetScalar (context, 0x4F000000) + ? X86GetScalar(context, 0x4F000000) : X86GetAllElements(context, 0x4F000000); nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); @@ -1472,7 +1471,7 @@ namespace ARMeilleure.Instructions else /* if (sizeF == 1) */ { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (op is OpCodeSimdShImm fixedOp) { @@ -1482,7 +1481,7 @@ namespace ARMeilleure.Instructions long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask); @@ -1500,7 +1499,7 @@ namespace ARMeilleure.Instructions Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar); Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808) - ? X86GetScalar (context, 0x43E0000000000000L) + ? X86GetScalar(context, 0x43E0000000000000L) : X86GetAllElements(context, 0x43E0000000000000L); nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); @@ -1528,7 +1527,7 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (op is OpCodeSimdShImm fixedOp) { @@ -1538,7 +1537,7 @@ namespace ARMeilleure.Instructions int fpScaled = 0x3F800000 + fBits * 0x800000; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask); @@ -1556,10 +1555,10 @@ namespace ARMeilleure.Instructions Operand zero = context.VectorZero(); Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648) - ? X86GetScalar (context, 0x4F000000) + ? X86GetScalar(context, 0x4F000000) : X86GetAllElements(context, 0x4F000000); Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes); @@ -1567,14 +1566,14 @@ namespace ARMeilleure.Instructions nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask); nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes); nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); - Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes); - dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt); + Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes); + dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt); if (scalar) { @@ -1590,7 +1589,7 @@ namespace ARMeilleure.Instructions else /* if (sizeF == 1) */ { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (op is OpCodeSimdShImm fixedOp) { @@ -1600,7 +1599,7 @@ namespace ARMeilleure.Instructions long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask); @@ -1618,10 +1617,10 @@ namespace ARMeilleure.Instructions Operand zero = context.VectorZero(); Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808) - ? X86GetScalar (context, 0x43E0000000000000L) + ? X86GetScalar(context, 0x43E0000000000000L) : X86GetAllElements(context, 0x43E0000000000000L); Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar); @@ -1629,14 +1628,14 @@ namespace ARMeilleure.Instructions nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask); nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar); nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); - Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes); - dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong); + Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes); + dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong); if (scalar) { @@ -1656,7 +1655,7 @@ namespace ARMeilleure.Instructions if (op.Size == 0) { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (isFixed) { @@ -1678,7 +1677,7 @@ namespace ARMeilleure.Instructions } Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes); int fpMaxVal = op.RegisterSize == RegisterSize.Int32 @@ -1703,7 +1702,7 @@ namespace ARMeilleure.Instructions else /* if (op.Size == 1) */ { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (isFixed) { @@ -1725,7 +1724,7 @@ namespace ARMeilleure.Instructions } Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes); long fpMaxVal = op.RegisterSize == RegisterSize.Int32 @@ -1758,7 +1757,7 @@ namespace ARMeilleure.Instructions if (op.Size == 0) { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (isFixed) { @@ -1782,7 +1781,7 @@ namespace ARMeilleure.Instructions Operand zero = context.VectorZero(); Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); int fpMaxVal = op.RegisterSize == RegisterSize.Int32 ? 0x4F000000 // 2.14748365E9f (2147483648) @@ -1791,16 +1790,16 @@ namespace ARMeilleure.Instructions Operand fpMaxValMask = X86GetScalar(context, fpMaxVal); Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes); nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask); nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes); nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); @@ -1813,14 +1812,14 @@ namespace ARMeilleure.Instructions } Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt); - dRes = context.Add(dRes, nIntOrLong); + dRes = context.Add(dRes, nIntOrLong); SetIntOrZR(context, op.Rd, dRes); } else /* if (op.Size == 1) */ { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (isFixed) { @@ -1844,7 +1843,7 @@ namespace ARMeilleure.Instructions Operand zero = context.VectorZero(); Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); long fpMaxVal = op.RegisterSize == RegisterSize.Int32 ? 0x41E0000000000000L // 2147483648.0000000d (2147483648) @@ -1853,16 +1852,16 @@ namespace ARMeilleure.Instructions Operand fpMaxValMask = X86GetScalar(context, fpMaxVal); Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes); nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask); nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes); nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); @@ -1875,7 +1874,7 @@ namespace ARMeilleure.Instructions } Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong); - dRes = context.Add(dRes, nIntOrLong); + dRes = context.Add(dRes, nIntOrLong); SetIntOrZR(context, op.Rd, dRes); } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs b/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs index bec36e2d..dcdcc65d 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs @@ -5,7 +5,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper32; @@ -217,33 +216,22 @@ namespace ARMeilleure.Instructions string name = nameof(Math.Round); MethodInfo info = (op.Size & 1) == 0 - ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) }) - : typeof(Math). GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) }); + ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) }) + : typeof(Math).GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) }); return context.Call(info, n, Const((int)roundMode)); } private static FPRoundingMode RMToRoundMode(int rm) { - FPRoundingMode roundMode; - switch (rm) + return rm switch { - case 0b00: - roundMode = FPRoundingMode.ToNearestAway; - break; - case 0b01: - roundMode = FPRoundingMode.ToNearest; - break; - case 0b10: - roundMode = FPRoundingMode.TowardsPlusInfinity; - break; - case 0b11: - roundMode = FPRoundingMode.TowardsMinusInfinity; - break; - default: - throw new ArgumentOutOfRangeException(nameof(rm)); - } - return roundMode; + 0b00 => FPRoundingMode.ToNearestAway, + 0b01 => FPRoundingMode.ToNearest, + 0b10 => FPRoundingMode.TowardsPlusInfinity, + 0b11 => FPRoundingMode.TowardsMinusInfinity, + _ => throw new ArgumentOutOfRangeException(nameof(rm)), + }; } // VCVTA/M/N/P (floating-point). @@ -270,22 +258,24 @@ namespace ARMeilleure.Instructions if (unsigned) { - inst = rm switch { + inst = rm switch + { 0b00 => Intrinsic.Arm64FcvtauGp, 0b01 => Intrinsic.Arm64FcvtnuGp, 0b10 => Intrinsic.Arm64FcvtpuGp, 0b11 => Intrinsic.Arm64FcvtmuGp, - _ => throw new ArgumentOutOfRangeException(nameof(rm)) + _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"), }; } else { - inst = rm switch { + inst = rm switch + { 0b00 => Intrinsic.Arm64FcvtasGp, 0b01 => Intrinsic.Arm64FcvtnsGp, 0b10 => Intrinsic.Arm64FcvtpsGp, 0b11 => Intrinsic.Arm64FcvtmsGp, - _ => throw new ArgumentOutOfRangeException(nameof(rm)) + _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"), }; } @@ -297,22 +287,24 @@ namespace ARMeilleure.Instructions { if (unsigned) { - inst = rm switch { + inst = rm switch + { 0b00 => Intrinsic.Arm64FcvtauS, 0b01 => Intrinsic.Arm64FcvtnuS, 0b10 => Intrinsic.Arm64FcvtpuS, 0b11 => Intrinsic.Arm64FcvtmuS, - _ => throw new ArgumentOutOfRangeException(nameof(rm)) + _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"), }; } else { - inst = rm switch { + inst = rm switch + { 0b00 => Intrinsic.Arm64FcvtasS, 0b01 => Intrinsic.Arm64FcvtnsS, 0b10 => Intrinsic.Arm64FcvtpsS, 0b11 => Intrinsic.Arm64FcvtmsS, - _ => throw new ArgumentOutOfRangeException(nameof(rm)) + _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"), }; } @@ -432,12 +424,13 @@ namespace ARMeilleure.Instructions if (Optimizations.UseAdvSimd) { - Intrinsic inst = rm switch { + Intrinsic inst = rm switch + { 0b00 => Intrinsic.Arm64FrintaS, 0b01 => Intrinsic.Arm64FrintnS, 0b10 => Intrinsic.Arm64FrintpS, 0b11 => Intrinsic.Arm64FrintmS, - _ => throw new ArgumentOutOfRangeException(nameof(rm)) + _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"), }; InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, inst); diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHash.cs b/src/ARMeilleure/Instructions/InstEmitSimdHash.cs index 4fb048ee..aee12d7d 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHash.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHash.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Instructions { static partial class InstEmit { -#region "Sha1" + #region "Sha1" public static void Sha1c_V(ArmEmitterContext context) { OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; @@ -89,9 +89,9 @@ namespace ARMeilleure.Instructions context.Copy(GetVec(op.Rd), res); } -#endregion + #endregion -#region "Sha256" + #region "Sha256" public static void Sha256h_V(ArmEmitterContext context) { OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; @@ -142,6 +142,6 @@ namespace ARMeilleure.Instructions context.Copy(GetVec(op.Rd), res); } -#endregion + #endregion } } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs b/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs index 51334608..c2bb951a 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Instructions { static partial class InstEmit32 { -#region "Sha256" + #region "Sha256" public static void Sha256h_V(ArmEmitterContext context) { OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp; @@ -59,6 +59,6 @@ namespace ARMeilleure.Instructions context.Copy(GetVecA32(op.Qd), res); } -#endregion + #endregion } } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs b/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs index 23e4948d..a672b159 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs @@ -18,9 +18,9 @@ namespace ARMeilleure.Instructions Operand round2 = context.AddIntrinsic(Intrinsic.X86Sha256Rnds2, src1, src2, w); Operand round4 = context.AddIntrinsic(Intrinsic.X86Sha256Rnds2, src2, round2, w2); - + Operand res = context.AddIntrinsic(Intrinsic.X86Shufps, round4, round2, Const(part2 ? 0x11 : 0xbb)); - + return res; } @@ -53,4 +53,4 @@ namespace ARMeilleure.Instructions return context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha256SchedulePart2)), x, y, z); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs index c44c9b4d..35052ad1 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs @@ -6,7 +6,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -18,19 +17,19 @@ namespace ARMeilleure.Instructions static class InstEmitSimdHelper { -#region "Masks" + #region "Masks" public static readonly long[] EvenMasks = new long[] { 14L << 56 | 12L << 48 | 10L << 40 | 08L << 32 | 06L << 24 | 04L << 16 | 02L << 8 | 00L << 0, // B 13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0, // H - 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0 // S + 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0, // S }; public static readonly long[] OddMasks = new long[] { 15L << 56 | 13L << 48 | 11L << 40 | 09L << 32 | 07L << 24 | 05L << 16 | 03L << 8 | 01L << 0, // B 15L << 56 | 14L << 48 | 11L << 40 | 10L << 32 | 07L << 24 | 06L << 16 | 03L << 8 | 02L << 0, // H - 15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0 // S + 15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0, // S }; public static readonly long ZeroMask = 128L << 56 | 128L << 48 | 128L << 40 | 128L << 32 | 128L << 24 | 128L << 16 | 128L << 8 | 128L << 0; @@ -38,19 +37,19 @@ namespace ARMeilleure.Instructions public static ulong X86GetGf2p8LogicalShiftLeft(int shift) { ulong identity = (0b00000001UL << 56) | (0b00000010UL << 48) | (0b00000100UL << 40) | (0b00001000UL << 32) | - (0b00010000UL << 24) | (0b00100000UL << 16) | (0b01000000UL << 8) | (0b10000000UL << 0); + (0b00010000UL << 24) | (0b00100000UL << 16) | (0b01000000UL << 8) | (0b10000000UL << 0); return shift >= 0 ? identity >> (shift * 8) : identity << (-shift * 8); } -#endregion + #endregion -#region "X86 SSE Intrinsics" + #region "X86 SSE Intrinsics" public static readonly Intrinsic[] X86PaddInstruction = new Intrinsic[] { Intrinsic.X86Paddb, Intrinsic.X86Paddw, Intrinsic.X86Paddd, - Intrinsic.X86Paddq + Intrinsic.X86Paddq, }; public static readonly Intrinsic[] X86PcmpeqInstruction = new Intrinsic[] @@ -58,7 +57,7 @@ namespace ARMeilleure.Instructions Intrinsic.X86Pcmpeqb, Intrinsic.X86Pcmpeqw, Intrinsic.X86Pcmpeqd, - Intrinsic.X86Pcmpeqq + Intrinsic.X86Pcmpeqq, }; public static readonly Intrinsic[] X86PcmpgtInstruction = new Intrinsic[] @@ -66,49 +65,49 @@ namespace ARMeilleure.Instructions Intrinsic.X86Pcmpgtb, Intrinsic.X86Pcmpgtw, Intrinsic.X86Pcmpgtd, - Intrinsic.X86Pcmpgtq + Intrinsic.X86Pcmpgtq, }; public static readonly Intrinsic[] X86PmaxsInstruction = new Intrinsic[] { Intrinsic.X86Pmaxsb, Intrinsic.X86Pmaxsw, - Intrinsic.X86Pmaxsd + Intrinsic.X86Pmaxsd, }; public static readonly Intrinsic[] X86PmaxuInstruction = new Intrinsic[] { Intrinsic.X86Pmaxub, Intrinsic.X86Pmaxuw, - Intrinsic.X86Pmaxud + Intrinsic.X86Pmaxud, }; public static readonly Intrinsic[] X86PminsInstruction = new Intrinsic[] { Intrinsic.X86Pminsb, Intrinsic.X86Pminsw, - Intrinsic.X86Pminsd + Intrinsic.X86Pminsd, }; public static readonly Intrinsic[] X86PminuInstruction = new Intrinsic[] { Intrinsic.X86Pminub, Intrinsic.X86Pminuw, - Intrinsic.X86Pminud + Intrinsic.X86Pminud, }; public static readonly Intrinsic[] X86PmovsxInstruction = new Intrinsic[] { Intrinsic.X86Pmovsxbw, Intrinsic.X86Pmovsxwd, - Intrinsic.X86Pmovsxdq + Intrinsic.X86Pmovsxdq, }; public static readonly Intrinsic[] X86PmovzxInstruction = new Intrinsic[] { Intrinsic.X86Pmovzxbw, Intrinsic.X86Pmovzxwd, - Intrinsic.X86Pmovzxdq + Intrinsic.X86Pmovzxdq, }; public static readonly Intrinsic[] X86PsllInstruction = new Intrinsic[] @@ -116,14 +115,14 @@ namespace ARMeilleure.Instructions 0, Intrinsic.X86Psllw, Intrinsic.X86Pslld, - Intrinsic.X86Psllq + Intrinsic.X86Psllq, }; public static readonly Intrinsic[] X86PsraInstruction = new Intrinsic[] { 0, Intrinsic.X86Psraw, - Intrinsic.X86Psrad + Intrinsic.X86Psrad, }; public static readonly Intrinsic[] X86PsrlInstruction = new Intrinsic[] @@ -131,7 +130,7 @@ namespace ARMeilleure.Instructions 0, Intrinsic.X86Psrlw, Intrinsic.X86Psrld, - Intrinsic.X86Psrlq + Intrinsic.X86Psrlq, }; public static readonly Intrinsic[] X86PsubInstruction = new Intrinsic[] @@ -139,7 +138,7 @@ namespace ARMeilleure.Instructions Intrinsic.X86Psubb, Intrinsic.X86Psubw, Intrinsic.X86Psubd, - Intrinsic.X86Psubq + Intrinsic.X86Psubq, }; public static readonly Intrinsic[] X86PunpckhInstruction = new Intrinsic[] @@ -147,7 +146,7 @@ namespace ARMeilleure.Instructions Intrinsic.X86Punpckhbw, Intrinsic.X86Punpckhwd, Intrinsic.X86Punpckhdq, - Intrinsic.X86Punpckhqdq + Intrinsic.X86Punpckhqdq, }; public static readonly Intrinsic[] X86PunpcklInstruction = new Intrinsic[] @@ -155,9 +154,9 @@ namespace ARMeilleure.Instructions Intrinsic.X86Punpcklbw, Intrinsic.X86Punpcklwd, Intrinsic.X86Punpckldq, - Intrinsic.X86Punpcklqdq + Intrinsic.X86Punpcklqdq, }; -#endregion + #endregion public static void EnterArmFpMode(EmitterContext context, Func getFpFlag) { @@ -310,15 +309,16 @@ namespace ARMeilleure.Instructions public static int X86GetRoundControl(FPRoundingMode roundMode) { - switch (roundMode) + return roundMode switch { - case FPRoundingMode.ToNearest: return 8 | 0; // even - case FPRoundingMode.TowardsPlusInfinity: return 8 | 2; - case FPRoundingMode.TowardsMinusInfinity: return 8 | 1; - case FPRoundingMode.TowardsZero: return 8 | 3; - } - - throw new ArgumentException($"Invalid rounding mode \"{roundMode}\"."); +#pragma warning disable IDE0055 // Disable formatting + FPRoundingMode.ToNearest => 8 | 0, // even + FPRoundingMode.TowardsPlusInfinity => 8 | 2, + FPRoundingMode.TowardsMinusInfinity => 8 | 1, + FPRoundingMode.TowardsZero => 8 | 3, + _ => throw new ArgumentException($"Invalid rounding mode \"{roundMode}\"."), +#pragma warning restore IDE0055 + }; } public static Operand EmitSse41RoundToNearestWithTiesToAwayOpF(ArmEmitterContext context, Operand n, bool scalar) @@ -334,11 +334,11 @@ namespace ARMeilleure.Instructions if ((op.Size & 1) == 0) { Operand signMask = scalar ? X86GetScalar(context, int.MinValue) : X86GetAllElements(context, int.MinValue); - signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy); + signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy); // 0x3EFFFFFF == BitConverter.SingleToInt32Bits(0.5f) - 1 Operand valueMask = scalar ? X86GetScalar(context, 0x3EFFFFFF) : X86GetAllElements(context, 0x3EFFFFFF); - valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask); + valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask); nCopy = context.AddIntrinsic(scalar ? Intrinsic.X86Addss : Intrinsic.X86Addps, nCopy, valueMask); @@ -347,11 +347,11 @@ namespace ARMeilleure.Instructions else { Operand signMask = scalar ? X86GetScalar(context, long.MinValue) : X86GetAllElements(context, long.MinValue); - signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy); + signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy); // 0x3FDFFFFFFFFFFFFFL == BitConverter.DoubleToInt64Bits(0.5d) - 1L Operand valueMask = scalar ? X86GetScalar(context, 0x3FDFFFFFFFFFFFFFL) : X86GetAllElements(context, 0x3FDFFFFFFFFFFFFFL); - valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask); + valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask); nCopy = context.AddIntrinsic(scalar ? Intrinsic.X86Addsd : Intrinsic.X86Addpd, nCopy, valueMask); @@ -461,7 +461,7 @@ namespace ARMeilleure.Instructions MethodInfo info = (op.Size & 1) == 0 ? typeof(MathF).GetMethod(name, new Type[] { typeof(float) }) - : typeof(Math). GetMethod(name, new Type[] { typeof(double) }); + : typeof(Math).GetMethod(name, new Type[] { typeof(double) }); return context.Call(info, n); } @@ -473,8 +473,8 @@ namespace ARMeilleure.Instructions string name = nameof(Math.Round); MethodInfo info = (op.Size & 1) == 0 - ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) }) - : typeof(Math). GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) }); + ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) }) + : typeof(Math).GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) }); return context.Call(info, n, Const((int)roundMode)); } @@ -482,7 +482,7 @@ namespace ARMeilleure.Instructions public static Operand EmitGetRoundingMode(ArmEmitterContext context) { Operand rMode = context.ShiftLeft(GetFpFlag(FPState.RMode1Flag), Const(1)); - rMode = context.BitwiseOr(rMode, GetFpFlag(FPState.RMode0Flag)); + rMode = context.BitwiseOr(rMode, GetFpFlag(FPState.RMode0Flag)); return rMode; } @@ -1015,8 +1015,8 @@ namespace ARMeilleure.Instructions for (int index = 0; index < elems; index++) { - Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed); - Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed); + Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed); + Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed); res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1); } @@ -1077,9 +1077,9 @@ namespace ARMeilleure.Instructions for (int index = 0; index < elems; index++) { - Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed); - Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed); - Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed); + Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed); + Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed); + Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed); res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1); } @@ -1143,8 +1143,8 @@ namespace ARMeilleure.Instructions for (int index = 0; index < elems; index++) { - Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed); - Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed); + Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed); + Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed); res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1); } @@ -1174,13 +1174,13 @@ namespace ARMeilleure.Instructions { int pairIndex = index << 1; - Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed); + Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed); Operand n1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed); - Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed); + Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed); Operand m1 = EmitVectorExtract(context, op.Rm, pairIndex + 1, op.Size, signed); - res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size); + res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size); res = EmitVectorInsert(context, res, emit(m0, m1), pairs + index, op.Size); } @@ -1197,11 +1197,11 @@ namespace ARMeilleure.Instructions if (op.RegisterSize == RegisterSize.Simd64) { Operand zeroEvenMask = X86GetElements(context, ZeroMask, EvenMasks[op.Size]); - Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks [op.Size]); + Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks[op.Size]); Operand mN = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); // m:n - Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n + Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n Operand right = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroOddMask); // 0:odd from m:n context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right)); @@ -1213,14 +1213,14 @@ namespace ARMeilleure.Instructions Operand oddEvenN = context.AddIntrinsic(Intrinsic.X86Pshufb, n, oddEvenMask); // odd:even from n Operand oddEvenM = context.AddIntrinsic(Intrinsic.X86Pshufb, m, oddEvenMask); // odd:even from m - Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM); + Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM); Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, oddEvenN, oddEvenM); context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right)); } else { - Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); + Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, n, m); context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[3], left, right)); @@ -1381,7 +1381,7 @@ namespace ARMeilleure.Instructions Operand m0 = context.VectorExtract(type, GetVec(op.Rm), pairIndex); Operand m1 = context.VectorExtract(type, GetVec(op.Rm), pairIndex + 1); - res = context.VectorInsert(res, emit(n0, n1), index); + res = context.VectorInsert(res, emit(n0, n1), index); res = context.VectorInsert(res, emit(m0, m1), pairs + index); } @@ -1433,18 +1433,18 @@ namespace ARMeilleure.Instructions public enum CmpCondition { // Legacy Sse. - Equal = 0, // Ordered, non-signaling. - LessThan = 1, // Ordered, signaling. - LessThanOrEqual = 2, // Ordered, signaling. - UnorderedQ = 3, // Non-signaling. - NotLessThan = 5, // Unordered, signaling. + Equal = 0, // Ordered, non-signaling. + LessThan = 1, // Ordered, signaling. + LessThanOrEqual = 2, // Ordered, signaling. + UnorderedQ = 3, // Non-signaling. + NotLessThan = 5, // Unordered, signaling. NotLessThanOrEqual = 6, // Unordered, signaling. - OrderedQ = 7, // Non-signaling. + OrderedQ = 7, // Non-signaling. // Vex. GreaterThanOrEqual = 13, // Ordered, signaling. - GreaterThan = 14, // Ordered, signaling. - OrderedS = 23 // Signaling. + GreaterThan = 14, // Ordered, signaling. + OrderedS = 23, // Signaling. } [Flags] @@ -1459,7 +1459,7 @@ namespace ARMeilleure.Instructions Add = 1 << 3, Sub = 1 << 4, - Accumulate = 1 << 5 + Accumulate = 1 << 5, } public static void EmitScalarSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit) @@ -1579,7 +1579,7 @@ namespace ARMeilleure.Instructions { Operand de; Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, !signed); - Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed); + Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed); if (op.Size <= 2) { @@ -1627,7 +1627,7 @@ namespace ARMeilleure.Instructions [Flags] public enum SaturatingNarrowFlags { - Scalar = 1 << 0, + Scalar = 1 << 0, SignedSrc = 1 << 1, SignedDst = 1 << 2, @@ -1637,14 +1637,14 @@ namespace ARMeilleure.Instructions VectorSxSx = SignedSrc | SignedDst, VectorSxZx = SignedSrc, - VectorZxZx = 0 + VectorZxZx = 0, } public static void EmitSaturatingNarrowOp(ArmEmitterContext context, SaturatingNarrowFlags flags) { OpCodeSimd op = (OpCodeSimd)context.CurrOp; - bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0; + bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0; bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0; bool signedDst = (flags & SaturatingNarrowFlags.SignedDst) != 0; @@ -2034,18 +2034,30 @@ namespace ARMeilleure.Instructions { switch (size) { - case 0: res = context.SignExtend8 (OperandType.I64, res); break; - case 1: res = context.SignExtend16(OperandType.I64, res); break; - case 2: res = context.SignExtend32(OperandType.I64, res); break; + case 0: + res = context.SignExtend8(OperandType.I64, res); + break; + case 1: + res = context.SignExtend16(OperandType.I64, res); + break; + case 2: + res = context.SignExtend32(OperandType.I64, res); + break; } } else { switch (size) { - case 0: res = context.ZeroExtend8 (OperandType.I64, res); break; - case 1: res = context.ZeroExtend16(OperandType.I64, res); break; - case 2: res = context.ZeroExtend32(OperandType.I64, res); break; + case 0: + res = context.ZeroExtend8(OperandType.I64, res); + break; + case 1: + res = context.ZeroExtend16(OperandType.I64, res); + break; + case 2: + res = context.ZeroExtend32(OperandType.I64, res); + break; } } @@ -2063,10 +2075,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: vector = context.VectorInsert8 (vector, value, index); break; - case 1: vector = context.VectorInsert16(vector, value, index); break; - case 2: vector = context.VectorInsert (vector, value, index); break; - case 3: vector = context.VectorInsert (vector, value, index); break; + case 0: + vector = context.VectorInsert8(vector, value, index); + break; + case 1: + vector = context.VectorInsert16(vector, value, index); + break; + case 2: + vector = context.VectorInsert(vector, value, index); + break; + case 3: + vector = context.VectorInsert(vector, value, index); + break; } return vector; diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs index 36d27d42..c1c59b87 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs @@ -4,7 +4,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -19,18 +18,13 @@ namespace ARMeilleure.Instructions { public static (int, int) GetQuadwordAndSubindex(int index, RegisterSize size) { - switch (size) + return size switch { - case RegisterSize.Simd128: - return (index >> 1, 0); - case RegisterSize.Simd64: - case RegisterSize.Int64: - return (index >> 1, index & 1); - case RegisterSize.Int32: - return (index >> 2, index & 3); - } - - throw new ArgumentException("Unrecognized Vector Register Size."); + RegisterSize.Simd128 => (index >> 1, 0), + RegisterSize.Simd64 or RegisterSize.Int64 => (index >> 1, index & 1), + RegisterSize.Int32 => (index >> 2, index & 3), + _ => throw new ArgumentException("Unrecognized Vector Register Size."), + }; } public static Operand ExtractScalar(ArmEmitterContext context, OperandType type, int reg) @@ -327,7 +321,7 @@ namespace ARMeilleure.Instructions for (int index = 0; index < elems; index++) { Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size + 1, signed); - Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed); + Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed); if (op.Size == 2) { @@ -380,8 +374,8 @@ namespace ARMeilleure.Instructions for (int index = 0; index < elems; index++) { Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size + 1, signed); - Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed); - Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed); + Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed); + Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed); if (op.Size == 2) { @@ -778,7 +772,10 @@ namespace ARMeilleure.Instructions { // Index into 0, 0 into index. This swap happens at the start of an A32 scalar op if required. int index = reg & (doubleWidth ? 1 : 3); - if (index == 0) return target; + if (index == 0) + { + return target; + } if (doubleWidth) { @@ -974,7 +971,7 @@ namespace ARMeilleure.Instructions Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32; - EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m)); + EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m)); } public static void EmitScalarTernaryOpSimd32(ArmEmitterContext context, Func3I scalarFunc) @@ -1195,7 +1192,7 @@ namespace ARMeilleure.Instructions : typeof(SoftFloat64).GetMethod(name); Array.Resize(ref callArgs, callArgs.Length + 1); - callArgs[callArgs.Length - 1] = Const(1); + callArgs[^1] = Const(1); context.ExitArmFpMode(); context.StoreToContext(); @@ -1245,16 +1242,24 @@ namespace ARMeilleure.Instructions { switch (size) { - case 0: res = context.SignExtend8(OperandType.I32, res); break; - case 1: res = context.SignExtend16(OperandType.I32, res); break; + case 0: + res = context.SignExtend8(OperandType.I32, res); + break; + case 1: + res = context.SignExtend16(OperandType.I32, res); + break; } } else { switch (size) { - case 0: res = context.ZeroExtend8(OperandType.I32, res); break; - case 1: res = context.ZeroExtend16(OperandType.I32, res); break; + case 0: + res = context.ZeroExtend8(OperandType.I32, res); + break; + case 1: + res = context.ZeroExtend16(OperandType.I32, res); + break; } } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs index 804d915c..568c0712 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs @@ -1,11 +1,9 @@ - using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; using System; using System.Diagnostics; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -74,7 +72,10 @@ namespace ARMeilleure.Instructions public static Operand EmitExtractScalar(ArmEmitterContext context, Operand target, int reg, bool doubleWidth) { int index = reg & (doubleWidth ? 1 : 3); - if (index == 0) return target; // Element is already at index 0, so just return the vector directly. + if (index == 0) + { + return target; // Element is already at index 0, so just return the vector directly. + } if (doubleWidth) { @@ -249,7 +250,7 @@ namespace ARMeilleure.Instructions OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp; inst |= ((op.Size & 1) != 0 ? Intrinsic.Arm64VDouble : Intrinsic.Arm64VFloat) | Intrinsic.Arm64V128; - EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m)); + EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m)); } public static void EmitScalarTernaryOpSimd32(ArmEmitterContext context, Func3I scalarFunc) @@ -336,16 +337,17 @@ namespace ARMeilleure.Instructions CmpCondition.GreaterThanOrEqual => Intrinsic.Arm64FcmgeVz, CmpCondition.LessThan => Intrinsic.Arm64FcmltVz, CmpCondition.LessThanOrEqual => Intrinsic.Arm64FcmleVz, - _ => throw new InvalidOperationException() + _ => throw new InvalidOperationException(), }; } - else { + else + { inst = cond switch { CmpCondition.Equal => Intrinsic.Arm64FcmeqV, CmpCondition.GreaterThan => Intrinsic.Arm64FcmgtV, CmpCondition.GreaterThanOrEqual => Intrinsic.Arm64FcmgeV, - _ => throw new InvalidOperationException() + _ => throw new InvalidOperationException(), }; } @@ -367,4 +369,4 @@ namespace ARMeilleure.Instructions } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs index f0d242ae..70dfc0fb 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs @@ -50,7 +50,7 @@ namespace ARMeilleure.Instructions } SetIntOrZR(context, op.Rd, op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (inst, n) + ? context.AddIntrinsicInt(inst, n) : context.AddIntrinsicLong(inst, n)); } @@ -288,7 +288,7 @@ namespace ARMeilleure.Instructions } SetIntOrZR(context, op.Rd, op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (inst, n, Const(fBits)) + ? context.AddIntrinsicInt(inst, n, Const(fBits)) : context.AddIntrinsicLong(inst, n, Const(fBits))); } @@ -695,7 +695,7 @@ namespace ARMeilleure.Instructions { OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - bool cmpWithZero = !(op is OpCodeSimdFcond) ? op.Bit3 : false; + bool cmpWithZero = op is not OpCodeSimdFcond && op.Bit3; Intrinsic inst = signalNaNs ? Intrinsic.Arm64FcmpeS : Intrinsic.Arm64FcmpS; @@ -717,4 +717,4 @@ namespace ARMeilleure.Instructions SetFlag(context, PState.NFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const(31)), one)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs b/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs index 2bf531e6..97e3da67 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; using System.Diagnostics; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -80,10 +79,11 @@ namespace ARMeilleure.Instructions int eSize = 8 << op.Size; Operand d = GetVec(op.Rd); - Operand imm = eSize switch { + Operand imm = eSize switch + { 16 => X86GetAllElements(context, (short)~op.Immediate), 32 => X86GetAllElements(context, (int)~op.Immediate), - _ => throw new InvalidOperationException($"Invalid element size {eSize}.") + _ => throw new InvalidOperationException($"Invalid element size {eSize}."), }; Operand res = context.AddIntrinsic(Intrinsic.X86Pand, d, imm); @@ -380,10 +380,11 @@ namespace ARMeilleure.Instructions int eSize = 8 << op.Size; Operand d = GetVec(op.Rd); - Operand imm = eSize switch { + Operand imm = eSize switch + { 16 => X86GetAllElements(context, (short)op.Immediate), 32 => X86GetAllElements(context, (int)op.Immediate), - _ => throw new InvalidOperationException($"Invalid element size {eSize}.") + _ => throw new InvalidOperationException($"Invalid element size {eSize}."), }; Operand res = context.AddIntrinsic(Intrinsic.X86Por, d, imm); @@ -414,8 +415,8 @@ namespace ARMeilleure.Instructions (0b00010000L << 32) | (0b00001000L << 24) | (0b00000100L << 16) | - (0b00000010L << 8) | - (0b00000001L << 0); + (0b00000010L << 8) | + (0b00000001L << 0); Operand vBitMatrix = X86GetAllElements(context, bitMatrix); @@ -451,13 +452,13 @@ namespace ARMeilleure.Instructions Debug.Assert(op.Type == OperandType.I64); Operand val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xaaul)), Const(1)), - context.ShiftLeft (context.BitwiseAnd(op, Const(0x55ul)), Const(1))); + context.ShiftLeft(context.BitwiseAnd(op, Const(0x55ul)), Const(1))); val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xccul)), Const(2)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x33ul)), Const(2))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x33ul)), Const(2))); return context.BitwiseOr(context.ShiftRightUI(val, Const(4)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x0ful)), Const(4))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x0ful)), Const(4))); } public static void Rev16_V(ArmEmitterContext context) diff --git a/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs b/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs index 68ef4ed1..747acb10 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs @@ -52,9 +52,15 @@ namespace ARMeilleure.Instructions // Replicate fields to fill the 64-bits, if size is < 64-bits. switch (op.Size) { - case 0: immediate *= 0x0101010101010101L; break; - case 1: immediate *= 0x0001000100010001L; break; - case 2: immediate *= 0x0000000100000001L; break; + case 0: + immediate *= 0x0101010101010101L; + break; + case 1: + immediate *= 0x0001000100010001L; + break; + case 2: + immediate *= 0x0000000100000001L; + break; } Operand imm = Const(immediate); @@ -199,9 +205,15 @@ namespace ARMeilleure.Instructions // Replicate fields to fill the 64-bits, if size is < 64-bits. switch (op.Size) { - case 0: immediate *= 0x0101010101010101L; break; - case 1: immediate *= 0x0001000100010001L; break; - case 2: immediate *= 0x0000000100000001L; break; + case 0: + immediate *= 0x0101010101010101L; + break; + case 1: + immediate *= 0x0001000100010001L; + break; + case 2: + immediate *= 0x0000000100000001L; + break; } Operand imm = Const(immediate); diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs b/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs index 9b19872a..dedf0fa0 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs @@ -40,6 +40,7 @@ namespace ARMeilleure.Instructions long offset = 0; +#pragma warning disable IDE0055 // Disable formatting for (int rep = 0; rep < op.Reps; rep++) for (int elem = 0; elem < op.Elems; elem++) for (int sElem = 0; sElem < op.SElems; sElem++) @@ -66,6 +67,7 @@ namespace ARMeilleure.Instructions offset += 1 << op.Size; } +#pragma warning restore IDE0055 if (op.WBack) { @@ -157,4 +159,4 @@ namespace ARMeilleure.Instructions context.Copy(n, context.Add(n, m)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMove.cs b/src/ARMeilleure/Instructions/InstEmitSimdMove.cs index b58a32f6..85c98fe3 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdMove.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdMove.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System.Collections.Generic; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -12,19 +11,19 @@ namespace ARMeilleure.Instructions { static partial class InstEmit { -#region "Masks" + #region "Masks" private static readonly long[] _masksE0_Uzp = new long[] { 13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0, - 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0 + 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0, }; private static readonly long[] _masksE1_Uzp = new long[] { 15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0, - 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0 + 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0, }; -#endregion + #endregion public static void Dup_Gp(ArmEmitterContext context) { @@ -36,9 +35,17 @@ namespace ARMeilleure.Instructions { switch (op.Size) { - case 0: n = context.ZeroExtend8 (n.Type, n); n = context.Multiply(n, Const(n.Type, 0x01010101)); break; - case 1: n = context.ZeroExtend16(n.Type, n); n = context.Multiply(n, Const(n.Type, 0x00010001)); break; - case 2: n = context.ZeroExtend32(n.Type, n); break; + case 0: + n = context.ZeroExtend8(n.Type, n); + n = context.Multiply(n, Const(n.Type, 0x01010101)); + break; + case 1: + n = context.ZeroExtend16(n.Type, n); + n = context.Multiply(n, Const(n.Type, 0x00010001)); + break; + case 2: + n = context.ZeroExtend32(n.Type, n); + break; } Operand res = context.VectorInsert(context.VectorZero(), n, 0); @@ -209,7 +216,7 @@ namespace ARMeilleure.Instructions OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp; Operand lblTrue = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand isTrue = InstEmitFlowHelper.GetCondTrue(context, op.Cond); @@ -353,7 +360,7 @@ namespace ARMeilleure.Instructions { OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; - Operand d = GetVec(op.Rd); + Operand d = GetVec(op.Rd); Operand ne = EmitVectorExtractZx(context, op.Rn, op.SrcIndex, op.Size); context.Copy(d, EmitVectorInsert(context, d, ne, op.DstIndex, op.Size)); @@ -497,8 +504,12 @@ namespace ARMeilleure.Instructions switch (op.Size) { - case 0: imm *= 0x01010101; break; - case 1: imm *= 0x00010001; break; + case 0: + imm *= 0x01010101; + break; + case 1: + imm *= 0x00010001; + break; } if (not) @@ -543,7 +554,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, mask); - mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m); + mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m); res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mMask); } @@ -557,7 +568,7 @@ namespace ARMeilleure.Instructions Operand mSubMask = context.AddIntrinsic(Intrinsic.X86Psubb, m, idxMask); Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, mSubMask, mask); - mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, mSubMask); + mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, mSubMask); Operand res2 = context.AddIntrinsic(Intrinsic.X86Pshufb, ni, mMask); @@ -566,7 +577,7 @@ namespace ARMeilleure.Instructions if (!isTbl) { - Operand idxMask = X86GetAllElements(context, (0x1010101010101010L * op.Size) - 0x0101010101010101L); + Operand idxMask = X86GetAllElements(context, (0x1010101010101010L * op.Size) - 0x0101010101010101L); Operand zeroMask = context.VectorZero(); Operand mPosMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, idxMask); @@ -590,7 +601,7 @@ namespace ARMeilleure.Instructions { Operand d = GetVec(op.Rd); - List args = new List(); + List args = new(); if (!isTbl) { @@ -612,20 +623,36 @@ namespace ARMeilleure.Instructions { switch (op.Size) { - case 1: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1)); break; - case 2: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2)); break; - case 3: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3)); break; - case 4: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl4)); break; + case 1: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1)); + break; + case 2: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2)); + break; + case 3: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3)); + break; + case 4: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl4)); + break; } } else { switch (op.Size) { - case 1: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx1)); break; - case 2: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2)); break; - case 3: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3)); break; - case 4: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4)); break; + case 1: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx1)); + break; + case 2: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2)); + break; + case 3: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3)); + break; + case 4: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4)); + break; } } @@ -644,7 +671,7 @@ namespace ARMeilleure.Instructions if (op.Size < 3) { long maskE0 = EvenMasks[op.Size]; - long maskE1 = OddMasks [op.Size]; + long maskE1 = OddMasks[op.Size]; mask = X86GetScalar(context, maskE0); @@ -691,7 +718,7 @@ namespace ARMeilleure.Instructions Operand ne = EmitVectorExtractZx(context, op.Rn, pairIndex + part, op.Size); Operand me = EmitVectorExtractZx(context, op.Rm, pairIndex + part, op.Size); - res = EmitVectorInsert(context, res, ne, pairIndex, op.Size); + res = EmitVectorInsert(context, res, ne, pairIndex, op.Size); res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size); } @@ -712,7 +739,7 @@ namespace ARMeilleure.Instructions if (op.Size < 3) { long maskE0 = EvenMasks[op.Size]; - long maskE1 = OddMasks [op.Size]; + long maskE1 = OddMasks[op.Size]; mask = X86GetScalar(context, maskE0); @@ -784,7 +811,7 @@ namespace ARMeilleure.Instructions Operand ne = EmitVectorExtractZx(context, op.Rn, idx + part, op.Size); Operand me = EmitVectorExtractZx(context, op.Rm, idx + part, op.Size); - res = EmitVectorInsert(context, res, ne, index, op.Size); + res = EmitVectorInsert(context, res, ne, index, op.Size); res = EmitVectorInsert(context, res, me, pairs + index, op.Size); } @@ -839,7 +866,7 @@ namespace ARMeilleure.Instructions Operand ne = EmitVectorExtractZx(context, op.Rn, baseIndex + index, op.Size); Operand me = EmitVectorExtractZx(context, op.Rm, baseIndex + index, op.Size); - res = EmitVectorInsert(context, res, ne, pairIndex, op.Size); + res = EmitVectorInsert(context, res, ne, pairIndex, op.Size); res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size); } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs b/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs index b8b91b31..050d35e9 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs @@ -2,7 +2,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper32; @@ -17,13 +16,13 @@ namespace ARMeilleure.Instructions private static readonly long[] _masksE0_Uzp = new long[] { 13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0, - 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0 + 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0, }; private static readonly long[] _masksE1_Uzp = new long[] { 15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0, - 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0 + 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0, }; #endregion @@ -220,7 +219,7 @@ namespace ARMeilleure.Instructions for (int index = 1; index < length; index++) { int newVn = (op.Vn + index) & 0x1F; - (int qn, int ind) = GetQuadwordAndSubindex(newVn, op.RegisterSize); + (int qn, _) = GetQuadwordAndSubindex(newVn, op.RegisterSize); Operand ni = EmitMoveDoubleWordToSide(context, GetVecA32(qn), newVn, 0); Operand idxMask = X86GetAllElements(context, 0x0808080808080808L * index); diff --git a/src/ARMeilleure/Instructions/InstEmitSimdShift.cs b/src/ARMeilleure/Instructions/InstEmitSimdShift.cs index 19e41119..be067064 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdShift.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdShift.cs @@ -6,7 +6,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -17,12 +16,12 @@ namespace ARMeilleure.Instructions static partial class InstEmit { -#region "Masks" + #region "Masks" private static readonly long[] _masks_SliSri = new long[] // Replication masks. { - 0x0101010101010101L, 0x0001000100010001L, 0x0000000100000001L, 0x0000000000000001L + 0x0101010101010101L, 0x0001000100010001L, 0x0000000100000001L, 0x0000000000000001L, }; -#endregion + #endregion public static void Rshrn_V(ArmEmitterContext context) { @@ -51,9 +50,15 @@ namespace ARMeilleure.Instructions switch (op.Size + 1) { - case 1: mask = X86GetAllElements(context, (int)roundConst * 0x00010001); break; - case 2: mask = X86GetAllElements(context, (int)roundConst); break; - case 3: mask = X86GetAllElements(context, roundConst); break; + case 1: + mask = X86GetAllElements(context, (int)roundConst * 0x00010001); + break; + case 2: + mask = X86GetAllElements(context, (int)roundConst); + break; + case 3: + mask = X86GetAllElements(context, roundConst); + break; } Intrinsic addInst = X86PaddInstruction[op.Size + 1]; @@ -1174,14 +1179,14 @@ namespace ARMeilleure.Instructions Scalar = 1 << 0, Signed = 1 << 1, - Round = 1 << 2, + Round = 1 << 2, Accumulate = 1 << 3, ScalarSx = Scalar | Signed, ScalarZx = Scalar, VectorSx = Signed, - VectorZx = 0 + VectorZx = 0, } private static void EmitScalarShrImmOpSx(ArmEmitterContext context, ShrImmFlags flags) @@ -1210,9 +1215,9 @@ namespace ARMeilleure.Instructions Operand res = context.VectorZero(); - bool scalar = (flags & ShrImmFlags.Scalar) != 0; - bool signed = (flags & ShrImmFlags.Signed) != 0; - bool round = (flags & ShrImmFlags.Round) != 0; + bool scalar = (flags & ShrImmFlags.Scalar) != 0; + bool signed = (flags & ShrImmFlags.Signed) != 0; + bool round = (flags & ShrImmFlags.Round) != 0; bool accumulate = (flags & ShrImmFlags.Accumulate) != 0; int shift = GetImmShr(op); @@ -1288,7 +1293,7 @@ namespace ARMeilleure.Instructions [Flags] private enum ShrImmSaturatingNarrowFlags { - Scalar = 1 << 0, + Scalar = 1 << 0, SignedSrc = 1 << 1, SignedDst = 1 << 2, @@ -1300,7 +1305,7 @@ namespace ARMeilleure.Instructions VectorSxSx = SignedSrc | SignedDst, VectorSxZx = SignedSrc, - VectorZxZx = 0 + VectorZxZx = 0, } private static void EmitRoundShrImmSaturatingNarrowOp(ArmEmitterContext context, ShrImmSaturatingNarrowFlags flags) @@ -1312,10 +1317,10 @@ namespace ARMeilleure.Instructions { OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0; + bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0; bool signedSrc = (flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0; bool signedDst = (flags & ShrImmSaturatingNarrowFlags.SignedDst) != 0; - bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0; + bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0; int shift = GetImmShr(op); @@ -1585,7 +1590,7 @@ namespace ARMeilleure.Instructions Scalar = 1 << 0, Signed = 1 << 1, Round = 1 << 2, - Saturating = 1 << 3 + Saturating = 1 << 3, } private static void EmitShlRegOp(ArmEmitterContext context, ShlRegFlags flags = ShlRegFlags.None) diff --git a/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs b/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs index 9ac68088..5c7d4828 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs @@ -5,7 +5,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper32; @@ -291,7 +290,7 @@ namespace ARMeilleure.Instructions VectorSxSx = SignedSrc | SignedDst, VectorSxZx = SignedSrc, - VectorZxZx = 0 + VectorZxZx = 0, } private static void EmitRoundShrImmSaturatingNarrowOp(ArmEmitterContext context, ShrImmSaturatingNarrowFlags flags) @@ -303,10 +302,10 @@ namespace ARMeilleure.Instructions { OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp; - bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0; + bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0; bool signedSrc = (flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0; bool signedDst = (flags & ShrImmSaturatingNarrowFlags.SignedDst) != 0; - bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0; + bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0; if (scalar) { diff --git a/src/ARMeilleure/Instructions/InstEmitSystem.cs b/src/ARMeilleure/Instructions/InstEmitSystem.cs index f84829aa..8c430fc2 100644 --- a/src/ARMeilleure/Instructions/InstEmitSystem.cs +++ b/src/ARMeilleure/Instructions/InstEmitSystem.cs @@ -28,18 +28,39 @@ namespace ARMeilleure.Instructions switch (GetPackedId(op)) { - case 0b11_011_0000_0000_001: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCtrEl0)); break; - case 0b11_011_0000_0000_111: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetDczidEl0)); break; - case 0b11_011_0100_0010_000: EmitGetNzcv(context); return; - case 0b11_011_0100_0100_000: EmitGetFpcr(context); return; - case 0b11_011_0100_0100_001: EmitGetFpsr(context); return; - case 0b11_011_1101_0000_010: EmitGetTpidrEl0(context); return; - case 0b11_011_1101_0000_011: EmitGetTpidrroEl0(context); return; - case 0b11_011_1110_0000_000: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntfrqEl0)); break; - case 0b11_011_1110_0000_001: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break; - case 0b11_011_1110_0000_010: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntvctEl0)); break; + case 0b11_011_0000_0000_001: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCtrEl0)); + break; + case 0b11_011_0000_0000_111: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetDczidEl0)); + break; + case 0b11_011_0100_0010_000: + EmitGetNzcv(context); + return; + case 0b11_011_0100_0100_000: + EmitGetFpcr(context); + return; + case 0b11_011_0100_0100_001: + EmitGetFpsr(context); + return; + case 0b11_011_1101_0000_010: + EmitGetTpidrEl0(context); + return; + case 0b11_011_1101_0000_011: + EmitGetTpidrroEl0(context); + return; + case 0b11_011_1110_0000_000: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntfrqEl0)); + break; + case 0b11_011_1110_0000_001: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); + break; + case 0b11_011_1110_0000_010: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntvctEl0)); + break; - default: throw new NotImplementedException($"Unknown MRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}."); + default: + throw new NotImplementedException($"Unknown MRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}."); } SetIntOrZR(context, op.Rt, context.Call(info)); @@ -51,12 +72,21 @@ namespace ARMeilleure.Instructions switch (GetPackedId(op)) { - case 0b11_011_0100_0010_000: EmitSetNzcv(context); return; - case 0b11_011_0100_0100_000: EmitSetFpcr(context); return; - case 0b11_011_0100_0100_001: EmitSetFpsr(context); return; - case 0b11_011_1101_0000_010: EmitSetTpidrEl0(context); return; + case 0b11_011_0100_0010_000: + EmitSetNzcv(context); + return; + case 0b11_011_0100_0100_000: + EmitSetFpcr(context); + return; + case 0b11_011_0100_0100_001: + EmitSetFpsr(context); + return; + case 0b11_011_1101_0000_010: + EmitSetTpidrEl0(context); + return; - default: throw new NotImplementedException($"Unknown MSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}."); + default: + throw new NotImplementedException($"Unknown MSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}."); } } @@ -75,20 +105,20 @@ namespace ARMeilleure.Instructions switch (GetPackedId(op)) { case 0b11_011_0111_0100_001: - { - // DC ZVA - Operand t = GetIntOrZR(context, op.Rt); - - for (long offset = 0; offset < DczSizeInBytes; offset += 8) { - Operand address = context.Add(t, Const(offset)); + // DC ZVA + Operand t = GetIntOrZR(context, op.Rt); - InstEmitMemoryHelper.EmitStore(context, address, RegisterConsts.ZeroIndex, 3); + for (long offset = 0; offset < DczSizeInBytes; offset += 8) + { + Operand address = context.Add(t, Const(offset)); + + InstEmitMemoryHelper.EmitStore(context, address, RegisterConsts.ZeroIndex, 3); + } + + break; } - break; - } - // No-op case 0b11_011_0111_1110_001: // DC CIVAC break; @@ -104,7 +134,7 @@ namespace ARMeilleure.Instructions { int id; - id = op.Op2 << 0; + id = op.Op2 << 0; id |= op.CRm << 3; id |= op.CRn << 7; id |= op.Op1 << 11; @@ -188,7 +218,7 @@ namespace ARMeilleure.Instructions OpCodeSystem op = (OpCodeSystem)context.CurrOp; Operand nzcv = GetIntOrZR(context, op.Rt); - nzcv = context.ConvertI64ToI32(nzcv); + nzcv = context.ConvertI64ToI32(nzcv); SetFlag(context, PState.VFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const((int)PState.VFlag)), Const(1))); SetFlag(context, PState.CFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const((int)PState.CFlag)), Const(1))); @@ -201,7 +231,7 @@ namespace ARMeilleure.Instructions OpCodeSystem op = (OpCodeSystem)context.CurrOp; Operand fpcr = GetIntOrZR(context, op.Rt); - fpcr = context.ConvertI64ToI32(fpcr); + fpcr = context.ConvertI64ToI32(fpcr); for (int flag = 0; flag < RegisterConsts.FpFlagsCount; flag++) { @@ -221,7 +251,7 @@ namespace ARMeilleure.Instructions context.ClearQcFlagIfModified(); Operand fpsr = GetIntOrZR(context, op.Rt); - fpsr = context.ConvertI64ToI32(fpsr); + fpsr = context.ConvertI64ToI32(fpsr); for (int flag = 0; flag < RegisterConsts.FpFlagsCount; flag++) { diff --git a/src/ARMeilleure/Instructions/InstEmitSystem32.cs b/src/ARMeilleure/Instructions/InstEmitSystem32.cs index f2732c99..82e62571 100644 --- a/src/ARMeilleure/Instructions/InstEmitSystem32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSystem32.cs @@ -4,7 +4,6 @@ using ARMeilleure.State; using ARMeilleure.Translation; using System; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -34,7 +33,8 @@ namespace ARMeilleure.Instructions switch (op.Opc2) { case 2: - EmitSetTpidrEl0(context); return; + EmitSetTpidrEl0(context); + return; default: throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."); @@ -83,17 +83,13 @@ namespace ARMeilleure.Instructions throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."); } - switch (op.Opc2) + result = op.Opc2 switch { - case 2: - result = EmitGetTpidrEl0(context); break; - - case 3: - result = EmitGetTpidrroEl0(context); break; - - default: - throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."); - } + 2 => EmitGetTpidrEl0(context), + 3 => EmitGetTpidrroEl0(context), + _ => throw new NotImplementedException( + $"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."), + }; break; @@ -126,27 +122,16 @@ namespace ARMeilleure.Instructions } int opc = op.MrrcOp; - - MethodInfo info; - - switch (op.CRm) + MethodInfo info = op.CRm switch { - case 14: // Timer. - switch (opc) - { - case 0: - info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break; - - default: - throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."); - } - - break; - - default: - throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X} at 0x{op.Address:X}."); - } - + // Timer. + 14 => opc switch + { + 0 => typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)), + _ => throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."), + }, + _ => throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X} at 0x{op.Address:X}."), + }; Operand result = context.Call(info); SetIntA32(context, op.Rt, context.ConvertI64ToI32(result)); @@ -235,7 +220,8 @@ namespace ARMeilleure.Instructions case 0b0000: // FPSID throw new NotImplementedException("Supervisor Only"); case 0b0001: // FPSCR - EmitGetFpscr(context); return; + EmitGetFpscr(context); + return; case 0b0101: // MVFR2 throw new NotImplementedException("MVFR2"); case 0b0110: // MVFR1 @@ -258,7 +244,8 @@ namespace ARMeilleure.Instructions case 0b0000: // FPSID throw new NotImplementedException("Supervisor Only"); case 0b0001: // FPSCR - EmitSetFpscr(context); return; + EmitSetFpscr(context); + return; case 0b0101: // MVFR2 throw new NotImplementedException("MVFR2"); case 0b0110: // MVFR1 diff --git a/src/ARMeilleure/Instructions/NativeInterface.cs b/src/ARMeilleure/Instructions/NativeInterface.cs index 2c35387a..d1b2e353 100644 --- a/src/ARMeilleure/Instructions/NativeInterface.cs +++ b/src/ARMeilleure/Instructions/NativeInterface.cs @@ -64,12 +64,12 @@ namespace ARMeilleure.Instructions #region "System registers" public static ulong GetCtrEl0() { - return (ulong)GetContext().CtrEl0; + return GetContext().CtrEl0; } public static ulong GetDczidEl0() { - return (ulong)GetContext().DczidEl0; + return GetContext().DczidEl0; } public static ulong GetCntfrqEl0() @@ -192,4 +192,4 @@ namespace ARMeilleure.Instructions return Context.Memory; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/SoftFallback.cs b/src/ARMeilleure/Instructions/SoftFallback.cs index 06d76a67..c4fe677b 100644 --- a/src/ARMeilleure/Instructions/SoftFallback.cs +++ b/src/ARMeilleure/Instructions/SoftFallback.cs @@ -5,7 +5,7 @@ namespace ARMeilleure.Instructions { static class SoftFallback { -#region "ShrImm64" + #region "ShrImm64" public static long SignedShrImm64(long value, long roundConst, int shift) { if (roundConst == 0L) @@ -89,12 +89,15 @@ namespace ARMeilleure.Instructions } } } -#endregion + #endregion -#region "Saturation" + #region "Saturation" public static int SatF32ToS32(float value) { - if (float.IsNaN(value)) return 0; + if (float.IsNaN(value)) + { + return 0; + } return value >= int.MaxValue ? int.MaxValue : value <= int.MinValue ? int.MinValue : (int)value; @@ -102,7 +105,10 @@ namespace ARMeilleure.Instructions public static long SatF32ToS64(float value) { - if (float.IsNaN(value)) return 0; + if (float.IsNaN(value)) + { + return 0; + } return value >= long.MaxValue ? long.MaxValue : value <= long.MinValue ? long.MinValue : (long)value; @@ -110,7 +116,10 @@ namespace ARMeilleure.Instructions public static uint SatF32ToU32(float value) { - if (float.IsNaN(value)) return 0; + if (float.IsNaN(value)) + { + return 0; + } return value >= uint.MaxValue ? uint.MaxValue : value <= uint.MinValue ? uint.MinValue : (uint)value; @@ -118,7 +127,10 @@ namespace ARMeilleure.Instructions public static ulong SatF32ToU64(float value) { - if (float.IsNaN(value)) return 0; + if (float.IsNaN(value)) + { + return 0; + } return value >= ulong.MaxValue ? ulong.MaxValue : value <= ulong.MinValue ? ulong.MinValue : (ulong)value; @@ -126,7 +138,10 @@ namespace ARMeilleure.Instructions public static int SatF64ToS32(double value) { - if (double.IsNaN(value)) return 0; + if (double.IsNaN(value)) + { + return 0; + } return value >= int.MaxValue ? int.MaxValue : value <= int.MinValue ? int.MinValue : (int)value; @@ -134,7 +149,10 @@ namespace ARMeilleure.Instructions public static long SatF64ToS64(double value) { - if (double.IsNaN(value)) return 0; + if (double.IsNaN(value)) + { + return 0; + } return value >= long.MaxValue ? long.MaxValue : value <= long.MinValue ? long.MinValue : (long)value; @@ -142,7 +160,10 @@ namespace ARMeilleure.Instructions public static uint SatF64ToU32(double value) { - if (double.IsNaN(value)) return 0; + if (double.IsNaN(value)) + { + return 0; + } return value >= uint.MaxValue ? uint.MaxValue : value <= uint.MinValue ? uint.MinValue : (uint)value; @@ -150,14 +171,17 @@ namespace ARMeilleure.Instructions public static ulong SatF64ToU64(double value) { - if (double.IsNaN(value)) return 0; + if (double.IsNaN(value)) + { + return 0; + } return value >= ulong.MaxValue ? ulong.MaxValue : value <= ulong.MinValue ? ulong.MinValue : (ulong)value; } -#endregion + #endregion -#region "Count" + #region "Count" public static ulong CountLeadingSigns(ulong value, int size) // size is 8, 16, 32 or 64 (SIMD&FP or Base Inst.). { value ^= value >> 1; @@ -197,9 +221,9 @@ namespace ARMeilleure.Instructions return (ulong)count; } -#endregion + #endregion -#region "Table" + #region "Table" public static V128 Tbl1(V128 vector, int bytes, V128 tb0) { return TblOrTbx(default, vector, bytes, tb0); @@ -270,21 +294,21 @@ namespace ARMeilleure.Instructions return new V128(res); } -#endregion + #endregion -#region "Crc32" - private const uint Crc32RevPoly = 0xedb88320; + #region "Crc32" + private const uint Crc32RevPoly = 0xedb88320; private const uint Crc32cRevPoly = 0x82f63b78; - public static uint Crc32b(uint crc, byte value) => Crc32 (crc, Crc32RevPoly, value); + public static uint Crc32b(uint crc, byte value) => Crc32(crc, Crc32RevPoly, value); public static uint Crc32h(uint crc, ushort value) => Crc32h(crc, Crc32RevPoly, value); - public static uint Crc32w(uint crc, uint value) => Crc32w(crc, Crc32RevPoly, value); - public static uint Crc32x(uint crc, ulong value) => Crc32x(crc, Crc32RevPoly, value); + public static uint Crc32w(uint crc, uint value) => Crc32w(crc, Crc32RevPoly, value); + public static uint Crc32x(uint crc, ulong value) => Crc32x(crc, Crc32RevPoly, value); - public static uint Crc32cb(uint crc, byte value) => Crc32 (crc, Crc32cRevPoly, value); + public static uint Crc32cb(uint crc, byte value) => Crc32(crc, Crc32cRevPoly, value); public static uint Crc32ch(uint crc, ushort value) => Crc32h(crc, Crc32cRevPoly, value); - public static uint Crc32cw(uint crc, uint value) => Crc32w(crc, Crc32cRevPoly, value); - public static uint Crc32cx(uint crc, ulong value) => Crc32x(crc, Crc32cRevPoly, value); + public static uint Crc32cw(uint crc, uint value) => Crc32w(crc, Crc32cRevPoly, value); + public static uint Crc32cx(uint crc, ulong value) => Crc32x(crc, Crc32cRevPoly, value); private static uint Crc32h(uint crc, uint poly, ushort val) { @@ -331,9 +355,9 @@ namespace ARMeilleure.Instructions return crc; } -#endregion + #endregion -#region "Aes" + #region "Aes" public static V128 Decrypt(V128 value, V128 roundKey) { return CryptoHelper.AesInvSubBytes(CryptoHelper.AesInvShiftRows(value ^ roundKey)); @@ -353,9 +377,9 @@ namespace ARMeilleure.Instructions { return CryptoHelper.AesMixColumns(value); } -#endregion + #endregion -#region "Sha1" + #region "Sha1" public static V128 HashChoose(V128 hash_abcd, uint hash_e, V128 wk) { for (int e = 0; e <= 3; e++) @@ -426,7 +450,7 @@ namespace ARMeilleure.Instructions ulong t2 = w4_7.Extract(0); ulong t1 = w0_3.Extract(1); - V128 result = new V128(t1, t2); + V128 result = new(t1, t2); return result ^ (w0_3 ^ w8_11); } @@ -472,9 +496,9 @@ namespace ARMeilleure.Instructions { return (value << count) | (value >> (32 - count)); } -#endregion + #endregion -#region "Sha256" + #region "Sha256" public static V128 HashLower(V128 hash_abcd, V128 hash_efgh, V128 wk) { return Sha256Hash(hash_abcd, hash_efgh, wk, part1: true); @@ -487,7 +511,7 @@ namespace ARMeilleure.Instructions public static V128 Sha256SchedulePart1(V128 w0_3, V128 w4_7) { - V128 result = new V128(); + V128 result = new(); for (int e = 0; e <= 3; e++) { @@ -505,7 +529,7 @@ namespace ARMeilleure.Instructions public static V128 Sha256SchedulePart2(V128 w0_3, V128 w8_11, V128 w12_15) { - V128 result = new V128(); + V128 result = new(); ulong t1 = w12_15.Extract(1); @@ -602,13 +626,13 @@ namespace ARMeilleure.Instructions ? (uint)(value & 0xFFFFFFFFUL) : (uint)(value >> 32); } -#endregion + #endregion public static V128 PolynomialMult64_128(ulong op1, ulong op2) { V128 result = V128.Zero; - V128 op2_128 = new V128(op2, 0); + V128 op2_128 = new(op2, 0); for (int i = 0; i < 64; i++) { diff --git a/src/ARMeilleure/Instructions/SoftFloat.cs b/src/ARMeilleure/Instructions/SoftFloat.cs index 4af73c6d..e8f44ce3 100644 --- a/src/ARMeilleure/Instructions/SoftFloat.cs +++ b/src/ARMeilleure/Instructions/SoftFloat.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Instructions { static SoftFloat() { - RecipEstimateTable = BuildRecipEstimateTable(); + RecipEstimateTable = BuildRecipEstimateTable(); RecipSqrtEstimateTable = BuildRecipSqrtEstimateTable(); } @@ -63,7 +63,7 @@ namespace ARMeilleure.Instructions while (src * (aux + 1u) * (aux + 1u) < (1u << 28)) { - aux = aux + 1u; + aux++; } uint dst = (aux + 1u) >> 1; @@ -133,8 +133,8 @@ namespace ARMeilleure.Instructions { sign = (~(uint)valueBits & 0x8000u) == 0u; - uint exp16 = ((uint)valueBits & 0x7C00u) >> 10; - uint frac16 = (uint)valueBits & 0x03FFu; + uint exp16 = ((uint)valueBits & 0x7C00u) >> 10; + uint frac16 = (uint)valueBits & 0x03FFu; double real; @@ -180,17 +180,17 @@ namespace ARMeilleure.Instructions const int e = 5; const int f = 10; - bool sign; + bool sign; double mantissa; if (real < 0d) { - sign = true; + sign = true; mantissa = -real; } else { - sign = false; + sign = false; mantissa = real; } @@ -229,22 +229,22 @@ namespace ARMeilleure.Instructions switch (context.Fpcr.GetRoundingMode()) { case FPRoundingMode.ToNearest: - roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); + roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); overflowToInf = true; break; case FPRoundingMode.TowardsPlusInfinity: - roundUp = (error != 0d && !sign); + roundUp = (error != 0d && !sign); overflowToInf = !sign; break; case FPRoundingMode.TowardsMinusInfinity: - roundUp = (error != 0d && sign); + roundUp = (error != 0d && sign); overflowToInf = sign; break; case FPRoundingMode.TowardsZero: - roundUp = false; + roundUp = false; overflowToInf = false; break; @@ -359,17 +359,17 @@ namespace ARMeilleure.Instructions const int e = 8; const int f = 23; - bool sign; + bool sign; double mantissa; if (real < 0d) { - sign = true; + sign = true; mantissa = -real; } else { - sign = false; + sign = false; mantissa = real; } @@ -415,22 +415,22 @@ namespace ARMeilleure.Instructions switch (context.Fpcr.GetRoundingMode()) { case FPRoundingMode.ToNearest: - roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); + roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); overflowToInf = true; break; case FPRoundingMode.TowardsPlusInfinity: - roundUp = (error != 0d && !sign); + roundUp = (error != 0d && !sign); overflowToInf = !sign; break; case FPRoundingMode.TowardsMinusInfinity: - roundUp = (error != 0d && sign); + roundUp = (error != 0d && sign); overflowToInf = sign; break; case FPRoundingMode.TowardsZero: - roundUp = false; + roundUp = false; overflowToInf = false; break; @@ -534,17 +534,17 @@ namespace ARMeilleure.Instructions const int e = 11; const int f = 52; - bool sign; + bool sign; double mantissa; if (real < 0d) { - sign = true; + sign = true; mantissa = -real; } else { - sign = false; + sign = false; mantissa = real; } @@ -590,22 +590,22 @@ namespace ARMeilleure.Instructions switch (context.Fpcr.GetRoundingMode()) { case FPRoundingMode.ToNearest: - roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); + roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); overflowToInf = true; break; case FPRoundingMode.TowardsPlusInfinity: - roundUp = (error != 0d && !sign); + roundUp = (error != 0d && !sign); overflowToInf = !sign; break; case FPRoundingMode.TowardsMinusInfinity: - roundUp = (error != 0d && sign); + roundUp = (error != 0d && sign); overflowToInf = sign; break; case FPRoundingMode.TowardsZero: - roundUp = false; + roundUp = false; overflowToInf = false; break; @@ -728,8 +728,8 @@ namespace ARMeilleure.Instructions sign = (~valueBits & 0x80000000u) == 0u; - uint exp32 = (valueBits & 0x7F800000u) >> 23; - uint frac32 = valueBits & 0x007FFFFFu; + uint exp32 = (valueBits & 0x7F800000u) >> 23; + uint frac32 = valueBits & 0x007FFFFFu; double real; @@ -798,8 +798,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == !sign2) { @@ -840,8 +842,8 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.Fpcr; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out _, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out _, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out _, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out _, context, fpcr); int result; @@ -995,8 +997,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && inf2) || (zero1 && zero2)) { @@ -1232,8 +1236,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1276,11 +1282,13 @@ namespace ARMeilleure.Instructions FPCR fpcr = standardFpscr ? context.StandardFpcrValue : context.Fpcr; valueA = valueA.FPUnpack(out FPType typeA, out bool signA, out uint addend, context, fpcr); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr); - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; float result = FPProcessNaNs3(typeA, type1, type2, addend, op1, op2, out bool done, context, fpcr); @@ -1293,10 +1301,11 @@ namespace ARMeilleure.Instructions if (!done) { - bool infA = typeA == FPType.Infinity; bool zeroA = typeA == FPType.Zero; + bool infA = typeA == FPType.Infinity; + bool zeroA = typeA == FPType.Zero; - bool signP = sign1 ^ sign2; - bool infP = inf1 || inf2; + bool signP = sign1 ^ sign2; + bool infP = inf1 || inf2; bool zeroP = zero1 || zero2; if ((inf1 && zero2) || (zero1 && inf2) || (infA && infP && signA != signP)) @@ -1359,8 +1368,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1435,34 +1446,17 @@ namespace ARMeilleure.Instructions } else if (MathF.Abs(value) < MathF.Pow(2f, -128)) { - bool overflowToInf; - - switch (fpcr.GetRoundingMode()) + var overflowToInf = fpcr.GetRoundingMode() switch { - case FPRoundingMode.ToNearest: - overflowToInf = true; - break; - - case FPRoundingMode.TowardsPlusInfinity: - overflowToInf = !sign; - break; - - case FPRoundingMode.TowardsMinusInfinity: - overflowToInf = sign; - break; - - case FPRoundingMode.TowardsZero: - overflowToInf = false; - break; - - default: - throw new ArgumentException($"Invalid rounding mode \"{fpcr.GetRoundingMode()}\"."); - } - + FPRoundingMode.TowardsPlusInfinity => !sign, + FPRoundingMode.TowardsMinusInfinity => sign, + FPRoundingMode.TowardsZero => false, + _ => throw new ArgumentException($"Invalid rounding mode \"{fpcr.GetRoundingMode()}\"."), + }; result = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign); SoftFloat.FPProcessException(FPException.Overflow, context, fpcr); - SoftFloat.FPProcessException(FPException.Inexact, context, fpcr); + SoftFloat.FPProcessException(FPException.Inexact, context, fpcr); } else if ((fpcr & FPCR.Fz) != 0 && (MathF.Abs(value) >= MathF.Pow(2f, 126))) { @@ -1518,15 +1512,17 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.StandardFpcrValue; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out uint op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out uint op2, context, fpcr); float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; float product; @@ -1559,8 +1555,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1691,8 +1689,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == sign2) { @@ -1733,15 +1733,17 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.StandardFpcrValue; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out uint op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out uint op2, context, fpcr); float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; float product; @@ -1774,8 +1776,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1860,8 +1864,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == sign2) { @@ -1958,7 +1964,7 @@ namespace ARMeilleure.Instructions { if ((valueBits & 0x007FFFFFu) == 0u || (fpcr & FPCR.Fz) != 0) { - type = FPType.Zero; + type = FPType.Zero; value = FPZero(sign); if ((valueBits & 0x007FFFFFu) != 0u) @@ -1979,7 +1985,7 @@ namespace ARMeilleure.Instructions } else { - type = (~valueBits & 0x00400000u) == 0u ? FPType.QNaN : FPType.SNaN; + type = (~valueBits & 0x00400000u) == 0u ? FPType.QNaN : FPType.SNaN; value = FPZero(sign); } } @@ -2153,8 +2159,8 @@ namespace ARMeilleure.Instructions sign = (~valueBits & 0x8000000000000000ul) == 0u; - ulong exp64 = (valueBits & 0x7FF0000000000000ul) >> 52; - ulong frac64 = valueBits & 0x000FFFFFFFFFFFFFul; + ulong exp64 = (valueBits & 0x7FF0000000000000ul) >> 52; + ulong frac64 = valueBits & 0x000FFFFFFFFFFFFFul; double real; @@ -2223,8 +2229,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == !sign2) { @@ -2265,8 +2273,8 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.Fpcr; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out _, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out _, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out _, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out _, context, fpcr); int result; @@ -2420,8 +2428,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && inf2) || (zero1 && zero2)) { @@ -2657,8 +2667,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -2701,11 +2713,13 @@ namespace ARMeilleure.Instructions FPCR fpcr = standardFpscr ? context.StandardFpcrValue : context.Fpcr; valueA = valueA.FPUnpack(out FPType typeA, out bool signA, out ulong addend, context, fpcr); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr); - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; double result = FPProcessNaNs3(typeA, type1, type2, addend, op1, op2, out bool done, context, fpcr); @@ -2718,10 +2732,11 @@ namespace ARMeilleure.Instructions if (!done) { - bool infA = typeA == FPType.Infinity; bool zeroA = typeA == FPType.Zero; + bool infA = typeA == FPType.Infinity; + bool zeroA = typeA == FPType.Zero; - bool signP = sign1 ^ sign2; - bool infP = inf1 || inf2; + bool signP = sign1 ^ sign2; + bool infP = inf1 || inf2; bool zeroP = zero1 || zero2; if ((inf1 && zero2) || (zero1 && inf2) || (infA && infP && signA != signP)) @@ -2784,8 +2799,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -2860,34 +2877,17 @@ namespace ARMeilleure.Instructions } else if (Math.Abs(value) < Math.Pow(2d, -1024)) { - bool overflowToInf; - - switch (fpcr.GetRoundingMode()) + var overflowToInf = fpcr.GetRoundingMode() switch { - case FPRoundingMode.ToNearest: - overflowToInf = true; - break; - - case FPRoundingMode.TowardsPlusInfinity: - overflowToInf = !sign; - break; - - case FPRoundingMode.TowardsMinusInfinity: - overflowToInf = sign; - break; - - case FPRoundingMode.TowardsZero: - overflowToInf = false; - break; - - default: - throw new ArgumentException($"Invalid rounding mode \"{fpcr.GetRoundingMode()}\"."); - } - + FPRoundingMode.TowardsPlusInfinity => !sign, + FPRoundingMode.TowardsMinusInfinity => sign, + FPRoundingMode.TowardsZero => false, + _ => throw new ArgumentException($"Invalid rounding mode \"{fpcr.GetRoundingMode()}\"."), + }; result = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign); SoftFloat.FPProcessException(FPException.Overflow, context, fpcr); - SoftFloat.FPProcessException(FPException.Inexact, context, fpcr); + SoftFloat.FPProcessException(FPException.Inexact, context, fpcr); } else if ((fpcr & FPCR.Fz) != 0 && (Math.Abs(value) >= Math.Pow(2d, 1022))) { @@ -2943,15 +2943,17 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.StandardFpcrValue; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out ulong op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out ulong op2, context, fpcr); double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; double product; @@ -2984,8 +2986,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -3116,8 +3120,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == sign2) { @@ -3158,15 +3164,17 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.StandardFpcrValue; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out ulong op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out ulong op2, context, fpcr); double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; double product; @@ -3199,8 +3207,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -3285,8 +3295,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == sign2) { @@ -3383,7 +3395,7 @@ namespace ARMeilleure.Instructions { if ((valueBits & 0x000FFFFFFFFFFFFFul) == 0ul || (fpcr & FPCR.Fz) != 0) { - type = FPType.Zero; + type = FPType.Zero; value = FPZero(sign); if ((valueBits & 0x000FFFFFFFFFFFFFul) != 0ul) @@ -3404,7 +3416,7 @@ namespace ARMeilleure.Instructions } else { - type = (~valueBits & 0x0008000000000000ul) == 0ul ? FPType.QNaN : FPType.SNaN; + type = (~valueBits & 0x0008000000000000ul) == 0ul ? FPType.QNaN : FPType.SNaN; value = FPZero(sign); } } diff --git a/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs b/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs index 07bd8b67..810461d7 100644 --- a/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs +++ b/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs @@ -10,7 +10,7 @@ namespace ARMeilleure.IntermediateRepresentation private int _succCount; private BasicBlock _succ0; - private BasicBlock _succ1; + private readonly BasicBlock _succ1; private HashSet _domFrontiers; public int Index { get; set; } @@ -27,10 +27,7 @@ namespace ARMeilleure.IntermediateRepresentation { get { - if (_domFrontiers == null) - { - _domFrontiers = new HashSet(); - } + _domFrontiers ??= new HashSet(); return _domFrontiers; } @@ -108,7 +105,7 @@ namespace ARMeilleure.IntermediateRepresentation oldBlock.Predecessors.Remove(this); block.Predecessors.Add(this); - + oldBlock = block; } @@ -156,4 +153,4 @@ namespace ARMeilleure.IntermediateRepresentation return base.GetHashCode(); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs b/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs index 96cfee35..74aaea6b 100644 --- a/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs +++ b/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs @@ -3,6 +3,6 @@ enum BasicBlockFrequency { Default, - Cold + Cold, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Comparison.cs b/src/ARMeilleure/IntermediateRepresentation/Comparison.cs index 628ce105..e3a68b49 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Comparison.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Comparison.cs @@ -2,16 +2,16 @@ { enum Comparison { - Equal = 0, - NotEqual = 1, - Greater = 2, - LessOrEqual = 3, - GreaterUI = 4, - LessOrEqualUI = 5, - GreaterOrEqual = 6, - Less = 7, - GreaterOrEqualUI = 8, - LessUI = 9 + Equal = 0, + NotEqual = 1, + Greater = 2, + LessOrEqual = 3, + GreaterUI = 4, + LessOrEqualUI = 5, + GreaterOrEqual = 6, + Less = 7, + GreaterOrEqualUI = 8, + LessUI = 9, } static class ComparisonExtensions diff --git a/src/ARMeilleure/IntermediateRepresentation/Instruction.cs b/src/ARMeilleure/IntermediateRepresentation/Instruction.cs index b55fe1da..9bae8d1f 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Instruction.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Instruction.cs @@ -67,6 +67,6 @@ namespace ARMeilleure.IntermediateRepresentation Phi, Spill, SpillArg, - StoreToContext + StoreToContext, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs b/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs index df5d39ae..b9cab667 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs @@ -1,8 +1,10 @@ using System; +using System.Diagnostics.CodeAnalysis; namespace ARMeilleure.IntermediateRepresentation { [Flags] + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] enum Intrinsic : ushort { // X86 (SSE and AVX) @@ -634,6 +636,6 @@ namespace ARMeilleure.IntermediateRepresentation Arm64VByte = 0 << Arm64VSizeShift, Arm64VHWord = 1 << Arm64VSizeShift, Arm64VWord = 2 << Arm64VSizeShift, - Arm64VDWord = 3 << Arm64VSizeShift + Arm64VDWord = 3 << Arm64VSizeShift, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs b/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs index 07d2633b..9b3df8ca 100644 --- a/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs +++ b/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs @@ -4,11 +4,11 @@ using System.Runtime.CompilerServices; namespace ARMeilleure.IntermediateRepresentation { - unsafe struct MemoryOperand + readonly unsafe struct MemoryOperand { private struct Data { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public byte Kind; public byte Type; #pragma warning restore CS0649 @@ -18,7 +18,7 @@ namespace ARMeilleure.IntermediateRepresentation public int Displacement; } - private Data* _data; + private readonly Data* _data; public MemoryOperand(Operand operand) { @@ -30,13 +30,13 @@ namespace ARMeilleure.IntermediateRepresentation public Operand BaseAddress { get => _data->BaseAddress; - set => _data->BaseAddress = value; + set => _data->BaseAddress = value; } public Operand Index { get => _data->Index; - set => _data->Index = value; + set => _data->Index = value; } public Multiplier Scale @@ -51,4 +51,4 @@ namespace ARMeilleure.IntermediateRepresentation set => _data->Displacement = value; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs b/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs index d6bc7d99..6bcdda01 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs @@ -6,6 +6,6 @@ namespace ARMeilleure.IntermediateRepresentation x2 = 1, x4 = 2, x8 = 3, - x16 = 4 + x16 = 4, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Operand.cs b/src/ARMeilleure/IntermediateRepresentation/Operand.cs index 9e8de3ba..89aefacb 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Operand.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Operand.cs @@ -27,25 +27,25 @@ namespace ARMeilleure.IntermediateRepresentation private Data* _data; - public OperandKind Kind + public readonly OperandKind Kind { get => (OperandKind)_data->Kind; private set => _data->Kind = (byte)value; } - public OperandType Type + public readonly OperandType Type { get => (OperandType)_data->Type; private set => _data->Type = (byte)value; } - public ulong Value + public readonly ulong Value { get => _data->Value; private set => _data->Value = value; } - public Symbol Symbol + public readonly Symbol Symbol { get { @@ -69,7 +69,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public ReadOnlySpan Assignments + public readonly ReadOnlySpan Assignments { get { @@ -79,7 +79,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public ReadOnlySpan Uses + public readonly ReadOnlySpan Uses { get { @@ -89,13 +89,13 @@ namespace ARMeilleure.IntermediateRepresentation } } - public int UsesCount => (int)_data->UsesCount; - public int AssignmentsCount => _data->AssignmentsCount; + public readonly int UsesCount => (int)_data->UsesCount; + public readonly int AssignmentsCount => _data->AssignmentsCount; - public bool Relocatable => Symbol.Type != SymbolType.None; + public readonly bool Relocatable => Symbol.Type != SymbolType.None; [MethodImpl(MethodImplOptions.AggressiveInlining)] - public Register GetRegister() + public readonly Register GetRegister() { Debug.Assert(Kind == OperandKind.Register); @@ -103,52 +103,52 @@ namespace ARMeilleure.IntermediateRepresentation } [MethodImpl(MethodImplOptions.AggressiveInlining)] - public MemoryOperand GetMemory() + public readonly MemoryOperand GetMemory() { Debug.Assert(Kind == OperandKind.Memory); return new MemoryOperand(this); } - public int GetLocalNumber() + public readonly int GetLocalNumber() { Debug.Assert(Kind == OperandKind.LocalVariable); return (int)Value; } - public byte AsByte() + public readonly byte AsByte() { return (byte)Value; } - public short AsInt16() + public readonly short AsInt16() { return (short)Value; } - public int AsInt32() + public readonly int AsInt32() { return (int)Value; } - public long AsInt64() + public readonly long AsInt64() { return (long)Value; } - public float AsFloat() + public readonly float AsFloat() { return BitConverter.Int32BitsToSingle((int)Value); } - public double AsDouble() + public readonly double AsDouble() { return BitConverter.Int64BitsToDouble((long)Value); } [MethodImpl(MethodImplOptions.AggressiveInlining)] - internal ref ulong GetValueUnsafe() + internal readonly ref ulong GetValueUnsafe() { return ref _data->Value; } @@ -163,7 +163,7 @@ namespace ARMeilleure.IntermediateRepresentation Value = (ulong)number; } - public void AddAssignment(Operation operation) + public readonly void AddAssignment(Operation operation) { if (Kind == OperandKind.LocalVariable) { @@ -187,7 +187,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void RemoveAssignment(Operation operation) + public readonly void RemoveAssignment(Operation operation) { if (Kind == OperandKind.LocalVariable) { @@ -211,7 +211,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void AddUse(Operation operation) + public readonly void AddUse(Operation operation) { if (Kind == OperandKind.LocalVariable) { @@ -235,7 +235,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void RemoveUse(Operation operation) + public readonly void RemoveUse(Operation operation) { if (Kind == OperandKind.LocalVariable) { @@ -259,7 +259,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public Span GetUses(ref Span buffer) + public readonly Span GetUses(ref Span buffer) { ReadOnlySpan uses = Uses; @@ -270,7 +270,7 @@ namespace ARMeilleure.IntermediateRepresentation uses.CopyTo(buffer); - return buffer.Slice(0, uses.Length); + return buffer[..uses.Length]; } private static void New(ref T* data, ref ushort count, ref ushort capacity, ushort initialCapacity) where T : unmanaged @@ -360,7 +360,7 @@ namespace ARMeilleure.IntermediateRepresentation { if (i + 1 < count) { - span.Slice(i + 1).CopyTo(span.Slice(i)); + span[(i + 1)..].CopyTo(span[i..]); } count--; @@ -380,7 +380,7 @@ namespace ARMeilleure.IntermediateRepresentation { if (i + 1 < count) { - span.Slice(i + 1).CopyTo(span.Slice(i)); + span[(i + 1)..].CopyTo(span[i..]); } count--; @@ -390,17 +390,17 @@ namespace ARMeilleure.IntermediateRepresentation } } - public override int GetHashCode() + public readonly override int GetHashCode() { return ((ulong)_data).GetHashCode(); } - public bool Equals(Operand operand) + public readonly bool Equals(Operand operand) { return operand._data == _data; } - public override bool Equals(object obj) + public readonly override bool Equals(object obj) { return obj is Operand operand && Equals(operand); } @@ -453,8 +453,10 @@ namespace ARMeilleure.IntermediateRepresentation // Look in the next InternTableProbeLength slots for a match. for (uint i = 0; i < InternTableProbeLength; i++) { - Operand interned = new(); - interned._data = &InternTable[(hash + i) % InternTableSize]; + Operand interned = new() + { + _data = &InternTable[(hash + i) % InternTableSize], + }; // If slot matches the allocation request then return that slot. if (interned.Kind == kind && interned.Type == type && interned.Value == value && interned.Symbol == symbol) @@ -479,11 +481,13 @@ namespace ARMeilleure.IntermediateRepresentation *data = default; - Operand result = new(); - result._data = data; - result.Value = value; - result.Kind = kind; - result.Type = type; + Operand result = new() + { + _data = data, + Value = value, + Kind = kind, + Type = type, + }; if (kind != OperandKind.Memory) { @@ -591,4 +595,4 @@ namespace ARMeilleure.IntermediateRepresentation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs b/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs index adb83561..2b973f00 100644 --- a/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs +++ b/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs @@ -8,6 +8,6 @@ namespace ARMeilleure.IntermediateRepresentation LocalVariable, Memory, Register, - Undefined + Undefined, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/OperandType.cs b/src/ARMeilleure/IntermediateRepresentation/OperandType.cs index 81b22cf5..67ebdcde 100644 --- a/src/ARMeilleure/IntermediateRepresentation/OperandType.cs +++ b/src/ARMeilleure/IntermediateRepresentation/OperandType.cs @@ -9,7 +9,7 @@ namespace ARMeilleure.IntermediateRepresentation I64, FP32, FP64, - V128 + V128, } static class OperandTypeExtensions @@ -22,44 +22,41 @@ namespace ARMeilleure.IntermediateRepresentation public static RegisterType ToRegisterType(this OperandType type) { - switch (type) + return type switch { - case OperandType.FP32: return RegisterType.Vector; - case OperandType.FP64: return RegisterType.Vector; - case OperandType.I32: return RegisterType.Integer; - case OperandType.I64: return RegisterType.Integer; - case OperandType.V128: return RegisterType.Vector; - } - - throw new InvalidOperationException($"Invalid operand type \"{type}\"."); + OperandType.FP32 => RegisterType.Vector, + OperandType.FP64 => RegisterType.Vector, + OperandType.I32 => RegisterType.Integer, + OperandType.I64 => RegisterType.Integer, + OperandType.V128 => RegisterType.Vector, + _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."), + }; } public static int GetSizeInBytes(this OperandType type) { - switch (type) + return type switch { - case OperandType.FP32: return 4; - case OperandType.FP64: return 8; - case OperandType.I32: return 4; - case OperandType.I64: return 8; - case OperandType.V128: return 16; - } - - throw new InvalidOperationException($"Invalid operand type \"{type}\"."); + OperandType.FP32 => 4, + OperandType.FP64 => 8, + OperandType.I32 => 4, + OperandType.I64 => 8, + OperandType.V128 => 16, + _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."), + }; } public static int GetSizeInBytesLog2(this OperandType type) { - switch (type) + return type switch { - case OperandType.FP32: return 2; - case OperandType.FP64: return 3; - case OperandType.I32: return 2; - case OperandType.I64: return 3; - case OperandType.V128: return 4; - } - - throw new InvalidOperationException($"Invalid operand type \"{type}\"."); + OperandType.FP32 => 2, + OperandType.FP64 => 3, + OperandType.I32 => 2, + OperandType.I64 => 3, + OperandType.V128 => 4, + _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."), + }; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Operation.cs b/src/ARMeilleure/IntermediateRepresentation/Operation.cs index c71e143c..bc3a71b3 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Operation.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Operation.cs @@ -20,60 +20,60 @@ namespace ARMeilleure.IntermediateRepresentation private Data* _data; - public Instruction Instruction + public readonly Instruction Instruction { get => (Instruction)_data->Instruction; private set => _data->Instruction = (ushort)value; } - public Intrinsic Intrinsic + public readonly Intrinsic Intrinsic { get => (Intrinsic)_data->Intrinsic; private set => _data->Intrinsic = (ushort)value; } - public Operation ListPrevious + public readonly Operation ListPrevious { get => _data->ListPrevious; set => _data->ListPrevious = value; } - public Operation ListNext + public readonly Operation ListNext { get => _data->ListNext; set => _data->ListNext = value; } - public Operand Destination + public readonly Operand Destination { get => _data->DestinationsCount != 0 ? GetDestination(0) : default; set => SetDestination(value); } - public int DestinationsCount => _data->DestinationsCount; - public int SourcesCount => _data->SourcesCount; + public readonly int DestinationsCount => _data->DestinationsCount; + public readonly int SourcesCount => _data->SourcesCount; - internal Span DestinationsUnsafe => new(_data->Destinations, _data->DestinationsCount); - internal Span SourcesUnsafe => new(_data->Sources, _data->SourcesCount); + internal readonly Span DestinationsUnsafe => new(_data->Destinations, _data->DestinationsCount); + internal readonly Span SourcesUnsafe => new(_data->Sources, _data->SourcesCount); - public PhiOperation AsPhi() + public readonly PhiOperation AsPhi() { Debug.Assert(Instruction == Instruction.Phi); return new PhiOperation(this); } - public Operand GetDestination(int index) + public readonly Operand GetDestination(int index) { return DestinationsUnsafe[index]; } - public Operand GetSource(int index) + public readonly Operand GetSource(int index) { return SourcesUnsafe[index]; } - public void SetDestination(int index, Operand dest) + public readonly void SetDestination(int index, Operand dest) { ref Operand curDest = ref DestinationsUnsafe[index]; @@ -83,7 +83,7 @@ namespace ARMeilleure.IntermediateRepresentation curDest = dest; } - public void SetSource(int index, Operand src) + public readonly void SetSource(int index, Operand src) { ref Operand curSrc = ref SourcesUnsafe[index]; @@ -93,7 +93,7 @@ namespace ARMeilleure.IntermediateRepresentation curSrc = src; } - private void RemoveOldDestinations() + private readonly void RemoveOldDestinations() { for (int i = 0; i < _data->DestinationsCount; i++) { @@ -101,7 +101,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void SetDestination(Operand dest) + public readonly void SetDestination(Operand dest) { RemoveOldDestinations(); @@ -119,7 +119,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void SetDestinations(Operand[] dests) + public readonly void SetDestinations(Operand[] dests) { RemoveOldDestinations(); @@ -135,7 +135,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - private void RemoveOldSources() + private readonly void RemoveOldSources() { for (int index = 0; index < _data->SourcesCount; index++) { @@ -143,7 +143,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void SetSource(Operand src) + public readonly void SetSource(Operand src) { RemoveOldSources(); @@ -161,7 +161,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void SetSources(Operand[] srcs) + public readonly void SetSources(Operand[] srcs) { RemoveOldSources(); @@ -184,7 +184,7 @@ namespace ARMeilleure.IntermediateRepresentation SetSource(source); } - private void AddAssignment(Operand op) + private readonly void AddAssignment(Operand op) { if (op != default) { @@ -192,7 +192,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - private void RemoveAssignment(Operand op) + private readonly void RemoveAssignment(Operand op) { if (op != default) { @@ -200,7 +200,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - private void AddUse(Operand op) + private readonly void AddUse(Operand op) { if (op != default) { @@ -208,7 +208,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - private void RemoveUse(Operand op) + private readonly void RemoveUse(Operand op) { if (op != default) { @@ -216,17 +216,17 @@ namespace ARMeilleure.IntermediateRepresentation } } - public bool Equals(Operation operation) + public readonly bool Equals(Operation operation) { return operation._data == _data; } - public override bool Equals(object obj) + public readonly override bool Equals(object obj) { return obj is Operation operation && Equals(operation); } - public override int GetHashCode() + public readonly override int GetHashCode() { return HashCode.Combine((IntPtr)_data); } @@ -267,9 +267,11 @@ namespace ARMeilleure.IntermediateRepresentation Data* data = Allocators.Operations.Allocate(); *data = default; - Operation result = new(); - result._data = data; - result.Instruction = inst; + Operation result = new() + { + _data = data, + Instruction = inst, + }; EnsureCapacity(ref result._data->Destinations, ref result._data->DestinationsCount, destCount); EnsureCapacity(ref result._data->Sources, ref result._data->SourcesCount, srcCount); @@ -373,4 +375,4 @@ namespace ARMeilleure.IntermediateRepresentation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Register.cs b/src/ARMeilleure/IntermediateRepresentation/Register.cs index 241e4d13..208f94be 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Register.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Register.cs @@ -11,7 +11,7 @@ namespace ARMeilleure.IntermediateRepresentation public Register(int index, RegisterType type) { Index = index; - Type = type; + Type = type; } public override int GetHashCode() @@ -37,7 +37,7 @@ namespace ARMeilleure.IntermediateRepresentation public bool Equals(Register other) { return other.Index == Index && - other.Type == Type; + other.Type == Type; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs b/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs index 88ac6c12..2b4c9068 100644 --- a/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs +++ b/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.IntermediateRepresentation Integer, Vector, Flag, - FpFlag + FpFlag, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Memory/IJitMemoryBlock.cs b/src/ARMeilleure/Memory/IJitMemoryBlock.cs index 9b11e07f..e94b0a60 100644 --- a/src/ARMeilleure/Memory/IJitMemoryBlock.cs +++ b/src/ARMeilleure/Memory/IJitMemoryBlock.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Memory void MapAsRx(ulong offset, ulong size); void MapAsRwx(ulong offset, ulong size); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Memory/IMemoryManager.cs b/src/ARMeilleure/Memory/IMemoryManager.cs index 5eb1fadd..ec5b81eb 100644 --- a/src/ARMeilleure/Memory/IMemoryManager.cs +++ b/src/ARMeilleure/Memory/IMemoryManager.cs @@ -74,4 +74,4 @@ namespace ARMeilleure.Memory /// Optional ID of the handles that should not be signalled void SignalMemoryTracking(ulong va, ulong size, bool write, bool precise = false, int? exemptId = null); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Memory/MemoryManagerType.cs b/src/ARMeilleure/Memory/MemoryManagerType.cs index ce84ccaf..e897a038 100644 --- a/src/ARMeilleure/Memory/MemoryManagerType.cs +++ b/src/ARMeilleure/Memory/MemoryManagerType.cs @@ -28,7 +28,7 @@ /// Same as the host mapped memory manager type, but without masking the address within the address space. /// Allows invalid access from JIT code to the rest of the program, but is faster. /// - HostMappedUnsafe + HostMappedUnsafe, } static class MemoryManagerTypeExtensions diff --git a/src/ARMeilleure/Native/JitSupportDarwin.cs b/src/ARMeilleure/Native/JitSupportDarwin.cs index 7d6a8634..ed347b9c 100644 --- a/src/ARMeilleure/Native/JitSupportDarwin.cs +++ b/src/ARMeilleure/Native/JitSupportDarwin.cs @@ -5,7 +5,7 @@ using System.Runtime.Versioning; namespace ARMeilleure.Native { [SupportedOSPlatform("macos")] - public static partial class JitSupportDarwin + internal static partial class JitSupportDarwin { [LibraryImport("libarmeilleure-jitsupport", EntryPoint = "armeilleure_jit_memcpy")] public static partial void Copy(IntPtr dst, IntPtr src, ulong n); diff --git a/src/ARMeilleure/Optimizations.cs b/src/ARMeilleure/Optimizations.cs index 13348cec..8fe478e4 100644 --- a/src/ARMeilleure/Optimizations.cs +++ b/src/ARMeilleure/Optimizations.cs @@ -1,5 +1,3 @@ -using System.Runtime.Intrinsics.Arm; - namespace ARMeilleure { using Arm64HardwareCapabilities = ARMeilleure.CodeGen.Arm64.HardwareCapabilities; @@ -9,31 +7,31 @@ namespace ARMeilleure { public static bool FastFP { get; set; } = true; - public static bool AllowLcqInFunctionTable { get; set; } = true; + public static bool AllowLcqInFunctionTable { get; set; } = true; public static bool UseUnmanagedDispatchLoop { get; set; } = true; - public static bool UseAdvSimdIfAvailable { get; set; } = true; - public static bool UseArm64AesIfAvailable { get; set; } = true; + public static bool UseAdvSimdIfAvailable { get; set; } = true; + public static bool UseArm64AesIfAvailable { get; set; } = true; public static bool UseArm64PmullIfAvailable { get; set; } = true; - public static bool UseSseIfAvailable { get; set; } = true; - public static bool UseSse2IfAvailable { get; set; } = true; - public static bool UseSse3IfAvailable { get; set; } = true; - public static bool UseSsse3IfAvailable { get; set; } = true; - public static bool UseSse41IfAvailable { get; set; } = true; - public static bool UseSse42IfAvailable { get; set; } = true; - public static bool UsePopCntIfAvailable { get; set; } = true; - public static bool UseAvxIfAvailable { get; set; } = true; - public static bool UseAvx512FIfAvailable { get; set; } = true; - public static bool UseAvx512VlIfAvailable { get; set; } = true; - public static bool UseAvx512BwIfAvailable { get; set; } = true; - public static bool UseAvx512DqIfAvailable { get; set; } = true; - public static bool UseF16cIfAvailable { get; set; } = true; - public static bool UseFmaIfAvailable { get; set; } = true; - public static bool UseAesniIfAvailable { get; set; } = true; + public static bool UseSseIfAvailable { get; set; } = true; + public static bool UseSse2IfAvailable { get; set; } = true; + public static bool UseSse3IfAvailable { get; set; } = true; + public static bool UseSsse3IfAvailable { get; set; } = true; + public static bool UseSse41IfAvailable { get; set; } = true; + public static bool UseSse42IfAvailable { get; set; } = true; + public static bool UsePopCntIfAvailable { get; set; } = true; + public static bool UseAvxIfAvailable { get; set; } = true; + public static bool UseAvx512FIfAvailable { get; set; } = true; + public static bool UseAvx512VlIfAvailable { get; set; } = true; + public static bool UseAvx512BwIfAvailable { get; set; } = true; + public static bool UseAvx512DqIfAvailable { get; set; } = true; + public static bool UseF16cIfAvailable { get; set; } = true; + public static bool UseFmaIfAvailable { get; set; } = true; + public static bool UseAesniIfAvailable { get; set; } = true; public static bool UsePclmulqdqIfAvailable { get; set; } = true; - public static bool UseShaIfAvailable { get; set; } = true; - public static bool UseGfniIfAvailable { get; set; } = true; + public static bool UseShaIfAvailable { get; set; } = true; + public static bool UseGfniIfAvailable { get; set; } = true; public static bool ForceLegacySse { @@ -41,6 +39,7 @@ namespace ARMeilleure set => X86HardwareCapabilities.ForceLegacySse = value; } +#pragma warning disable IDE0055 // Disable formatting internal static bool UseAdvSimd => UseAdvSimdIfAvailable && Arm64HardwareCapabilities.SupportsAdvSimd; internal static bool UseArm64Aes => UseArm64AesIfAvailable && Arm64HardwareCapabilities.SupportsAes; internal static bool UseArm64Pmull => UseArm64PmullIfAvailable && Arm64HardwareCapabilities.SupportsPmull; @@ -63,6 +62,7 @@ namespace ARMeilleure internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && X86HardwareCapabilities.SupportsPclmulqdq; internal static bool UseSha => UseShaIfAvailable && X86HardwareCapabilities.SupportsSha; internal static bool UseGfni => UseGfniIfAvailable && X86HardwareCapabilities.SupportsGfni; +#pragma warning restore IDE0055 internal static bool UseAvx512Ortho => UseAvx512F && UseAvx512Vl; internal static bool UseAvx512OrthoFloat => UseAvx512Ortho && UseAvx512Dq; diff --git a/src/ARMeilleure/Signal/NativeSignalHandler.cs b/src/ARMeilleure/Signal/NativeSignalHandler.cs index 5da0c772..ed284677 100644 --- a/src/ARMeilleure/Signal/NativeSignalHandler.cs +++ b/src/ARMeilleure/Signal/NativeSignalHandler.cs @@ -74,7 +74,7 @@ namespace ARMeilleure.Signal private static ulong _pageSize; private static ulong _pageMask; - private static IntPtr _handlerConfig; + private static readonly IntPtr _handlerConfig; private static IntPtr _signalHandlerPtr; private static IntPtr _signalHandlerHandle; @@ -96,11 +96,17 @@ namespace ARMeilleure.Signal public static void InitializeSignalHandler(ulong pageSize, Func customSignalHandlerFactory = null) { - if (_initialized) return; + if (_initialized) + { + return; + } lock (_lock) { - if (_initialized) return; + if (_initialized) + { + return; + } _pageSize = pageSize; _pageMask = pageSize - 1; @@ -284,7 +290,7 @@ namespace ARMeilleure.Signal const ulong auxOffset = 464; // uc_mcontext.__reserved const uint esrMagic = 0x45535201; - context.Copy(auxPtr, context.Add(ucontextPtr, Const(auxOffset))); + context.Copy(auxPtr, context.Add(ucontextPtr, Const(auxOffset))); context.MarkLabel(loopLabel); @@ -319,7 +325,7 @@ namespace ARMeilleure.Signal private static UnixExceptionHandler GenerateUnixSignalHandler(IntPtr signalStructPtr) { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); // (int sig, SigInfo* sigInfo, void* ucontext) Operand sigInfoPtr = context.LoadArgument(OperandType.I64, 1); @@ -367,7 +373,7 @@ namespace ARMeilleure.Signal private static VectoredExceptionHandler GenerateWindowsSignalHandler(IntPtr signalStructPtr) { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); // (ExceptionPointers* exceptionInfo) Operand exceptionInfoPtr = context.LoadArgument(OperandType.I64, 0); diff --git a/src/ARMeilleure/Signal/TestMethods.cs b/src/ARMeilleure/Signal/TestMethods.cs index e2ecad24..ec228c85 100644 --- a/src/ARMeilleure/Signal/TestMethods.cs +++ b/src/ARMeilleure/Signal/TestMethods.cs @@ -20,7 +20,7 @@ namespace ARMeilleure.Signal public static DebugPartialUnmap GenerateDebugPartialUnmap() { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); var result = WindowsPartialUnmapHandler.EmitRetryFromAccessViolation(context); @@ -37,7 +37,7 @@ namespace ARMeilleure.Signal public static DebugThreadLocalMapGetOrReserve GenerateDebugThreadLocalMapGetOrReserve(IntPtr structPtr) { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); var result = WindowsPartialUnmapHandler.EmitThreadLocalMapIntGetOrReserve(context, structPtr, context.LoadArgument(OperandType.I32, 0), context.LoadArgument(OperandType.I32, 1)); @@ -54,7 +54,7 @@ namespace ARMeilleure.Signal public static DebugNativeWriteLoop GenerateDebugNativeWriteLoop() { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); // Loop a write to the target address until "running" is false. diff --git a/src/ARMeilleure/Signal/UnixSignalHandlerRegistration.cs b/src/ARMeilleure/Signal/UnixSignalHandlerRegistration.cs index 22009240..79a8f803 100644 --- a/src/ARMeilleure/Signal/UnixSignalHandlerRegistration.cs +++ b/src/ARMeilleure/Signal/UnixSignalHandlerRegistration.cs @@ -47,10 +47,10 @@ namespace ARMeilleure.Signal public static SigAction RegisterExceptionHandler(IntPtr action) { - SigAction sig = new SigAction + SigAction sig = new() { sa_handler = action, - sa_flags = SA_SIGINFO + sa_flags = SA_SIGINFO, }; sigemptyset(ref sig.sa_mask); diff --git a/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs b/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs index 941e36e5..4da1b32d 100644 --- a/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs +++ b/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs @@ -137,6 +137,7 @@ namespace ARMeilleure.Signal return context.Add(structsPtr, context.SignExtend32(OperandType.I64, offset)); } +#pragma warning disable IDE0051 // Remove unused private member private static void EmitThreadLocalMapIntRelease(EmitterContext context, IntPtr threadLocalMapPtr, Operand threadId, Operand index) { Operand offset = context.Multiply(index, Const(sizeof(int))); @@ -145,6 +146,7 @@ namespace ARMeilleure.Signal context.CompareAndSwap(idPtr, threadId, Const(0)); } +#pragma warning restore IDE0051 private static void EmitAtomicAddI32(EmitterContext context, Operand ptr, Operand additive) { diff --git a/src/ARMeilleure/State/Aarch32Mode.cs b/src/ARMeilleure/State/Aarch32Mode.cs index 395e288a..add1cd26 100644 --- a/src/ARMeilleure/State/Aarch32Mode.cs +++ b/src/ARMeilleure/State/Aarch32Mode.cs @@ -2,14 +2,14 @@ namespace ARMeilleure.State { enum Aarch32Mode { - User = 0b10000, - Fiq = 0b10001, - Irq = 0b10010, + User = 0b10000, + Fiq = 0b10001, + Irq = 0b10010, Supervisor = 0b10011, - Monitor = 0b10110, - Abort = 0b10111, + Monitor = 0b10110, + Abort = 0b10111, Hypervisor = 0b11010, - Undefined = 0b11011, - System = 0b11111 + Undefined = 0b11011, + System = 0b11111, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/ExceptionCallback.cs b/src/ARMeilleure/State/ExceptionCallback.cs index 38d6eef7..2a4e9656 100644 --- a/src/ARMeilleure/State/ExceptionCallback.cs +++ b/src/ARMeilleure/State/ExceptionCallback.cs @@ -2,4 +2,4 @@ namespace ARMeilleure.State { public delegate void ExceptionCallbackNoArgs(ExecutionContext context); public delegate void ExceptionCallback(ExecutionContext context, ulong address, int id); -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/ExecutionContext.cs b/src/ARMeilleure/State/ExecutionContext.cs index 859fb3a5..ce10a591 100644 --- a/src/ARMeilleure/State/ExecutionContext.cs +++ b/src/ARMeilleure/State/ExecutionContext.cs @@ -7,7 +7,7 @@ namespace ARMeilleure.State { private const int MinCountForCheck = 4000; - private NativeContext _nativeContext; + private readonly NativeContext _nativeContext; internal IntPtr NativeContextPtr => _nativeContext.BasePtr; @@ -17,8 +17,10 @@ namespace ARMeilleure.State public ulong Pc => _nativeContext.GetPc(); +#pragma warning disable CA1822 // Mark member as static public uint CtrEl0 => 0x8444c004; public uint DczidEl0 => 0x00000004; +#pragma warning restore CA1822 public ulong CntfrqEl0 => _counter.Frequency; public ulong CntpctEl0 => _counter.Counter; @@ -170,4 +172,4 @@ namespace ARMeilleure.State _nativeContext.Dispose(); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/ExecutionMode.cs b/src/ARMeilleure/State/ExecutionMode.cs index f43c5569..e1fb722b 100644 --- a/src/ARMeilleure/State/ExecutionMode.cs +++ b/src/ARMeilleure/State/ExecutionMode.cs @@ -4,6 +4,6 @@ namespace ARMeilleure.State { Aarch32Arm = 0, Aarch32Thumb = 1, - Aarch64 = 2 + Aarch64 = 2, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/FPCR.cs b/src/ARMeilleure/State/FPCR.cs index 6f707de7..427300ad 100644 --- a/src/ARMeilleure/State/FPCR.cs +++ b/src/ARMeilleure/State/FPCR.cs @@ -13,10 +13,10 @@ namespace ARMeilleure.State Ide = 1u << 15, RMode0 = 1u << 22, RMode1 = 1u << 23, - Fz = 1u << 24, - Dn = 1u << 25, + Fz = 1u << 24, + Dn = 1u << 25, Ahp = 1u << 26, - Mask = Ahp | Dn | Fz | RMode1 | RMode0 | Ide | Ixe | Ufe | Ofe | Dze | Ioe // 0x07C09F00u + Mask = Ahp | Dn | Fz | RMode1 | RMode0 | Ide | Ixe | Ufe | Ofe | Dze | Ioe, // 0x07C09F00u } } diff --git a/src/ARMeilleure/State/FPException.cs b/src/ARMeilleure/State/FPException.cs index e24e07af..5b13659a 100644 --- a/src/ARMeilleure/State/FPException.cs +++ b/src/ARMeilleure/State/FPException.cs @@ -2,11 +2,11 @@ namespace ARMeilleure.State { enum FPException { - InvalidOp = 0, + InvalidOp = 0, DivideByZero = 1, - Overflow = 2, - Underflow = 3, - Inexact = 4, - InputDenorm = 7 + Overflow = 2, + Underflow = 3, + Inexact = 4, + InputDenorm = 7, } } diff --git a/src/ARMeilleure/State/FPRoundingMode.cs b/src/ARMeilleure/State/FPRoundingMode.cs index 8d757a15..0913175e 100644 --- a/src/ARMeilleure/State/FPRoundingMode.cs +++ b/src/ARMeilleure/State/FPRoundingMode.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.State { public enum FPRoundingMode { - ToNearest = 0, // With ties to even. - TowardsPlusInfinity = 1, + ToNearest = 0, // With ties to even. + TowardsPlusInfinity = 1, TowardsMinusInfinity = 2, - TowardsZero = 3, - ToNearestAway = 4 // With ties to away. + TowardsZero = 3, + ToNearestAway = 4, // With ties to away. } } diff --git a/src/ARMeilleure/State/FPSCR.cs b/src/ARMeilleure/State/FPSCR.cs index d6d2fc26..65a060eb 100644 --- a/src/ARMeilleure/State/FPSCR.cs +++ b/src/ARMeilleure/State/FPSCR.cs @@ -10,6 +10,6 @@ namespace ARMeilleure.State Z = 1u << 30, N = 1u << 31, - Mask = N | Z | C | V | FPSR.Mask | FPCR.Mask // 0xFFC09F9Fu + Mask = N | Z | C | V | FPSR.Mask | FPCR.Mask, // 0xFFC09F9Fu } } diff --git a/src/ARMeilleure/State/FPSR.cs b/src/ARMeilleure/State/FPSR.cs index 5e66d5ce..915b2fb3 100644 --- a/src/ARMeilleure/State/FPSR.cs +++ b/src/ARMeilleure/State/FPSR.cs @@ -13,6 +13,6 @@ namespace ARMeilleure.State Idc = 1u << 7, Qc = 1u << 27, - Mask = Qc | Idc | Ixc | Ufc | Ofc | Dzc | Ioc // 0x0800009Fu + Mask = Qc | Idc | Ixc | Ufc | Ofc | Dzc | Ioc, // 0x0800009Fu } } diff --git a/src/ARMeilleure/State/FPState.cs b/src/ARMeilleure/State/FPState.cs index fa6ab9d4..027272ee 100644 --- a/src/ARMeilleure/State/FPState.cs +++ b/src/ARMeilleure/State/FPState.cs @@ -26,6 +26,6 @@ RMode1Flag = 23, FzFlag = 24, DnFlag = 25, - AhpFlag = 26 + AhpFlag = 26, } } diff --git a/src/ARMeilleure/State/FPType.cs b/src/ARMeilleure/State/FPType.cs index 84e0db8d..367082ff 100644 --- a/src/ARMeilleure/State/FPType.cs +++ b/src/ARMeilleure/State/FPType.cs @@ -6,6 +6,6 @@ namespace ARMeilleure.State Zero, Infinity, QNaN, - SNaN + SNaN, } } diff --git a/src/ARMeilleure/State/ICounter.cs b/src/ARMeilleure/State/ICounter.cs index 93e721ea..7aa1cce7 100644 --- a/src/ARMeilleure/State/ICounter.cs +++ b/src/ARMeilleure/State/ICounter.cs @@ -15,4 +15,4 @@ namespace ARMeilleure.State /// ulong Counter { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/NativeContext.cs b/src/ARMeilleure/State/NativeContext.cs index 3189bdd8..5403042e 100644 --- a/src/ARMeilleure/State/NativeContext.cs +++ b/src/ARMeilleure/State/NativeContext.cs @@ -23,7 +23,7 @@ namespace ARMeilleure.State public int Running; } - private static NativeCtxStorage _dummyStorage = new NativeCtxStorage(); + private static NativeCtxStorage _dummyStorage = new(); private readonly IJitMemoryBlock _block; @@ -266,4 +266,4 @@ namespace ARMeilleure.State public void Dispose() => _block.Dispose(); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/PState.cs b/src/ARMeilleure/State/PState.cs index 9a80bc57..d4ddc865 100644 --- a/src/ARMeilleure/State/PState.cs +++ b/src/ARMeilleure/State/PState.cs @@ -12,6 +12,6 @@ namespace ARMeilleure.State VFlag = 28, CFlag = 29, ZFlag = 30, - NFlag = 31 + NFlag = 31, } } diff --git a/src/ARMeilleure/State/RegisterAlias.cs b/src/ARMeilleure/State/RegisterAlias.cs index 7ebfa275..a9574089 100644 --- a/src/ARMeilleure/State/RegisterAlias.cs +++ b/src/ARMeilleure/State/RegisterAlias.cs @@ -2,13 +2,13 @@ namespace ARMeilleure.State { static class RegisterAlias { - public const int R8Usr = 8; - public const int R9Usr = 9; + public const int R8Usr = 8; + public const int R9Usr = 9; public const int R10Usr = 10; public const int R11Usr = 11; public const int R12Usr = 12; - public const int SpUsr = 13; - public const int LrUsr = 14; + public const int SpUsr = 13; + public const int LrUsr = 14; public const int SpHyp = 15; @@ -24,13 +24,13 @@ namespace ARMeilleure.State public const int LrUnd = 22; public const int SpUnd = 23; - public const int R8Fiq = 24; - public const int R9Fiq = 25; + public const int R8Fiq = 24; + public const int R9Fiq = 25; public const int R10Fiq = 26; public const int R11Fiq = 27; public const int R12Fiq = 28; - public const int SpFiq = 29; - public const int LrFiq = 30; + public const int SpFiq = 29; + public const int LrFiq = 30; public const int Aarch32Sp = 13; public const int Aarch32Lr = 14; @@ -39,4 +39,4 @@ namespace ARMeilleure.State public const int Lr = 30; public const int Zr = 31; } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/RegisterConsts.cs b/src/ARMeilleure/State/RegisterConsts.cs index d6294080..b43f8d64 100644 --- a/src/ARMeilleure/State/RegisterConsts.cs +++ b/src/ARMeilleure/State/RegisterConsts.cs @@ -2,14 +2,14 @@ namespace ARMeilleure.State { static class RegisterConsts { - public const int IntRegsCount = 32; - public const int VecRegsCount = 32; - public const int FlagsCount = 32; - public const int FpFlagsCount = 32; + public const int IntRegsCount = 32; + public const int VecRegsCount = 32; + public const int FlagsCount = 32; + public const int FpFlagsCount = 32; public const int IntAndVecRegsCount = IntRegsCount + VecRegsCount; - public const int FpFlagsOffset = IntRegsCount + VecRegsCount + FlagsCount; - public const int TotalCount = IntRegsCount + VecRegsCount + FlagsCount + FpFlagsCount; + public const int FpFlagsOffset = IntRegsCount + VecRegsCount + FlagsCount; + public const int TotalCount = IntRegsCount + VecRegsCount + FlagsCount + FpFlagsCount; public const int ZeroIndex = 31; } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/V128.cs b/src/ARMeilleure/State/V128.cs index 441bbfa6..cbcaddfc 100644 --- a/src/ARMeilleure/State/V128.cs +++ b/src/ARMeilleure/State/V128.cs @@ -19,7 +19,7 @@ namespace ARMeilleure.State /// /// Gets a new with all bits set to zero. /// - public static V128 Zero => new V128(0, 0); + public static V128 Zero => new(0, 0); /// /// Initializes a new instance of the struct with the specified value @@ -55,9 +55,9 @@ namespace ARMeilleure.State /// Element 3 public V128(float e0, float e1, float e2, float e3) { - _e0 = (ulong)(uint)BitConverter.SingleToInt32Bits(e0) << 0; + _e0 = (ulong)(uint)BitConverter.SingleToInt32Bits(e0) << 0; _e0 |= (ulong)(uint)BitConverter.SingleToInt32Bits(e1) << 32; - _e1 = (ulong)(uint)BitConverter.SingleToInt32Bits(e2) << 0; + _e1 = (ulong)(uint)BitConverter.SingleToInt32Bits(e2) << 0; _e1 |= (ulong)(uint)BitConverter.SingleToInt32Bits(e3) << 32; } @@ -98,9 +98,9 @@ namespace ARMeilleure.State /// Element 3 public V128(uint e0, uint e1, uint e2, uint e3) { - _e0 = (ulong)e0 << 0; + _e0 = (ulong)e0 << 0; _e0 |= (ulong)e1 << 32; - _e1 = (ulong)e2 << 0; + _e1 = (ulong)e2 << 0; _e1 |= (ulong)e3 << 32; } @@ -137,7 +137,9 @@ namespace ARMeilleure.State public T Extract(int index) where T : unmanaged { if ((uint)index >= GetElementCount()) + { ThrowIndexOutOfRange(); + } // Performs: // return *((*T)this + index); @@ -156,7 +158,9 @@ namespace ARMeilleure.State public void Insert(int index, T value) where T : unmanaged { if ((uint)index >= GetElementCount()) + { ThrowIndexOutOfRange(); + } // Performs: // *((*T)this + index) = value; @@ -167,13 +171,13 @@ namespace ARMeilleure.State /// Returns a new array which represents the . /// /// A new array which represents the - public byte[] ToArray() + public readonly byte[] ToArray() { - byte[] data = new byte[16]; + byte[] data = new byte[16]; Span span = data; BitConverter.TryWriteBytes(span, _e0); - BitConverter.TryWriteBytes(span.Slice(8), _e1); + BitConverter.TryWriteBytes(span[8..], _e1); return data; } @@ -225,7 +229,7 @@ namespace ARMeilleure.State /// /// Target /// Result of not operation - public static V128 operator ~(V128 x) => new V128(~x._e0, ~x._e1); + public static V128 operator ~(V128 x) => new(~x._e0, ~x._e1); /// /// Performs a bitwise and on the specified instances. @@ -233,7 +237,7 @@ namespace ARMeilleure.State /// First instance /// Second instance /// Result of and operation - public static V128 operator &(V128 x, V128 y) => new V128(x._e0 & y._e0, x._e1 & y._e1); + public static V128 operator &(V128 x, V128 y) => new(x._e0 & y._e0, x._e1 & y._e1); /// /// Performs a bitwise or on the specified instances. @@ -241,7 +245,7 @@ namespace ARMeilleure.State /// First instance /// Second instance /// Result of or operation - public static V128 operator |(V128 x, V128 y) => new V128(x._e0 | y._e0, x._e1 | y._e1); + public static V128 operator |(V128 x, V128 y) => new(x._e0 | y._e0, x._e1 | y._e1); /// /// Performs a bitwise exlusive or on the specified instances. @@ -249,7 +253,7 @@ namespace ARMeilleure.State /// First instance /// Second instance /// Result of exclusive or operation - public static V128 operator ^(V128 x, V128 y) => new V128(x._e0 ^ y._e0, x._e1 ^ y._e1); + public static V128 operator ^(V128 x, V128 y) => new(x._e0 ^ y._e0, x._e1 ^ y._e1); /// /// Determines if the specified instances are equal. @@ -272,7 +276,7 @@ namespace ARMeilleure.State /// /// Other instance /// true if equal; otherwise false - public bool Equals(V128 other) + public readonly bool Equals(V128 other) { return other._e0 == _e0 && other._e1 == _e1; } @@ -282,24 +286,24 @@ namespace ARMeilleure.State /// /// Other instance /// true if equal; otherwise false - public override bool Equals(object obj) + public readonly override bool Equals(object obj) { return obj is V128 vector && Equals(vector); } /// - public override int GetHashCode() + public readonly override int GetHashCode() { return HashCode.Combine(_e0, _e1); } /// - public override string ToString() + public readonly override string ToString() { return $"0x{_e1:X16}{_e0:X16}"; } - private uint GetElementCount() where T : unmanaged + private static uint GetElementCount() where T : unmanaged { return (uint)(Unsafe.SizeOf() / Unsafe.SizeOf()); } @@ -309,4 +313,4 @@ namespace ARMeilleure.State throw new ArgumentOutOfRangeException("index"); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Statistics.cs b/src/ARMeilleure/Statistics.cs index fbc64708..2f873bcf 100644 --- a/src/ARMeilleure/Statistics.cs +++ b/src/ARMeilleure/Statistics.cs @@ -1,4 +1,6 @@ +#if M_PROFILE using System; +#endif using System.Collections.Concurrent; using System.Collections.Generic; using System.Diagnostics; @@ -11,12 +13,12 @@ namespace ARMeilleure { private const int ReportMaxFunctions = 100; -#pragma warning disable CS0169 +#if M_PROFILE [ThreadStatic] private static Stopwatch _executionTimer; -#pragma warning restore CS0169 +#endif - private static ConcurrentDictionary _ticksPerFunction; + private static readonly ConcurrentDictionary _ticksPerFunction; static Statistics() { @@ -47,7 +49,7 @@ namespace ARMeilleure long ticks = _executionTimer.ElapsedTicks; - _ticksPerFunction.AddOrUpdate(funcAddr, ticks, (key, oldTicks) => oldTicks + ticks); + TicksPerFunction.AddOrUpdate(funcAddr, ticks, (key, oldTicks) => oldTicks + ticks); #endif } @@ -69,7 +71,7 @@ namespace ARMeilleure { int count = 0; - StringBuilder sb = new StringBuilder(); + StringBuilder sb = new(); sb.AppendLine(" Function address | Time"); sb.AppendLine("--------------------------"); @@ -91,4 +93,4 @@ namespace ARMeilleure return sb.ToString(); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/ArmEmitterContext.cs b/src/ARMeilleure/Translation/ArmEmitterContext.cs index 565d2aad..e2407473 100644 --- a/src/ARMeilleure/Translation/ArmEmitterContext.cs +++ b/src/ARMeilleure/Translation/ArmEmitterContext.cs @@ -55,7 +55,7 @@ namespace ARMeilleure.Translation public Aarch32Mode Mode { get; } private int _ifThenBlockStateIndex = 0; - private Condition[] _ifThenBlockState = { }; + private Condition[] _ifThenBlockState = Array.Empty(); public bool IsInIfThenBlock => _ifThenBlockStateIndex < _ifThenBlockState.Length; public Condition CurrentIfThenBlockCond => _ifThenBlockState[_ifThenBlockStateIndex]; @@ -96,7 +96,7 @@ namespace ARMeilleure.Translation OperandType returnType = GetOperandType(info.ReturnType); - Symbol symbol = new Symbol(SymbolType.DelegateTable, (ulong)index); + Symbol symbol = new(SymbolType.DelegateTable, (ulong)index); Symbols.Add((ulong)funcPtr.ToInt64(), info.Name); @@ -219,6 +219,7 @@ namespace ARMeilleure.Translation { switch (condition) { +#pragma warning disable IDE0055 // Disable formatting case Condition.Eq: return ICompareEqual (n, m); case Condition.Ne: return ICompareNotEqual (n, m); case Condition.GeUn: return ICompareGreaterOrEqualUI(n, m); @@ -229,6 +230,7 @@ namespace ARMeilleure.Translation case Condition.Lt: return ICompareLess (n, m); case Condition.Gt: return ICompareGreater (n, m); case Condition.Le: return ICompareLessOrEqual (n, m); +#pragma warning restore IDE0055 } } else if (cmpName == InstName.Adds && _optOpLastCompare is IOpCodeAluImm op) @@ -253,12 +255,14 @@ namespace ARMeilleure.Translation switch (condition) { +#pragma warning disable IDE0055 // Disable formatting case Condition.Eq: return ICompareEqual (n, m); case Condition.Ne: return ICompareNotEqual (n, m); case Condition.Ge: return ICompareGreaterOrEqual(n, m); case Condition.Lt: return ICompareLess (n, m); case Condition.Gt: return ICompareGreater (n, m); case Condition.Le: return ICompareLessOrEqual (n, m); +#pragma warning restore IDE0055 } } @@ -279,4 +283,4 @@ namespace ARMeilleure.Translation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Cache/CacheEntry.cs b/src/ARMeilleure/Translation/Cache/CacheEntry.cs index dc5503b1..25b06f78 100644 --- a/src/ARMeilleure/Translation/Cache/CacheEntry.cs +++ b/src/ARMeilleure/Translation/Cache/CacheEntry.cs @@ -7,14 +7,14 @@ namespace ARMeilleure.Translation.Cache readonly struct CacheEntry : IComparable { public int Offset { get; } - public int Size { get; } + public int Size { get; } public UnwindInfo UnwindInfo { get; } public CacheEntry(int offset, int size, UnwindInfo unwindInfo) { - Offset = offset; - Size = size; + Offset = offset; + Size = size; UnwindInfo = unwindInfo; } @@ -23,4 +23,4 @@ namespace ARMeilleure.Translation.Cache return Offset.CompareTo(other.Offset); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs b/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs index 4c22de40..dd67e420 100644 --- a/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs +++ b/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs @@ -23,7 +23,7 @@ namespace ARMeilleure.Translation.Cache } } - private readonly List _blocks = new List(); + private readonly List _blocks = new(); public CacheMemoryAllocator(int capacity) { diff --git a/src/ARMeilleure/Translation/Cache/JitCache.cs b/src/ARMeilleure/Translation/Cache/JitCache.cs index 03cba5ad..91a05412 100644 --- a/src/ARMeilleure/Translation/Cache/JitCache.cs +++ b/src/ARMeilleure/Translation/Cache/JitCache.cs @@ -13,8 +13,8 @@ namespace ARMeilleure.Translation.Cache { static partial class JitCache { - private static readonly int PageSize = (int)MemoryBlock.GetPageSize(); - private static readonly int PageMask = PageSize - 1; + private static readonly int _pageSize = (int)MemoryBlock.GetPageSize(); + private static readonly int _pageMask = _pageSize - 1; private const int CodeAlignment = 4; // Bytes. private const int CacheSize = 2047 * 1024 * 1024; @@ -24,7 +24,7 @@ namespace ARMeilleure.Translation.Cache private static CacheMemoryAllocator _cacheAllocator; - private static readonly List _cacheEntries = new List(); + private static readonly List _cacheEntries = new(); private static readonly object _lock = new(); private static bool _initialized; @@ -35,11 +35,17 @@ namespace ARMeilleure.Translation.Cache public static void Initialize(IJitMemoryAllocator allocator) { - if (_initialized) return; + if (_initialized) + { + return; + } lock (_lock) { - if (_initialized) return; + if (_initialized) + { + return; + } _jitRegion = new ReservedRegion(allocator, CacheSize); @@ -52,7 +58,7 @@ namespace ARMeilleure.Translation.Cache if (OperatingSystem.IsWindows()) { - JitUnwindWindows.InstallFunctionTableHandler(_jitRegion.Pointer, CacheSize, _jitRegion.Pointer + Allocate(PageSize)); + JitUnwindWindows.InstallFunctionTableHandler(_jitRegion.Pointer, CacheSize, _jitRegion.Pointer + Allocate(_pageSize)); } _initialized = true; @@ -75,7 +81,7 @@ namespace ARMeilleure.Translation.Cache { unsafe { - fixed (byte *codePtr = code) + fixed (byte* codePtr = code) { JitSupportDarwin.Copy(funcPtr, (IntPtr)codePtr, (ulong)code.Length); } @@ -124,8 +130,8 @@ namespace ARMeilleure.Translation.Cache { int endOffs = offset + size; - int regionStart = offset & ~PageMask; - int regionEnd = (endOffs + PageMask) & ~PageMask; + int regionStart = offset & ~_pageMask; + int regionEnd = (endOffs + _pageMask) & ~_pageMask; _jitRegion.Block.MapAsRwx((ulong)regionStart, (ulong)(regionEnd - regionStart)); } @@ -134,8 +140,8 @@ namespace ARMeilleure.Translation.Cache { int endOffs = offset + size; - int regionStart = offset & ~PageMask; - int regionEnd = (endOffs + PageMask) & ~PageMask; + int regionStart = offset & ~_pageMask; + int regionEnd = (endOffs + _pageMask) & ~_pageMask; _jitRegion.Block.MapAsRx((ulong)regionStart, (ulong)(regionEnd - regionStart)); } @@ -163,7 +169,7 @@ namespace ARMeilleure.Translation.Cache private static void Add(int offset, int size, UnwindInfo unwindInfo) { - CacheEntry entry = new CacheEntry(offset, size, unwindInfo); + CacheEntry entry = new(offset, size, unwindInfo); int index = _cacheEntries.BinarySearch(entry); @@ -212,4 +218,4 @@ namespace ARMeilleure.Translation.Cache return false; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs b/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs index 57f7bf12..3aa2e19f 100644 --- a/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs +++ b/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs @@ -6,7 +6,7 @@ namespace ARMeilleure.Translation.Cache { class JitCacheInvalidation { - private static int[] _invalidationCode = new int[] + private static readonly int[] _invalidationCode = new int[] { unchecked((int)0xd53b0022), // mrs x2, ctr_el0 unchecked((int)0xd3504c44), // ubfx x4, x2, #16, #4 @@ -40,8 +40,8 @@ namespace ARMeilleure.Translation.Cache private delegate void InvalidateCache(ulong start, ulong end); - private InvalidateCache _invalidateCache; - private ReservedRegion _invalidateCacheCodeRegion; + private readonly InvalidateCache _invalidateCache; + private readonly ReservedRegion _invalidateCacheCodeRegion; private readonly bool _needsInvalidation; @@ -76,4 +76,4 @@ namespace ARMeilleure.Translation.Cache } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs b/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs index 77727bf1..91fd19c2 100644 --- a/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs +++ b/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs @@ -29,15 +29,15 @@ namespace ARMeilleure.Translation.Cache private enum UnwindOp { - PushNonvol = 0, - AllocLarge = 1, - AllocSmall = 2, - SetFpreg = 3, - SaveNonvol = 4, + PushNonvol = 0, + AllocLarge = 1, + AllocSmall = 2, + SetFpreg = 3, + SaveNonvol = 4, SaveNonvolFar = 5, - SaveXmm128 = 8, + SaveXmm128 = 8, SaveXmm128Far = 9, - PushMachframe = 10 + PushMachframe = 10, } private unsafe delegate RuntimeFunction* GetRuntimeFunctionCallback(ulong controlPc, IntPtr context); @@ -111,72 +111,73 @@ namespace ARMeilleure.Translation.Cache switch (entry.PseudoOp) { case UnwindPseudoOp.SaveXmm128: - { - int stackOffset = entry.StackOffsetOrAllocSize; - - Debug.Assert(stackOffset % 16 == 0); - - if (stackOffset <= 0xFFFF0) { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128, entry.PrologOffset, entry.RegIndex); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset / 16); - } - else - { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128Far, entry.PrologOffset, entry.RegIndex); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 0); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 16); - } + int stackOffset = entry.StackOffsetOrAllocSize; - break; - } + Debug.Assert(stackOffset % 16 == 0); + + if (stackOffset <= 0xFFFF0) + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128, entry.PrologOffset, entry.RegIndex); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset / 16); + } + else + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128Far, entry.PrologOffset, entry.RegIndex); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 0); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 16); + } + + break; + } case UnwindPseudoOp.AllocStack: - { - int allocSize = entry.StackOffsetOrAllocSize; - - Debug.Assert(allocSize % 8 == 0); - - if (allocSize <= 128) { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocSmall, entry.PrologOffset, (allocSize / 8) - 1); - } - else if (allocSize <= 0x7FFF8) - { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 0); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize / 8); - } - else - { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 1); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 0); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 16); - } + int allocSize = entry.StackOffsetOrAllocSize; - break; - } + Debug.Assert(allocSize % 8 == 0); + + if (allocSize <= 128) + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocSmall, entry.PrologOffset, (allocSize / 8) - 1); + } + else if (allocSize <= 0x7FFF8) + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 0); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize / 8); + } + else + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 1); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 0); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 16); + } + + break; + } case UnwindPseudoOp.PushReg: - { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.PushNonvol, entry.PrologOffset, entry.RegIndex); + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.PushNonvol, entry.PrologOffset, entry.RegIndex); - break; - } + break; + } - default: throw new NotImplementedException($"({nameof(entry.PseudoOp)} = {entry.PseudoOp})"); + default: + throw new NotImplementedException($"({nameof(entry.PseudoOp)} = {entry.PseudoOp})"); } } Debug.Assert(codeIndex <= MaxUnwindCodesArraySize); - _unwindInfo->VersionAndFlags = 1; // Flags: The function has no handler. - _unwindInfo->SizeOfProlog = (byte)unwindInfo.PrologSize; + _unwindInfo->VersionAndFlags = 1; // Flags: The function has no handler. + _unwindInfo->SizeOfProlog = (byte)unwindInfo.PrologSize; _unwindInfo->CountOfUnwindCodes = (byte)codeIndex; - _unwindInfo->FrameRegister = 0; + _unwindInfo->FrameRegister = 0; _runtimeFunction->BeginAddress = (uint)funcEntry.Offset; - _runtimeFunction->EndAddress = (uint)(funcEntry.Offset + funcEntry.Size); - _runtimeFunction->UnwindData = (uint)_sizeOfRuntimeFunction; + _runtimeFunction->EndAddress = (uint)(funcEntry.Offset + funcEntry.Size); + _runtimeFunction->UnwindData = (uint)_sizeOfRuntimeFunction; return _runtimeFunction; } @@ -186,4 +187,4 @@ namespace ARMeilleure.Translation.Cache return (ushort)(prologOffset | ((int)op << 8) | (opInfo << 12)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Compiler.cs b/src/ARMeilleure/Translation/Compiler.cs index d4aa5cd9..293e6349 100644 --- a/src/ARMeilleure/Translation/Compiler.cs +++ b/src/ARMeilleure/Translation/Compiler.cs @@ -11,10 +11,10 @@ namespace ARMeilleure.Translation { public static CompiledFunction Compile( ControlFlowGraph cfg, - OperandType[] argTypes, - OperandType retType, - CompilerOptions options, - Architecture target) + OperandType[] argTypes, + OperandType retType, + CompilerOptions options, + Architecture target) { CompilerContext cctx = new(cfg, argTypes, retType, options); @@ -65,4 +65,4 @@ namespace ARMeilleure.Translation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/CompilerContext.cs b/src/ARMeilleure/Translation/CompilerContext.cs index 510dec58..5b10686b 100644 --- a/src/ARMeilleure/Translation/CompilerContext.cs +++ b/src/ARMeilleure/Translation/CompilerContext.cs @@ -6,21 +6,21 @@ namespace ARMeilleure.Translation { public ControlFlowGraph Cfg { get; } - public OperandType[] FuncArgTypes { get; } - public OperandType FuncReturnType { get; } + public OperandType[] FuncArgTypes { get; } + public OperandType FuncReturnType { get; } public CompilerOptions Options { get; } public CompilerContext( ControlFlowGraph cfg, - OperandType[] funcArgTypes, - OperandType funcReturnType, - CompilerOptions options) + OperandType[] funcArgTypes, + OperandType funcReturnType, + CompilerOptions options) { - Cfg = cfg; - FuncArgTypes = funcArgTypes; + Cfg = cfg; + FuncArgTypes = funcArgTypes; FuncReturnType = funcReturnType; - Options = options; + Options = options; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/CompilerOptions.cs b/src/ARMeilleure/Translation/CompilerOptions.cs index 0a07ed4a..d454de7f 100644 --- a/src/ARMeilleure/Translation/CompilerOptions.cs +++ b/src/ARMeilleure/Translation/CompilerOptions.cs @@ -5,13 +5,13 @@ namespace ARMeilleure.Translation [Flags] enum CompilerOptions { - None = 0, - SsaForm = 1 << 0, - Optimize = 1 << 1, - Lsra = 1 << 2, + None = 0, + SsaForm = 1 << 0, + Optimize = 1 << 1, + Lsra = 1 << 2, Relocatable = 1 << 3, MediumCq = SsaForm | Optimize, - HighCq = SsaForm | Optimize | Lsra + HighCq = SsaForm | Optimize | Lsra, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/ControlFlowGraph.cs b/src/ARMeilleure/Translation/ControlFlowGraph.cs index c935f152..3ead49c9 100644 --- a/src/ARMeilleure/Translation/ControlFlowGraph.cs +++ b/src/ARMeilleure/Translation/ControlFlowGraph.cs @@ -130,7 +130,7 @@ namespace ARMeilleure.Translation public BasicBlock SplitEdge(BasicBlock predecessor, BasicBlock successor) { - BasicBlock splitBlock = new BasicBlock(Blocks.Count); + BasicBlock splitBlock = new(Blocks.Count); for (int i = 0; i < predecessor.SuccessorsCount; i++) { @@ -152,4 +152,4 @@ namespace ARMeilleure.Translation return splitBlock; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/DelegateInfo.cs b/src/ARMeilleure/Translation/DelegateInfo.cs index 36320ac3..27479a00 100644 --- a/src/ARMeilleure/Translation/DelegateInfo.cs +++ b/src/ARMeilleure/Translation/DelegateInfo.cs @@ -5,7 +5,9 @@ namespace ARMeilleure.Translation { class DelegateInfo { +#pragma warning disable IDE0052 // Remove unread private member private readonly Delegate _dlg; // Ensure that this delegate will not be garbage collected. +#pragma warning restore IDE0052 public IntPtr FuncPtr { get; } diff --git a/src/ARMeilleure/Translation/Dominance.cs b/src/ARMeilleure/Translation/Dominance.cs index b9b961d1..e2185bd8 100644 --- a/src/ARMeilleure/Translation/Dominance.cs +++ b/src/ARMeilleure/Translation/Dominance.cs @@ -29,7 +29,7 @@ namespace ARMeilleure.Translation cfg.Entry.ImmediateDominator = cfg.Entry; - Debug.Assert(cfg.Entry == cfg.PostOrderBlocks[cfg.PostOrderBlocks.Length - 1]); + Debug.Assert(cfg.Entry == cfg.PostOrderBlocks[^1]); bool modified; @@ -92,4 +92,4 @@ namespace ARMeilleure.Translation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/EmitterContext.cs b/src/ARMeilleure/Translation/EmitterContext.cs index 8fcb4dee..88bfe133 100644 --- a/src/ARMeilleure/Translation/EmitterContext.cs +++ b/src/ARMeilleure/Translation/EmitterContext.cs @@ -108,9 +108,9 @@ namespace ARMeilleure.Translation protected static OperandType GetOperandType(Type type) { - if (type == typeof(bool) || type == typeof(byte) || - type == typeof(char) || type == typeof(short) || - type == typeof(int) || type == typeof(sbyte) || + if (type == typeof(bool) || type == typeof(byte) || + type == typeof(char) || type == typeof(short) || + type == typeof(int) || type == typeof(sbyte) || type == typeof(ushort) || type == typeof(uint)) { return OperandType.I32; @@ -635,7 +635,7 @@ namespace ARMeilleure.Translation private void NewNextBlock() { - BasicBlock block = new BasicBlock(_irBlocks.Count); + BasicBlock block = new(_irBlocks.Count); _irBlocks.AddLast(block); diff --git a/src/ARMeilleure/Translation/GuestFunction.cs b/src/ARMeilleure/Translation/GuestFunction.cs index ac131a0d..6414d6bd 100644 --- a/src/ARMeilleure/Translation/GuestFunction.cs +++ b/src/ARMeilleure/Translation/GuestFunction.cs @@ -3,4 +3,4 @@ using System; namespace ARMeilleure.Translation { delegate ulong GuestFunction(IntPtr nativeContextPtr); -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/IntervalTree.cs b/src/ARMeilleure/Translation/IntervalTree.cs index 9af01bea..afd89b93 100644 --- a/src/ARMeilleure/Translation/IntervalTree.cs +++ b/src/ARMeilleure/Translation/IntervalTree.cs @@ -6,15 +6,15 @@ namespace ARMeilleure.Translation /// /// An Augmented Interval Tree based off of the "TreeDictionary"'s Red-Black Tree. Allows fast overlap checking of ranges. /// - /// Key - /// Value - class IntervalTree where K : IComparable + /// Key + /// Value + class IntervalTree where TK : IComparable { private const int ArrayGrowthSize = 32; private const bool Black = true; private const bool Red = false; - private IntervalTreeNode _root = null; + private IntervalTreeNode _root = null; private int _count = 0; public int Count => _count; @@ -27,9 +27,9 @@ namespace ARMeilleure.Translation /// Key of the node value to get /// Value with the given /// True if the key is on the dictionary, false otherwise - public bool TryGet(K key, out V value) + public bool TryGet(TK key, out TV value) { - IntervalTreeNode node = GetNode(key); + IntervalTreeNode node = GetNode(key); if (node == null) { @@ -49,7 +49,7 @@ namespace ARMeilleure.Translation /// Overlaps array to place results in /// Index to start writing results into the array. Defaults to 0 /// Number of intervals found - public int Get(K start, K end, ref K[] overlaps, int overlapCount = 0) + public int Get(TK start, TK end, ref TK[] overlaps, int overlapCount = 0) { GetKeys(_root, start, end, ref overlaps, ref overlapCount); @@ -65,11 +65,11 @@ namespace ARMeilleure.Translation /// Optional factory used to create a new value if is already on the tree /// is null /// True if the value was added, false if the start key was already in the dictionary - public bool AddOrUpdate(K start, K end, V value, Func updateFactoryCallback) + public bool AddOrUpdate(TK start, TK end, TV value, Func updateFactoryCallback) { ArgumentNullException.ThrowIfNull(value); - return BSTInsert(start, end, value, updateFactoryCallback, out IntervalTreeNode node); + return BSTInsert(start, end, value, updateFactoryCallback, out _); } /// @@ -80,11 +80,11 @@ namespace ARMeilleure.Translation /// Value to add /// is null /// if is not yet on the tree, or the existing value otherwise - public V GetOrAdd(K start, K end, V value) + public TV GetOrAdd(TK start, TK end, TV value) { ArgumentNullException.ThrowIfNull(value); - BSTInsert(start, end, value, null, out IntervalTreeNode node); + BSTInsert(start, end, value, null, out IntervalTreeNode node); return node.Value; } @@ -93,7 +93,7 @@ namespace ARMeilleure.Translation /// /// Key of the node to remove /// Number of deleted values - public int Remove(K key) + public int Remove(TK key) { int removed = Delete(key); @@ -106,9 +106,9 @@ namespace ARMeilleure.Translation /// Adds all the nodes in the dictionary into . /// /// A list of all values sorted by Key Order - public List AsList() + public List AsList() { - List list = new List(); + List list = new(); AddToList(_root, list); @@ -124,7 +124,7 @@ namespace ARMeilleure.Translation /// /// The node to search for values within /// The list to add values to - private void AddToList(IntervalTreeNode node, List list) + private void AddToList(IntervalTreeNode node, List list) { if (node == null) { @@ -144,11 +144,11 @@ namespace ARMeilleure.Translation /// Key of the node to get /// is null /// Node reference in the tree - private IntervalTreeNode GetNode(K key) + private IntervalTreeNode GetNode(TK key) { ArgumentNullException.ThrowIfNull(key); - IntervalTreeNode node = _root; + IntervalTreeNode node = _root; while (node != null) { int cmp = key.CompareTo(node.Start); @@ -175,7 +175,7 @@ namespace ARMeilleure.Translation /// End of the range /// Overlaps array to place results in /// Overlaps count to update - private void GetKeys(IntervalTreeNode node, K start, K end, ref K[] overlaps, ref int overlapCount) + private void GetKeys(IntervalTreeNode node, TK start, TK end, ref TK[] overlaps, ref int overlapCount) { if (node == null || start.CompareTo(node.Max) >= 0) { @@ -206,10 +206,10 @@ namespace ARMeilleure.Translation /// This should only be called if the max increases - not for rebalancing or removals. /// /// The node to start propagating from - private void PropagateIncrease(IntervalTreeNode node) + private static void PropagateIncrease(IntervalTreeNode node) { - K max = node.Max; - IntervalTreeNode ptr = node; + TK max = node.Max; + IntervalTreeNode ptr = node; while ((ptr = ptr.Parent) != null) { @@ -229,13 +229,13 @@ namespace ARMeilleure.Translation /// This fully recalculates the max value from all children when there is potential for it to decrease. /// /// The node to start propagating from - private void PropagateFull(IntervalTreeNode node) + private static void PropagateFull(IntervalTreeNode node) { - IntervalTreeNode ptr = node; + IntervalTreeNode ptr = node; do { - K max = ptr.End; + TK max = ptr.End; if (ptr.Left != null && ptr.Left.Max.CompareTo(max) > 0) { @@ -263,10 +263,10 @@ namespace ARMeilleure.Translation /// Optional factory used to create a new value if is already on the tree /// Node that was inserted or modified /// True if was not yet on the tree, false otherwise - private bool BSTInsert(K start, K end, V value, Func updateFactoryCallback, out IntervalTreeNode outNode) + private bool BSTInsert(TK start, TK end, TV value, Func updateFactoryCallback, out IntervalTreeNode outNode) { - IntervalTreeNode parent = null; - IntervalTreeNode node = _root; + IntervalTreeNode parent = null; + IntervalTreeNode node = _root; while (node != null) { @@ -311,7 +311,7 @@ namespace ARMeilleure.Translation return false; } } - IntervalTreeNode newNode = new IntervalTreeNode(start, end, value, parent); + IntervalTreeNode newNode = new(start, end, value, parent); if (newNode.Parent == null) { _root = newNode; @@ -337,16 +337,16 @@ namespace ARMeilleure.Translation /// /// Key to search for /// Number of deleted values - private int Delete(K key) + private int Delete(TK key) { - IntervalTreeNode nodeToDelete = GetNode(key); + IntervalTreeNode nodeToDelete = GetNode(key); if (nodeToDelete == null) { return 0; } - IntervalTreeNode replacementNode; + IntervalTreeNode replacementNode; if (LeftOf(nodeToDelete) == null || RightOf(nodeToDelete) == null) { @@ -357,7 +357,7 @@ namespace ARMeilleure.Translation replacementNode = PredecessorOf(nodeToDelete); } - IntervalTreeNode tmp = LeftOf(replacementNode) ?? RightOf(replacementNode); + IntervalTreeNode tmp = LeftOf(replacementNode) ?? RightOf(replacementNode); if (tmp != null) { @@ -400,9 +400,9 @@ namespace ARMeilleure.Translation /// /// Root Node /// Node with the maximum key in the tree of - private static IntervalTreeNode Maximum(IntervalTreeNode node) + private static IntervalTreeNode Maximum(IntervalTreeNode node) { - IntervalTreeNode tmp = node; + IntervalTreeNode tmp = node; while (tmp.Right != null) { tmp = tmp.Right; @@ -416,13 +416,13 @@ namespace ARMeilleure.Translation /// /// Node to find the predecessor of /// Predecessor of - private static IntervalTreeNode PredecessorOf(IntervalTreeNode node) + private static IntervalTreeNode PredecessorOf(IntervalTreeNode node) { if (node.Left != null) { return Maximum(node.Left); } - IntervalTreeNode parent = node.Parent; + IntervalTreeNode parent = node.Parent; while (parent != null && node == parent.Left) { node = parent; @@ -435,15 +435,15 @@ namespace ARMeilleure.Translation #region Private Methods (RBL) - private void RestoreBalanceAfterRemoval(IntervalTreeNode balanceNode) + private void RestoreBalanceAfterRemoval(IntervalTreeNode balanceNode) { - IntervalTreeNode ptr = balanceNode; + IntervalTreeNode ptr = balanceNode; while (ptr != _root && ColorOf(ptr) == Black) { if (ptr == LeftOf(ParentOf(ptr))) { - IntervalTreeNode sibling = RightOf(ParentOf(ptr)); + IntervalTreeNode sibling = RightOf(ParentOf(ptr)); if (ColorOf(sibling) == Red) { @@ -475,7 +475,7 @@ namespace ARMeilleure.Translation } else { - IntervalTreeNode sibling = LeftOf(ParentOf(ptr)); + IntervalTreeNode sibling = LeftOf(ParentOf(ptr)); if (ColorOf(sibling) == Red) { @@ -509,14 +509,14 @@ namespace ARMeilleure.Translation SetColor(ptr, Black); } - private void RestoreBalanceAfterInsertion(IntervalTreeNode balanceNode) + private void RestoreBalanceAfterInsertion(IntervalTreeNode balanceNode) { SetColor(balanceNode, Red); while (balanceNode != null && balanceNode != _root && ColorOf(ParentOf(balanceNode)) == Red) { if (ParentOf(balanceNode) == LeftOf(ParentOf(ParentOf(balanceNode)))) { - IntervalTreeNode sibling = RightOf(ParentOf(ParentOf(balanceNode))); + IntervalTreeNode sibling = RightOf(ParentOf(ParentOf(balanceNode))); if (ColorOf(sibling) == Red) { @@ -539,7 +539,7 @@ namespace ARMeilleure.Translation } else { - IntervalTreeNode sibling = LeftOf(ParentOf(ParentOf(balanceNode))); + IntervalTreeNode sibling = LeftOf(ParentOf(ParentOf(balanceNode))); if (ColorOf(sibling) == Red) { @@ -564,17 +564,17 @@ namespace ARMeilleure.Translation SetColor(_root, Black); } - private void RotateLeft(IntervalTreeNode node) + private void RotateLeft(IntervalTreeNode node) { if (node != null) { - IntervalTreeNode right = RightOf(node); + IntervalTreeNode right = RightOf(node); node.Right = LeftOf(right); if (node.Right != null) { node.Right.Parent = node; } - IntervalTreeNode nodeParent = ParentOf(node); + IntervalTreeNode nodeParent = ParentOf(node); right.Parent = nodeParent; if (nodeParent == null) { @@ -595,17 +595,17 @@ namespace ARMeilleure.Translation } } - private void RotateRight(IntervalTreeNode node) + private void RotateRight(IntervalTreeNode node) { if (node != null) { - IntervalTreeNode left = LeftOf(node); + IntervalTreeNode left = LeftOf(node); node.Left = RightOf(left); if (node.Left != null) { node.Left.Parent = node; } - IntervalTreeNode nodeParent = ParentOf(node); + IntervalTreeNode nodeParent = ParentOf(node); left.Parent = nodeParent; if (nodeParent == null) { @@ -637,7 +637,7 @@ namespace ARMeilleure.Translation /// /// Node /// The boolean color of , or black if null - private static bool ColorOf(IntervalTreeNode node) + private static bool ColorOf(IntervalTreeNode node) { return node == null || node.Color; } @@ -649,7 +649,7 @@ namespace ARMeilleure.Translation /// /// Node to set the color of /// Color (Boolean) - private static void SetColor(IntervalTreeNode node, bool color) + private static void SetColor(IntervalTreeNode node, bool color) { if (node != null) { @@ -662,7 +662,7 @@ namespace ARMeilleure.Translation /// /// Node to retrieve the left child from /// Left child of - private static IntervalTreeNode LeftOf(IntervalTreeNode node) + private static IntervalTreeNode LeftOf(IntervalTreeNode node) { return node?.Left; } @@ -672,7 +672,7 @@ namespace ARMeilleure.Translation /// /// Node to retrieve the right child from /// Right child of - private static IntervalTreeNode RightOf(IntervalTreeNode node) + private static IntervalTreeNode RightOf(IntervalTreeNode node) { return node?.Right; } @@ -682,14 +682,14 @@ namespace ARMeilleure.Translation /// /// Node to retrieve the parent from /// Parent of - private static IntervalTreeNode ParentOf(IntervalTreeNode node) + private static IntervalTreeNode ParentOf(IntervalTreeNode node) { return node?.Parent; } #endregion - public bool ContainsKey(K key) + public bool ContainsKey(TK key) { return GetNode(key) != null; } @@ -704,36 +704,36 @@ namespace ARMeilleure.Translation /// /// Represents a node in the IntervalTree which contains start and end keys of type K, and a value of generic type V. /// - /// Key type of the node - /// Value type of the node - class IntervalTreeNode + /// Key type of the node + /// Value type of the node + class IntervalTreeNode { public bool Color = true; - public IntervalTreeNode Left = null; - public IntervalTreeNode Right = null; - public IntervalTreeNode Parent = null; + public IntervalTreeNode Left = null; + public IntervalTreeNode Right = null; + public IntervalTreeNode Parent = null; /// /// The start of the range. /// - public K Start; + public TK Start; /// /// The end of the range. /// - public K End; + public TK End; /// /// The maximum end value of this node and all its children. /// - public K Max; + public TK Max; /// /// Value stored on this node. /// - public V Value; + public TV Value; - public IntervalTreeNode(K start, K end, V value, IntervalTreeNode parent) + public IntervalTreeNode(TK start, TK end, TV value, IntervalTreeNode parent) { Start = start; End = end; diff --git a/src/ARMeilleure/Translation/PTC/EncodingCache.cs b/src/ARMeilleure/Translation/PTC/EncodingCache.cs index 90d40c47..d9b38ace 100644 --- a/src/ARMeilleure/Translation/PTC/EncodingCache.cs +++ b/src/ARMeilleure/Translation/PTC/EncodingCache.cs @@ -6,4 +6,4 @@ namespace ARMeilleure.Translation.PTC { public static readonly Encoding UTF8NoBOM = new UTF8Encoding(encoderShouldEmitUTF8Identifier: false, throwOnInvalidBytes: true); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs b/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs index 1b11ac0b..efff45a9 100644 --- a/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs +++ b/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs @@ -7,4 +7,4 @@ namespace ARMeilleure.Translation.PTC event Action PtcStateChanged; void Continue(); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/PTC/Ptc.cs b/src/ARMeilleure/Translation/PTC/Ptc.cs index 3c697bff..665f568d 100644 --- a/src/ARMeilleure/Translation/PTC/Ptc.cs +++ b/src/ARMeilleure/Translation/PTC/Ptc.cs @@ -17,13 +17,12 @@ using System.Runtime; using System.Runtime.CompilerServices; using System.Runtime.InteropServices; using System.Threading; - using static ARMeilleure.Translation.PTC.PtcFormatter; namespace ARMeilleure.Translation.PTC { - using Arm64HardwareCapabilities = ARMeilleure.CodeGen.Arm64.HardwareCapabilities; - using X86HardwareCapabilities = ARMeilleure.CodeGen.X86.HardwareCapabilities; + using Arm64HardwareCapabilities = CodeGen.Arm64.HardwareCapabilities; + using X86HardwareCapabilities = CodeGen.X86.HardwareCapabilities; class Ptc : IPtcLoadState { @@ -187,8 +186,8 @@ namespace ARMeilleure.Translation.PTC string fileNameActual = $"{CachePathActual}.cache"; string fileNameBackup = $"{CachePathBackup}.cache"; - FileInfo fileInfoActual = new FileInfo(fileNameActual); - FileInfo fileInfoBackup = new FileInfo(fileNameBackup); + FileInfo fileInfoActual = new(fileNameActual); + FileInfo fileInfoBackup = new(fileNameBackup); if (fileInfoActual.Exists && fileInfoActual.Length != 0L) { @@ -275,104 +274,102 @@ namespace ARMeilleure.Translation.PTC { intPtr = Marshal.AllocHGlobal(new IntPtr(outerHeader.UncompressedStreamSize)); - using (UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite)) + using UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite); + try { - try - { - deflateStream.CopyTo(stream); - } - catch - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - Debug.Assert(stream.Position == stream.Length); - - stream.Seek(0L, SeekOrigin.Begin); - - InnerHeader innerHeader = DeserializeStructure(stream); - - if (!innerHeader.IsHeaderValid()) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - if (innerHeader.Magic != _innerHeaderMagic) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength); - stream.Seek(innerHeader.InfosLength, SeekOrigin.Current); - - Hash128 infosHash = XXHash128.ComputeHash(infosBytes); - - if (innerHeader.InfosHash != infosHash) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty; - stream.Seek(innerHeader.CodesLength, SeekOrigin.Current); - - Hash128 codesHash = XXHash128.ComputeHash(codesBytes); - - if (innerHeader.CodesHash != codesHash) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength); - stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current); - - Hash128 relocsHash = XXHash128.ComputeHash(relocsBytes); - - if (innerHeader.RelocsHash != relocsHash) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength); - stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current); - - Hash128 unwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes); - - if (innerHeader.UnwindInfosHash != unwindInfosHash) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - Debug.Assert(stream.Position == stream.Length); - - stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin); - - _infosStream.Write(infosBytes); - stream.Seek(innerHeader.InfosLength, SeekOrigin.Current); - - _codesList.ReadFrom(stream); - - _relocsStream.Write(relocsBytes); - stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current); - - _unwindInfosStream.Write(unwindInfosBytes); - stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current); - - Debug.Assert(stream.Position == stream.Length); + deflateStream.CopyTo(stream); } + catch + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + Debug.Assert(stream.Position == stream.Length); + + stream.Seek(0L, SeekOrigin.Begin); + + InnerHeader innerHeader = DeserializeStructure(stream); + + if (!innerHeader.IsHeaderValid()) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + if (innerHeader.Magic != _innerHeaderMagic) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength); + stream.Seek(innerHeader.InfosLength, SeekOrigin.Current); + + Hash128 infosHash = XXHash128.ComputeHash(infosBytes); + + if (innerHeader.InfosHash != infosHash) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty; + stream.Seek(innerHeader.CodesLength, SeekOrigin.Current); + + Hash128 codesHash = XXHash128.ComputeHash(codesBytes); + + if (innerHeader.CodesHash != codesHash) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength); + stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current); + + Hash128 relocsHash = XXHash128.ComputeHash(relocsBytes); + + if (innerHeader.RelocsHash != relocsHash) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength); + stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current); + + Hash128 unwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes); + + if (innerHeader.UnwindInfosHash != unwindInfosHash) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + Debug.Assert(stream.Position == stream.Length); + + stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin); + + _infosStream.Write(infosBytes); + stream.Seek(innerHeader.InfosLength, SeekOrigin.Current); + + _codesList.ReadFrom(stream); + + _relocsStream.Write(relocsBytes); + stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current); + + _unwindInfosStream.Write(unwindInfosBytes); + stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current); + + Debug.Assert(stream.Position == stream.Length); } finally { @@ -390,7 +387,7 @@ namespace ARMeilleure.Translation.PTC return true; } - private void InvalidateCompressedStream(FileStream compressedStream) + private static void InvalidateCompressedStream(FileStream compressedStream) { compressedStream.SetLength(0L); } @@ -404,7 +401,7 @@ namespace ARMeilleure.Translation.PTC string fileNameActual = $"{CachePathActual}.cache"; string fileNameBackup = $"{CachePathBackup}.cache"; - FileInfo fileInfoActual = new FileInfo(fileNameActual); + FileInfo fileInfoActual = new(fileNameActual); if (fileInfoActual.Exists && fileInfoActual.Length != 0L) { @@ -427,32 +424,34 @@ namespace ARMeilleure.Translation.PTC { int translatedFuncsCount; - InnerHeader innerHeader = new InnerHeader(); + InnerHeader innerHeader = new() + { + Magic = _innerHeaderMagic, - innerHeader.Magic = _innerHeaderMagic; + InfosLength = (int)_infosStream.Length, + CodesLength = _codesList.Length(), + RelocsLength = (int)_relocsStream.Length, + UnwindInfosLength = (int)_unwindInfosStream.Length, + }; - innerHeader.InfosLength = (int)_infosStream.Length; - innerHeader.CodesLength = _codesList.Length(); - innerHeader.RelocsLength = (int)_relocsStream.Length; - innerHeader.UnwindInfosLength = (int)_unwindInfosStream.Length; + OuterHeader outerHeader = new() + { + Magic = _outerHeaderMagic, - OuterHeader outerHeader = new OuterHeader(); + CacheFileVersion = InternalVersion, + Endianness = GetEndianness(), + FeatureInfo = GetFeatureInfo(), + MemoryManagerMode = GetMemoryManagerMode(), + OSPlatform = GetOSPlatform(), + Architecture = (uint)RuntimeInformation.ProcessArchitecture, - outerHeader.Magic = _outerHeaderMagic; - - outerHeader.CacheFileVersion = InternalVersion; - outerHeader.Endianness = GetEndianness(); - outerHeader.FeatureInfo = GetFeatureInfo(); - outerHeader.MemoryManagerMode = GetMemoryManagerMode(); - outerHeader.OSPlatform = GetOSPlatform(); - outerHeader.Architecture = (uint)RuntimeInformation.ProcessArchitecture; - - outerHeader.UncompressedStreamSize = + UncompressedStreamSize = (long)Unsafe.SizeOf() + innerHeader.InfosLength + innerHeader.CodesLength + innerHeader.RelocsLength + - innerHeader.UnwindInfosLength; + innerHeader.UnwindInfosLength, + }; outerHeader.SetHeaderHash(); @@ -462,58 +461,54 @@ namespace ARMeilleure.Translation.PTC { intPtr = Marshal.AllocHGlobal(new IntPtr(outerHeader.UncompressedStreamSize)); - using (UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite)) + using UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite); + stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin); + + ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength); + _infosStream.WriteTo(stream); + + ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty; + _codesList.WriteTo(stream); + + ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength); + _relocsStream.WriteTo(stream); + + ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength); + _unwindInfosStream.WriteTo(stream); + + Debug.Assert(stream.Position == stream.Length); + + innerHeader.InfosHash = XXHash128.ComputeHash(infosBytes); + innerHeader.CodesHash = XXHash128.ComputeHash(codesBytes); + innerHeader.RelocsHash = XXHash128.ComputeHash(relocsBytes); + innerHeader.UnwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes); + + innerHeader.SetHeaderHash(); + + stream.Seek(0L, SeekOrigin.Begin); + SerializeStructure(stream, innerHeader); + + translatedFuncsCount = GetEntriesCount(); + + ResetCarriersIfNeeded(); + + using FileStream compressedStream = new(fileName, FileMode.OpenOrCreate); + using DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true); + try { - stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin); - - ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength); - _infosStream.WriteTo(stream); - - ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty; - _codesList.WriteTo(stream); - - ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength); - _relocsStream.WriteTo(stream); - - ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength); - _unwindInfosStream.WriteTo(stream); - - Debug.Assert(stream.Position == stream.Length); - - innerHeader.InfosHash = XXHash128.ComputeHash(infosBytes); - innerHeader.CodesHash = XXHash128.ComputeHash(codesBytes); - innerHeader.RelocsHash = XXHash128.ComputeHash(relocsBytes); - innerHeader.UnwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes); - - innerHeader.SetHeaderHash(); + SerializeStructure(compressedStream, outerHeader); stream.Seek(0L, SeekOrigin.Begin); - SerializeStructure(stream, innerHeader); + stream.CopyTo(deflateStream); + } + catch + { + compressedStream.Position = 0L; + } - translatedFuncsCount = GetEntriesCount(); - - ResetCarriersIfNeeded(); - - using (FileStream compressedStream = new(fileName, FileMode.OpenOrCreate)) - using (DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true)) - { - try - { - SerializeStructure(compressedStream, outerHeader); - - stream.Seek(0L, SeekOrigin.Begin); - stream.CopyTo(deflateStream); - } - catch - { - compressedStream.Position = 0L; - } - - if (compressedStream.Position < compressedStream.Length) - { - compressedStream.SetLength(compressedStream.Position); - } - } + if (compressedStream.Position < compressedStream.Length) + { + compressedStream.SetLength(compressedStream.Position); } } finally @@ -647,7 +642,7 @@ namespace ARMeilleure.Translation.PTC return _codesList[index]; } - private RelocEntry[] GetRelocEntries(BinaryReader relocsReader, int relocEntriesCount) + private static RelocEntry[] GetRelocEntries(BinaryReader relocsReader, int relocEntriesCount) { RelocEntry[] relocEntries = new RelocEntry[relocEntriesCount]; @@ -663,7 +658,7 @@ namespace ARMeilleure.Translation.PTC return relocEntries; } - private void PatchCode(Translator translator, Span code, RelocEntry[] relocEntries, out Counter callCounter) + private static void PatchCode(Translator translator, Span code, RelocEntry[] relocEntries, out Counter callCounter) { callCounter = null; @@ -678,7 +673,10 @@ namespace ARMeilleure.Translation.PTC if (translator.FunctionTable.IsValid(guestAddress)) { - unsafe { imm = (IntPtr)Unsafe.AsPointer(ref translator.FunctionTable.GetValue(guestAddress)); } + unsafe + { + imm = (IntPtr)Unsafe.AsPointer(ref translator.FunctionTable.GetValue(guestAddress)); + } } } else if (symbol.Type == SymbolType.DelegateTable) @@ -696,12 +694,12 @@ namespace ARMeilleure.Translation.PTC } else if (symbol == CountTableSymbol) { - if (callCounter == null) - { - callCounter = new Counter(translator.CountTable); - } + callCounter ??= new Counter(translator.CountTable); - unsafe { imm = (IntPtr)Unsafe.AsPointer(ref callCounter.Value); } + unsafe + { + imm = (IntPtr)Unsafe.AsPointer(ref callCounter.Value); + } } else if (symbol == DispatchStubSymbol) { @@ -717,7 +715,7 @@ namespace ARMeilleure.Translation.PTC } } - private UnwindInfo ReadUnwindInfo(BinaryReader unwindInfosReader) + private static UnwindInfo ReadUnwindInfo(BinaryReader unwindInfosReader) { int pushEntriesLength = unwindInfosReader.ReadInt32(); @@ -738,7 +736,7 @@ namespace ARMeilleure.Translation.PTC return new UnwindInfo(pushEntries, prologueSize); } - private TranslatedFunction FastTranslate( + private static TranslatedFunction FastTranslate( byte[] code, Counter callCounter, ulong guestSize, @@ -809,13 +807,13 @@ namespace ARMeilleure.Translation.PTC PtcStateChanged?.Invoke(PtcLoadingState.Start, _translateCount, _translateTotalCount); - using AutoResetEvent progressReportEvent = new AutoResetEvent(false); + using AutoResetEvent progressReportEvent = new(false); - Thread progressReportThread = new Thread(ReportProgress) + Thread progressReportThread = new(ReportProgress) { Name = "Ptc.ProgressReporter", Priority = ThreadPriority.Lowest, - IsBackground = true + IsBackground = true, }; progressReportThread.Start(progressReportEvent); @@ -845,12 +843,14 @@ namespace ARMeilleure.Translation.PTC } } - List threads = new List(); + List threads = new(); for (int i = 0; i < degreeOfParallelism; i++) { - Thread thread = new Thread(TranslateFuncs); - thread.IsBackground = true; + Thread thread = new(TranslateFuncs) + { + IsBackground = true, + }; threads.Add(thread); } @@ -871,8 +871,10 @@ namespace ARMeilleure.Translation.PTC Logger.Info?.Print(LogClass.Ptc, $"{_translateCount} of {_translateTotalCount} functions translated | Thread count: {degreeOfParallelism} in {sw.Elapsed.TotalSeconds} s"); - Thread preSaveThread = new Thread(PreSave); - preSaveThread.IsBackground = true; + Thread preSaveThread = new(PreSave) + { + IsBackground = true, + }; preSaveThread.Start(); } @@ -910,15 +912,16 @@ namespace ARMeilleure.Translation.PTC RelocInfo relocInfo = compiledFunc.RelocInfo; UnwindInfo unwindInfo = compiledFunc.UnwindInfo; - InfoEntry infoEntry = new InfoEntry(); - - infoEntry.Address = address; - infoEntry.GuestSize = guestSize; - infoEntry.Hash = hash; - infoEntry.HighCq = highCq; - infoEntry.Stubbed = false; - infoEntry.CodeLength = code.Length; - infoEntry.RelocEntriesCount = relocInfo.Entries.Length; + InfoEntry infoEntry = new() + { + Address = address, + GuestSize = guestSize, + Hash = hash, + HighCq = highCq, + Stubbed = false, + CodeLength = code.Length, + RelocEntriesCount = relocInfo.Entries.Length, + }; SerializeStructure(_infosStream, infoEntry); @@ -996,10 +999,12 @@ namespace ARMeilleure.Translation.PTC { uint osPlatform = 0u; +#pragma warning disable IDE0055 // Disable formatting osPlatform |= (OperatingSystem.IsFreeBSD() ? 1u : 0u) << 0; osPlatform |= (OperatingSystem.IsLinux() ? 1u : 0u) << 1; osPlatform |= (OperatingSystem.IsMacOS() ? 1u : 0u) << 2; osPlatform |= (OperatingSystem.IsWindows() ? 1u : 0u) << 3; +#pragma warning restore IDE0055 return osPlatform; } @@ -1025,14 +1030,14 @@ namespace ARMeilleure.Translation.PTC { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())); + HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]); } public bool IsHeaderValid() { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())) == HeaderHash; + return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]) == HeaderHash; } } @@ -1060,14 +1065,14 @@ namespace ARMeilleure.Translation.PTC { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())); + HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]); } public bool IsHeaderValid() { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())) == HeaderHash; + return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]) == HeaderHash; } } diff --git a/src/ARMeilleure/Translation/PTC/PtcFormatter.cs b/src/ARMeilleure/Translation/PTC/PtcFormatter.cs index 2f7a9c21..ddac3133 100644 --- a/src/ARMeilleure/Translation/PTC/PtcFormatter.cs +++ b/src/ARMeilleure/Translation/PTC/PtcFormatter.cs @@ -47,7 +47,7 @@ namespace ARMeilleure.Translation.PTC [MethodImpl(MethodImplOptions.AggressiveInlining)] public static T DeserializeStructure(Stream stream) where T : struct { - T structure = default(T); + T structure = default; Span spanT = MemoryMarshal.CreateSpan(ref structure, 1); int bytesCount = stream.Read(MemoryMarshal.AsBytes(spanT)); @@ -176,4 +176,4 @@ namespace ARMeilleure.Translation.PTC } #endregion } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs b/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs index 526cf91f..587be793 100644 --- a/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs +++ b/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs @@ -4,6 +4,6 @@ namespace ARMeilleure.Translation.PTC { Start, Loading, - Loaded + Loaded, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/PTC/PtcProfiler.cs b/src/ARMeilleure/Translation/PTC/PtcProfiler.cs index 391e29c7..3a4bfcec 100644 --- a/src/ARMeilleure/Translation/PTC/PtcProfiler.cs +++ b/src/ARMeilleure/Translation/PTC/PtcProfiler.cs @@ -12,7 +12,6 @@ using System.IO.Compression; using System.Runtime.CompilerServices; using System.Runtime.InteropServices; using System.Threading; - using static ARMeilleure.Translation.PTC.PtcFormatter; namespace ARMeilleure.Translation.PTC @@ -46,7 +45,7 @@ namespace ARMeilleure.Translation.PTC public bool Enabled { get; private set; } public ulong StaticCodeStart { get; set; } - public ulong StaticCodeSize { get; set; } + public ulong StaticCodeSize { get; set; } public PtcProfiler(Ptc ptc) { @@ -129,8 +128,8 @@ namespace ARMeilleure.Translation.PTC string fileNameActual = $"{_ptc.CachePathActual}.info"; string fileNameBackup = $"{_ptc.CachePathBackup}.info"; - FileInfo fileInfoActual = new FileInfo(fileNameActual); - FileInfo fileInfoBackup = new FileInfo(fileNameBackup); + FileInfo fileInfoActual = new(fileNameActual); + FileInfo fileInfoBackup = new(fileNameBackup); if (fileInfoActual.Exists && fileInfoActual.Length != 0L) { @@ -183,42 +182,40 @@ namespace ARMeilleure.Translation.PTC return false; } - using (MemoryStream stream = MemoryStreamManager.Shared.GetStream()) + using MemoryStream stream = MemoryStreamManager.Shared.GetStream(); + Debug.Assert(stream.Seek(0L, SeekOrigin.Begin) == 0L && stream.Length == 0L); + + try { - Debug.Assert(stream.Seek(0L, SeekOrigin.Begin) == 0L && stream.Length == 0L); - - try - { - deflateStream.CopyTo(stream); - } - catch - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - Debug.Assert(stream.Position == stream.Length); - - stream.Seek(0L, SeekOrigin.Begin); - - Hash128 expectedHash = DeserializeStructure(stream); - - Hash128 actualHash = XXHash128.ComputeHash(GetReadOnlySpan(stream)); - - if (actualHash != expectedHash) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - ProfiledFuncs = Deserialize(stream); - - Debug.Assert(stream.Position == stream.Length); - - _lastHash = actualHash; + deflateStream.CopyTo(stream); } + catch + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + Debug.Assert(stream.Position == stream.Length); + + stream.Seek(0L, SeekOrigin.Begin); + + Hash128 expectedHash = DeserializeStructure(stream); + + Hash128 actualHash = XXHash128.ComputeHash(GetReadOnlySpan(stream)); + + if (actualHash != expectedHash) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + ProfiledFuncs = Deserialize(stream); + + Debug.Assert(stream.Position == stream.Length); + + _lastHash = actualHash; } long fileSize = new FileInfo(fileName).Length; @@ -233,12 +230,12 @@ namespace ARMeilleure.Translation.PTC return DeserializeDictionary(stream, (stream) => DeserializeStructure(stream)); } - private ReadOnlySpan GetReadOnlySpan(MemoryStream memoryStream) + private static ReadOnlySpan GetReadOnlySpan(MemoryStream memoryStream) { return new(memoryStream.GetBuffer(), (int)memoryStream.Position, (int)memoryStream.Length - (int)memoryStream.Position); } - private void InvalidateCompressedStream(FileStream compressedStream) + private static void InvalidateCompressedStream(FileStream compressedStream) { compressedStream.SetLength(0L); } @@ -250,7 +247,7 @@ namespace ARMeilleure.Translation.PTC string fileNameActual = $"{_ptc.CachePathActual}.info"; string fileNameBackup = $"{_ptc.CachePathBackup}.info"; - FileInfo fileInfoActual = new FileInfo(fileNameActual); + FileInfo fileInfoActual = new(fileNameActual); if (fileInfoActual.Exists && fileInfoActual.Length != 0L) { @@ -266,12 +263,13 @@ namespace ARMeilleure.Translation.PTC { int profiledFuncsCount; - OuterHeader outerHeader = new OuterHeader(); + OuterHeader outerHeader = new() + { + Magic = _outerHeaderMagic, - outerHeader.Magic = _outerHeaderMagic; - - outerHeader.InfoFileVersion = InternalVersion; - outerHeader.Endianness = Ptc.GetEndianness(); + InfoFileVersion = InternalVersion, + Endianness = Ptc.GetEndianness(), + }; outerHeader.SetHeaderHash(); @@ -301,28 +299,26 @@ namespace ARMeilleure.Translation.PTC return; } - using (FileStream compressedStream = new(fileName, FileMode.OpenOrCreate)) - using (DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true)) + using FileStream compressedStream = new(fileName, FileMode.OpenOrCreate); + using DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true); + try { - try - { - SerializeStructure(compressedStream, outerHeader); + SerializeStructure(compressedStream, outerHeader); - stream.WriteTo(deflateStream); + stream.WriteTo(deflateStream); - _lastHash = hash; - } - catch - { - compressedStream.Position = 0L; + _lastHash = hash; + } + catch + { + compressedStream.Position = 0L; - _lastHash = default; - } + _lastHash = default; + } - if (compressedStream.Position < compressedStream.Length) - { - compressedStream.SetLength(compressedStream.Position); - } + if (compressedStream.Position < compressedStream.Length) + { + compressedStream.SetLength(compressedStream.Position); } } @@ -334,7 +330,7 @@ namespace ARMeilleure.Translation.PTC } } - private void Serialize(Stream stream, Dictionary profiledFuncs) + private static void Serialize(Stream stream, Dictionary profiledFuncs) { SerializeDictionary(stream, profiledFuncs, (stream, structure) => SerializeStructure(stream, structure)); } @@ -354,14 +350,14 @@ namespace ARMeilleure.Translation.PTC { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())); + HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]); } public bool IsHeaderValid() { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())) == HeaderHash; + return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]) == HeaderHash; } } @@ -418,4 +414,4 @@ namespace ARMeilleure.Translation.PTC } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/PTC/PtcState.cs b/src/ARMeilleure/Translation/PTC/PtcState.cs index ca4f4108..f6692e87 100644 --- a/src/ARMeilleure/Translation/PTC/PtcState.cs +++ b/src/ARMeilleure/Translation/PTC/PtcState.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.Translation.PTC Enabled, Continuing, Closing, - Disabled + Disabled, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/RegisterToLocal.cs b/src/ARMeilleure/Translation/RegisterToLocal.cs index abb9b373..91372eb0 100644 --- a/src/ARMeilleure/Translation/RegisterToLocal.cs +++ b/src/ARMeilleure/Translation/RegisterToLocal.cs @@ -9,7 +9,7 @@ namespace ARMeilleure.Translation { public static void Rename(ControlFlowGraph cfg) { - Dictionary registerToLocalMap = new Dictionary(); + Dictionary registerToLocalMap = new(); Operand GetLocal(Operand op) { @@ -49,4 +49,4 @@ namespace ARMeilleure.Translation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/RegisterUsage.cs b/src/ARMeilleure/Translation/RegisterUsage.cs index 3ec0a7b4..c8c25062 100644 --- a/src/ARMeilleure/Translation/RegisterUsage.cs +++ b/src/ARMeilleure/Translation/RegisterUsage.cs @@ -12,7 +12,7 @@ namespace ARMeilleure.Translation static class RegisterUsage { private const int RegsCount = 32; - private const int RegsMask = RegsCount - 1; + private const int RegsMask = RegsCount - 1; private readonly struct RegisterMask : IEquatable { @@ -90,7 +90,7 @@ namespace ARMeilleure.Translation public static void RunPass(ControlFlowGraph cfg, ExecutionMode mode) { // Compute local register inputs and outputs used inside blocks. - RegisterMask[] localInputs = new RegisterMask[cfg.Blocks.Count]; + RegisterMask[] localInputs = new RegisterMask[cfg.Blocks.Count]; RegisterMask[] localOutputs = new RegisterMask[cfg.Blocks.Count]; for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext) @@ -119,7 +119,7 @@ namespace ARMeilleure.Translation // Compute global register inputs and outputs used across blocks. RegisterMask[] globalCmnOutputs = new RegisterMask[cfg.Blocks.Count]; - RegisterMask[] globalInputs = new RegisterMask[cfg.Blocks.Count]; + RegisterMask[] globalInputs = new RegisterMask[cfg.Blocks.Count]; RegisterMask[] globalOutputs = new RegisterMask[cfg.Blocks.Count]; bool modified; @@ -286,10 +286,12 @@ namespace ARMeilleure.Translation switch (register.Type) { +#pragma warning disable IDE0055 // Disable formatting case RegisterType.Flag: intMask = (1L << RegsCount) << register.Index; break; case RegisterType.Integer: intMask = 1L << register.Index; break; case RegisterType.FpFlag: vecMask = (1L << RegsCount) << register.Index; break; case RegisterType.Vector: vecMask = 1L << register.Index; break; +#pragma warning restore IDE0055 } return new RegisterMask(intMask, vecMask); @@ -373,15 +375,14 @@ namespace ARMeilleure.Translation private static OperandType GetOperandType(RegisterType type, ExecutionMode mode) { - switch (type) + return type switch { - case RegisterType.Flag: return OperandType.I32; - case RegisterType.FpFlag: return OperandType.I32; - case RegisterType.Integer: return (mode == ExecutionMode.Aarch64) ? OperandType.I64 : OperandType.I32; - case RegisterType.Vector: return OperandType.V128; - } - - throw new ArgumentException($"Invalid register type \"{type}\"."); + RegisterType.Flag => OperandType.I32, + RegisterType.FpFlag => OperandType.I32, + RegisterType.Integer => (mode == ExecutionMode.Aarch64) ? OperandType.I64 : OperandType.I32, + RegisterType.Vector => OperandType.V128, + _ => throw new ArgumentException($"Invalid register type \"{type}\"."), + }; } private static bool EndsWithReturn(BasicBlock block) @@ -391,4 +392,4 @@ namespace ARMeilleure.Translation return last != default && last.Instruction == Instruction.Return; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/SsaConstruction.cs b/src/ARMeilleure/Translation/SsaConstruction.cs index 2b6efc11..cddcfcd4 100644 --- a/src/ARMeilleure/Translation/SsaConstruction.cs +++ b/src/ARMeilleure/Translation/SsaConstruction.cs @@ -180,7 +180,7 @@ namespace ARMeilleure.Translation } previous = current; - current = current.ImmediateDominator; + current = current.ImmediateDominator; } while (previous != current); @@ -286,4 +286,4 @@ namespace ARMeilleure.Translation return key; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/SsaDeconstruction.cs b/src/ARMeilleure/Translation/SsaDeconstruction.cs index cd6bcca1..68af54e5 100644 --- a/src/ARMeilleure/Translation/SsaDeconstruction.cs +++ b/src/ARMeilleure/Translation/SsaDeconstruction.cs @@ -45,4 +45,4 @@ namespace ARMeilleure.Translation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/TranslatedFunction.cs b/src/ARMeilleure/Translation/TranslatedFunction.cs index f007883e..1446c254 100644 --- a/src/ARMeilleure/Translation/TranslatedFunction.cs +++ b/src/ARMeilleure/Translation/TranslatedFunction.cs @@ -31,4 +31,4 @@ namespace ARMeilleure.Translation return dispatcher(context.NativeContextPtr, (ulong)FuncPointer); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Translator.cs b/src/ARMeilleure/Translation/Translator.cs index 234be2ac..dc18038b 100644 --- a/src/ARMeilleure/Translation/Translator.cs +++ b/src/ARMeilleure/Translation/Translator.cs @@ -22,24 +22,24 @@ namespace ARMeilleure.Translation { public class Translator { - private static readonly AddressTable.Level[] Levels64Bit = + private static readonly AddressTable.Level[] _levels64Bit = new AddressTable.Level[] { new(31, 17), new(23, 8), new(15, 8), new( 7, 8), - new( 2, 5) + new( 2, 5), }; - private static readonly AddressTable.Level[] Levels32Bit = + private static readonly AddressTable.Level[] _levels32Bit = new AddressTable.Level[] { new(31, 17), new(23, 8), new(15, 8), new( 7, 8), - new( 1, 6) + new( 1, 6), }; private readonly IJitMemoryAllocator _allocator; @@ -75,7 +75,7 @@ namespace ARMeilleure.Translation CountTable = new EntryTable(); Functions = new TranslatorCache(); - FunctionTable = new AddressTable(for64Bits ? Levels64Bit : Levels32Bit); + FunctionTable = new AddressTable(for64Bits ? _levels64Bit : _levels32Bit); Stubs = new TranslatorStubs(this); FunctionTable.Fill = (ulong)Stubs.SlowDispatchStub; @@ -126,7 +126,7 @@ namespace ARMeilleure.Translation // TODO: Use physical cores rather than logical. This only really makes sense for processors with // hyperthreading. Requires OS specific code. int unboundedThreadCount = Math.Max(1, (Environment.ProcessorCount - 6) / 3); - int threadCount = Math.Min(4, unboundedThreadCount); + int threadCount = Math.Min(4, unboundedThreadCount); Thread[] backgroundTranslationThreads = new Thread[threadCount]; @@ -134,10 +134,10 @@ namespace ARMeilleure.Translation { bool last = i != 0 && i == unboundedThreadCount - 1; - backgroundTranslationThreads[i] = new Thread(BackgroundTranslate) + backgroundTranslationThreads[i] = new(BackgroundTranslate) { Name = "CPU.BackgroundTranslatorThread." + i, - Priority = last ? ThreadPriority.Lowest : ThreadPriority.Normal + Priority = last ? ThreadPriority.Lowest : ThreadPriority.Normal, }; backgroundTranslationThreads[i].Start(); diff --git a/src/ARMeilleure/Translation/TranslatorStubs.cs b/src/ARMeilleure/Translation/TranslatorStubs.cs index 69648df4..eceb1b74 100644 --- a/src/ARMeilleure/Translation/TranslatorStubs.cs +++ b/src/ARMeilleure/Translation/TranslatorStubs.cs @@ -224,7 +224,7 @@ namespace ARMeilleure.Translation /// Emitter context for the method /// Pointer to the native context /// True if entering guest code, false otherwise - private void EmitSyncFpContext(EmitterContext context, Operand nativeContext, bool enter) + private static void EmitSyncFpContext(EmitterContext context, Operand nativeContext, bool enter) { if (enter) { diff --git a/src/ARMeilleure/Translation/TranslatorTestMethods.cs b/src/ARMeilleure/Translation/TranslatorTestMethods.cs index ab96019a..35cd8dc5 100644 --- a/src/ARMeilleure/Translation/TranslatorTestMethods.cs +++ b/src/ARMeilleure/Translation/TranslatorTestMethods.cs @@ -1,7 +1,6 @@ using ARMeilleure.CodeGen.X86; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; -using ARMeilleure.Translation; using System; using System.Runtime.InteropServices; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -62,7 +61,7 @@ namespace ARMeilleure.Translation public static FpFlagsPInvokeTest GenerateFpFlagsPInvokeTest() { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); Operand methodAddress = context.Copy(context.LoadArgument(OperandType.I64, 0)); @@ -110,7 +109,7 @@ namespace ARMeilleure.Translation context.MarkLabel(correct2Label); - // Call a managed method. This method should not change Fz state. + // Call a managed method. This method should not change Fz state. context.Call(methodAddress, OperandType.None);