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Author SHA1 Message Date
LDj3SNuD
c7387be0d2 Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)
* Update AOpCodeTable.cs

* Update AInstEmitSimdShift.cs

* Update CpuTestSimdShImm.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Create CpuTestSimdIns.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs
2018-09-17 01:54:05 -03:00
LDj3SNuD
a0c78f7920 Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)
* Update AOpCodeTable.cs

* Update AInstEmitSimdShift.cs

* Update ASoftFallback.cs

* Update AOpCodeSimdShImm.cs

* Update ABitUtils.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Create CpuTestSimdShImm.cs

* Create CpuTestSimdRegElem.cs

* Address PR feedback.

* Nit.

* Nit.
2018-09-08 14:24:29 -03:00
gdkchan
514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions

* Address PR feedback

* Address PR feedback

* Remove another useless temp var

* nit: Alignment

* Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount()

* Fix encodings and move flag bit test out of the loop
2018-07-14 13:13:02 -03:00
gdkchan
b50bc46888 CPU fix for the cases using a Mask with shift = 0 2018-03-14 01:59:22 -03:00
gdkchan
553ba659c4 Add CRC32 instruction and SLI (vector) 2018-03-14 00:12:05 -03:00
gdkchan
553f6c2976 Fix EmitScalarUnaryOpF and add SSRA (vector) 2018-03-10 00:00:31 -03:00
gdkchan
aa2d2b3149 Add SHLL instruction 2018-03-09 23:28:38 -03:00
emmauss
62b827f474 Split main project into core,graphics and chocolarm4 subproject (#29) 2018-02-20 17:09:23 -03:00
Renamed from Ryujinx/Cpu/Instruction/AInstEmitSimdShift.cs (Browse further)