5 commits

Author	SHA1	Message	Date
LDj3SNuD	a5ad1e9a06	Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) ... * Update AOpCodeTable.cs * Update AInstEmitSimdLogical.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs	2018-04-25 23:20:22 -03:00
LDj3SNuD	873a7cd112	Add Cls Instruction. (#67) ... * Update AInstEmitAlu.cs * Update ASoftFallback.cs * Update AOpCodeTable.cs	2018-03-23 22:06:05 -03:00
gdkchan	708761963e	Fix corner cases of ADCS and SBFM	2018-02-26 15:56:34 -03:00
gdkchan	31b35a9645	Add FABD (scalar), ADCS, SBCS instructions, update config with better default control mappings, update readme with the new mappings	2018-02-24 18:47:08 -03:00
emmauss	62b827f474	Split main project into core,graphics and chocolarm4 subproject (#29)	2018-02-20 17:09:23 -03:00

Renamed from Ryujinx/Cpu/Instruction/AInstEmitAlu.cs (Browse further)