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Author SHA1 Message Date
gdkchan
e21ebbf666 Misc. CPU optimizations (#575)
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0

* Refactoring

* Add a config entry to enable or disable the reg load/store opt.

* Remove unnecessary register state stores for calls when the callee is know

* Rename IoType to VarType

* Enable tier 0 while fixing some perf issues related to tier 0

* Small tweak -- Compile before adding to the cache, to avoid lags

* Add required config entry
2019-02-28 13:03:31 +11:00
gdkchan
932224f051 ARM exclusive monitor and multicore fixes (#589)
* Implement ARM exclusive load/store with compare exchange insts, and enable multicore by default

* Fix comment typo

* Support Linux and OSX on MemoryAlloc and CompareExchange128, some cleanup

* Use intel syntax on assembly code

* Adjust identation

* Add CPUID check and fix exclusive reservation granule size

* Update schema multicore scheduling default value

* Make the cpu id check code lower case aswell
2019-02-19 10:52:06 +11:00
jduncanator
d306115750 Logger and Configuration Refactoring (#573)
* Logging: Refactor log targets into Ryujinx.Common

* Logger: Implement JSON Log Target

* Logger: Optimize Console/File logging targets

Implement a simple ObjectPool to pool up StringBuilders to avoid causing excessive GCing of gen1/2 items when large amounts of log entries are being generated.

We can also pre-determine the async overflow action at initialization time, allowing for an easy optimization in the message enqueue function, avoiding a number of comparisons.

* Logger: Implement LogFormatters

* Config: Refactor configuration file and loading

* Config: Rename to .jsonc to avoid highlighting issues in VSC and GitHub

* Resolve style nits

* Config: Resolve incorrect default key binding

* Config: Also update key binding default in schema

* Tidy up namespace imports

* Config: Update CONFIG.md to reflect new Config file
2019-02-11 09:00:32 -03:00