3 commits

Author	SHA1	Message	Date
LDj3SNuD	ca1e37a295	Remove old Tester, update Tests (some reworks). (#400) ... * Delete Bits.cs * Delete Integer.cs * Delete Instructions.cs * Delete Pseudocode.cs * Add files via upload * Add mnemonic. * Literals all uppercase. * Nit. * Allow FPSR control. * Allow FPSR control. * Allow FPSR control.	2018-09-08 14:23:07 -03:00
Merry	326777ca4a	Ryujinx.Tests: Add unicorn to test framework (#389) ... * Ryujinx.Tests: Add unicorn to test framework * CpuTestSimdArithmetic: Comment out inaccurate results	2018-09-01 11:24:05 -03:00
LDj3SNuD	8f6387128a	Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) ... * Add files via upload * Add files via upload * Add files via upload * CPE * Add EmitSse42Crc32() * Update CpuTestSimdCmp.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update Instructions.cs	2018-06-25 22:32:29 -03:00