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ryujinx-final/ARMeilleure/Decoders/OpCode32SimdLong.cs
gdkchan 89ccec197e
Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)
* Implement VMOVL and VORR.I32 AArch32 SIMD instructions

* Rename <dt> to <size> on test description

* Rename Widen to Long and improve VMOVL implementation a bit
2020-03-10 16:17:30 +11:00

27 lines
824 B
C#

namespace ARMeilleure.Decoders
{
class OpCode32SimdLong : OpCode32SimdBase
{
public bool U { get; private set; }
public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int imm3h = (opCode >> 19) & 0x7;
// The value must be a power of 2, otherwise it is the encoding of another instruction.
switch (imm3h)
{
case 1: Size = 0; break;
case 2: Size = 1; break;
case 4: Size = 2; break;
}
U = ((opCode >> 24) & 0x1) != 0;
RegisterSize = RegisterSize.Simd64;
Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf);
Vm = ((opCode >> 1) & 0x10) | ((opCode >> 0) & 0xf);
}
}
}