a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
354 lines
13 KiB
C#
354 lines
13 KiB
C#
using ChocolArm64.Translation;
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using System;
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using System.Diagnostics;
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using System.Runtime.CompilerServices;
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using System.Runtime.Intrinsics;
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using static ChocolArm64.Instructions.VectorHelper;
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namespace ChocolArm64.State
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{
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public class CpuThreadState : ARMeilleure.State.IExecutionContext
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{
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private const int MinCountForCheck = 40000;
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internal const int ErgSizeLog2 = 4;
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internal const int DczSizeLog2 = 4;
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public ulong X0, X1, X2, X3, X4, X5, X6, X7,
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X8, X9, X10, X11, X12, X13, X14, X15,
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X16, X17, X18, X19, X20, X21, X22, X23,
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X24, X25, X26, X27, X28, X29, X30, X31;
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public Vector128<float> V0, V1, V2, V3, V4, V5, V6, V7,
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V8, V9, V10, V11, V12, V13, V14, V15,
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V16, V17, V18, V19, V20, V21, V22, V23,
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V24, V25, V26, V27, V28, V29, V30, V31;
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public bool IsAarch32 { get; set; }
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public bool Thumb;
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public bool BigEndian;
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public bool Overflow;
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public bool Carry;
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public bool Zero;
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public bool Negative;
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public int ElrHyp;
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public bool Running { get; set; }
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private bool _interrupted;
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private int _syncCount;
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public long TpidrEl0 { get; set; }
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public long Tpidr { get; set; }
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public int CFpcr { get; set; }
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public int CFpsr { get; set; }
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public ARMeilleure.State.FPCR Fpcr
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{
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get => (ARMeilleure.State.FPCR)CFpcr;
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set => CFpcr = (int)value;
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}
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public ARMeilleure.State.FPSR Fpsr
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{
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get => (ARMeilleure.State.FPSR)CFpsr;
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set => CFpsr = (int)value;
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}
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public int Psr
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{
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get
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{
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return (Negative ? (int)PState.NMask : 0) |
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(Zero ? (int)PState.ZMask : 0) |
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(Carry ? (int)PState.CMask : 0) |
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(Overflow ? (int)PState.VMask : 0);
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}
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}
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public uint CtrEl0 => 0x8444c004;
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public uint DczidEl0 => 0x00000004;
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public ulong CntfrqEl0 { get; set; }
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public ulong CntpctEl0
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{
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get
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{
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double ticks = _tickCounter.ElapsedTicks * _hostTickFreq;
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return (ulong)(ticks * CntfrqEl0);
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}
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}
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public event EventHandler<EventArgs> Interrupt;
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public event EventHandler<ARMeilleure.State.InstExceptionEventArgs> Break;
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public event EventHandler<ARMeilleure.State.InstExceptionEventArgs> SupervisorCall;
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public event EventHandler<ARMeilleure.State.InstUndefinedEventArgs> Undefined;
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private static Stopwatch _tickCounter;
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private static double _hostTickFreq;
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internal Translator CurrentTranslator;
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private ulong _exclusiveAddress;
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internal ulong ExclusiveValueLow { get; set; }
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internal ulong ExclusiveValueHigh { get; set; }
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public CpuThreadState()
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{
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ClearExclusiveAddress();
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Running = true;
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}
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static CpuThreadState()
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{
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_hostTickFreq = 1.0 / Stopwatch.Frequency;
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_tickCounter = new Stopwatch();
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_tickCounter.Start();
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}
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internal void SetExclusiveAddress(ulong address)
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{
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_exclusiveAddress = GetMaskedExclusiveAddress(address);
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}
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internal bool CheckExclusiveAddress(ulong address)
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{
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return GetMaskedExclusiveAddress(address) == _exclusiveAddress;
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}
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internal void ClearExclusiveAddress()
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{
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_exclusiveAddress = ulong.MaxValue;
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}
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private ulong GetMaskedExclusiveAddress(ulong address)
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{
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return address & ~((4UL << ErgSizeLog2) - 1);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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internal bool Synchronize()
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{
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// Firing a interrupt frequently is expensive, so we only
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// do it after a given number of instructions has executed.
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_syncCount++;
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if (_syncCount >= MinCountForCheck)
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{
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CheckInterrupt();
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}
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return Running;
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}
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[MethodImpl(MethodImplOptions.NoInlining)]
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private void CheckInterrupt()
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{
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_syncCount = 0;
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if (_interrupted)
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{
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_interrupted = false;
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Interrupt?.Invoke(this, EventArgs.Empty);
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}
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}
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public ulong GetX(int index)
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{
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switch (index)
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{
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case 0: return X0;
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case 1: return X1;
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case 2: return X2;
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case 3: return X3;
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case 4: return X4;
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case 5: return X5;
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case 6: return X6;
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case 7: return X7;
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case 8: return X8;
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case 9: return X9;
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case 10: return X10;
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case 11: return X11;
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case 12: return X12;
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case 13: return X13;
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case 14: return X14;
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case 15: return X15;
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case 16: return X16;
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case 17: return X17;
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case 18: return X18;
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case 19: return X19;
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case 20: return X20;
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case 21: return X21;
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case 22: return X22;
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case 23: return X23;
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case 24: return X24;
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case 25: return X25;
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case 26: return X26;
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case 27: return X27;
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case 28: return X28;
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case 29: return X29;
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case 30: return X30;
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case 31: return X31;
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default: throw new ArgumentOutOfRangeException(nameof(index));
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}
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}
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public void SetX(int index, ulong value)
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{
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switch (index)
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{
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case 0: X0 = value; break;
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case 1: X1 = value; break;
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case 2: X2 = value; break;
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case 3: X3 = value; break;
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case 4: X4 = value; break;
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case 5: X5 = value; break;
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case 6: X6 = value; break;
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case 7: X7 = value; break;
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case 8: X8 = value; break;
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case 9: X9 = value; break;
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case 10: X10 = value; break;
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case 11: X11 = value; break;
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case 12: X12 = value; break;
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case 13: X13 = value; break;
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case 14: X14 = value; break;
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case 15: X15 = value; break;
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case 16: X16 = value; break;
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case 17: X17 = value; break;
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case 18: X18 = value; break;
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case 19: X19 = value; break;
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case 20: X20 = value; break;
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case 21: X21 = value; break;
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case 22: X22 = value; break;
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case 23: X23 = value; break;
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case 24: X24 = value; break;
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case 25: X25 = value; break;
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case 26: X26 = value; break;
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case 27: X27 = value; break;
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case 28: X28 = value; break;
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case 29: X29 = value; break;
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case 30: X30 = value; break;
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case 31: X31 = value; break;
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default: throw new ArgumentOutOfRangeException(nameof(index));
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}
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}
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public ARMeilleure.State.V128 GetV(int index)
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{
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switch (index)
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{
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case 0: return new ARMeilleure.State.V128(VectorExtractIntZx(V0, 0, 3), VectorExtractIntZx(V0, 1, 3));
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case 1: return new ARMeilleure.State.V128(VectorExtractIntZx(V1, 0, 3), VectorExtractIntZx(V1, 1, 3));
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case 2: return new ARMeilleure.State.V128(VectorExtractIntZx(V2, 0, 3), VectorExtractIntZx(V2, 1, 3));
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case 3: return new ARMeilleure.State.V128(VectorExtractIntZx(V3, 0, 3), VectorExtractIntZx(V3, 1, 3));
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case 4: return new ARMeilleure.State.V128(VectorExtractIntZx(V4, 0, 3), VectorExtractIntZx(V4, 1, 3));
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case 5: return new ARMeilleure.State.V128(VectorExtractIntZx(V5, 0, 3), VectorExtractIntZx(V5, 1, 3));
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case 6: return new ARMeilleure.State.V128(VectorExtractIntZx(V6, 0, 3), VectorExtractIntZx(V6, 1, 3));
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case 7: return new ARMeilleure.State.V128(VectorExtractIntZx(V7, 0, 3), VectorExtractIntZx(V7, 1, 3));
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case 8: return new ARMeilleure.State.V128(VectorExtractIntZx(V8, 0, 3), VectorExtractIntZx(V8, 1, 3));
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case 9: return new ARMeilleure.State.V128(VectorExtractIntZx(V9, 0, 3), VectorExtractIntZx(V9, 1, 3));
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case 10: return new ARMeilleure.State.V128(VectorExtractIntZx(V10, 0, 3), VectorExtractIntZx(V10, 1, 3));
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case 11: return new ARMeilleure.State.V128(VectorExtractIntZx(V11, 0, 3), VectorExtractIntZx(V11, 1, 3));
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case 12: return new ARMeilleure.State.V128(VectorExtractIntZx(V12, 0, 3), VectorExtractIntZx(V12, 1, 3));
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case 13: return new ARMeilleure.State.V128(VectorExtractIntZx(V13, 0, 3), VectorExtractIntZx(V13, 1, 3));
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case 14: return new ARMeilleure.State.V128(VectorExtractIntZx(V14, 0, 3), VectorExtractIntZx(V14, 1, 3));
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case 15: return new ARMeilleure.State.V128(VectorExtractIntZx(V15, 0, 3), VectorExtractIntZx(V15, 1, 3));
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case 16: return new ARMeilleure.State.V128(VectorExtractIntZx(V16, 0, 3), VectorExtractIntZx(V16, 1, 3));
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case 17: return new ARMeilleure.State.V128(VectorExtractIntZx(V17, 0, 3), VectorExtractIntZx(V17, 1, 3));
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case 18: return new ARMeilleure.State.V128(VectorExtractIntZx(V18, 0, 3), VectorExtractIntZx(V18, 1, 3));
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case 19: return new ARMeilleure.State.V128(VectorExtractIntZx(V19, 0, 3), VectorExtractIntZx(V19, 1, 3));
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case 20: return new ARMeilleure.State.V128(VectorExtractIntZx(V20, 0, 3), VectorExtractIntZx(V20, 1, 3));
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case 21: return new ARMeilleure.State.V128(VectorExtractIntZx(V21, 0, 3), VectorExtractIntZx(V21, 1, 3));
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case 22: return new ARMeilleure.State.V128(VectorExtractIntZx(V22, 0, 3), VectorExtractIntZx(V22, 1, 3));
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case 23: return new ARMeilleure.State.V128(VectorExtractIntZx(V23, 0, 3), VectorExtractIntZx(V23, 1, 3));
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case 24: return new ARMeilleure.State.V128(VectorExtractIntZx(V24, 0, 3), VectorExtractIntZx(V24, 1, 3));
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case 25: return new ARMeilleure.State.V128(VectorExtractIntZx(V25, 0, 3), VectorExtractIntZx(V25, 1, 3));
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case 26: return new ARMeilleure.State.V128(VectorExtractIntZx(V26, 0, 3), VectorExtractIntZx(V26, 1, 3));
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case 27: return new ARMeilleure.State.V128(VectorExtractIntZx(V27, 0, 3), VectorExtractIntZx(V27, 1, 3));
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case 28: return new ARMeilleure.State.V128(VectorExtractIntZx(V28, 0, 3), VectorExtractIntZx(V28, 1, 3));
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case 29: return new ARMeilleure.State.V128(VectorExtractIntZx(V29, 0, 3), VectorExtractIntZx(V29, 1, 3));
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case 30: return new ARMeilleure.State.V128(VectorExtractIntZx(V30, 0, 3), VectorExtractIntZx(V30, 1, 3));
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case 31: return new ARMeilleure.State.V128(VectorExtractIntZx(V31, 0, 3), VectorExtractIntZx(V31, 1, 3));
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default: throw new ArgumentOutOfRangeException(nameof(index));
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}
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}
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public bool GetPstateFlag(ARMeilleure.State.PState flag)
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{
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switch (flag)
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{
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case ARMeilleure.State.PState.NFlag: return Negative;
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case ARMeilleure.State.PState.ZFlag: return Zero;
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case ARMeilleure.State.PState.CFlag: return Carry;
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case ARMeilleure.State.PState.VFlag: return Overflow;
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default: throw new ArgumentOutOfRangeException(nameof(flag));
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}
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}
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public void RequestInterrupt()
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{
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_interrupted = true;
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}
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internal void OnBreak(long position, int imm)
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{
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Break?.Invoke(this, new ARMeilleure.State.InstExceptionEventArgs((ulong)position, imm));
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}
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internal void OnSvcCall(long position, int imm)
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{
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SupervisorCall?.Invoke(this, new ARMeilleure.State.InstExceptionEventArgs((ulong)position, imm));
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}
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internal void OnUndefined(long position, int rawOpCode)
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{
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Undefined?.Invoke(this, new ARMeilleure.State.InstUndefinedEventArgs((ulong)position, rawOpCode));
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}
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internal ExecutionMode GetExecutionMode()
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{
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if (!IsAarch32)
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{
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return ExecutionMode.Aarch64;
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}
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else
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{
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return Thumb ? ExecutionMode.Aarch32Thumb : ExecutionMode.Aarch32Arm;
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}
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}
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internal bool GetFpcrFlag(Fpcr flag)
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{
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return (CFpcr & (1 << (int)flag)) != 0;
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}
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internal void SetFpsrFlag(Fpsr flag)
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{
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CFpsr |= 1 << (int)flag;
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}
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internal RoundMode FPRoundingMode()
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{
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return (RoundMode)((CFpcr >> (int)State.Fpcr.RMode) & 3);
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}
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public void Dispose() { }
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}
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}
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