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FICTURE7 36ec1bc6c0 Relax block ordering constraints (#1535) ... * Relax block ordering constraints Before `block.Next` had to follow `block.ListNext`, now it does not. Instead `CodeGenerator` will now emit the necessary jump instructions to ensure control flow. This makes control flow and block order modifications easier. It also eliminates some simple cases of redundant branches. * Set PPTC version		2020-09-12 12:32:53 -03:00
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Assembler.cs	Implement inline memory load/store exclusive and ordered (#1413)	2020-07-30 11:29:28 -03:00
CallConvName.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CallingConvention.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CodeGenCommon.cs	Optimize x64 loads and stores using complex addressing modes (#972)	2020-03-10 09:29:34 +11:00
CodeGenContext.cs	Add Profiled Persistent Translation Cache. (#769)	2020-06-16 20:28:02 +02:00
CodeGenerator.cs	Relax block ordering constraints (#1535)	2020-09-12 12:32:53 -03:00
HardwareCapabilities.cs	Implement a new physical memory manager and replace DeviceMemory (#856)	2020-05-04 08:54:50 +10:00
IntrinsicInfo.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
IntrinsicTable.cs	Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)	2020-07-13 20:48:14 +10:00
IntrinsicType.cs	Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)	2020-07-13 20:48:14 +10:00
PreAllocator.cs	Improve branch operations (#1442)	2020-08-05 08:52:33 +10:00
X86Condition.cs	Improve branch operations (#1442)	2020-08-05 08:52:33 +10:00
X86Instruction.cs	Implement inline memory load/store exclusive and ordered (#1413)	2020-07-30 11:29:28 -03:00
X86Optimizer.cs	Fix PPTC on Windows 7. (#1369)	2020-07-09 10:45:24 +10:00
X86Register.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00