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LDj3SNuD 063fae50fe Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268) ... * Update CpuTestSimdArithmetic.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update Instructions.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdMove.cs * Delete CpuTestSimdMove.cs		2018-07-15 00:53:26 -03:00
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Decoder	Added support for more shader instructions and texture formats, fix swapped channels in RGB565 and RGBA5551? texture formats, allow zero values on blending registers, initial work to build CFG on the shader decoder, update the BRA instruction to work with it (WIP)	2018-05-29 20:37:10 -03:00
Decoder32	Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)	2018-05-26 17:50:47 -03:00
Events	Implement SvcGetThreadContext3	2018-06-26 01:10:15 -03:00
Exceptions	Split main project into core,graphics and chocolarm4 subproject (#29)	2018-02-20 17:09:23 -03:00
Instruction	Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268)	2018-07-15 00:53:26 -03:00
Instruction32	Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)	2018-05-26 17:50:47 -03:00
Memory	Query multiple pages at once with GetWriteWatch (#222)	2018-07-08 16:55:15 -03:00
State	Implement SvcGetThreadContext3	2018-06-26 01:10:15 -03:00
Translation	Remove broken adds/cmn with condition check optimization (#218)	2018-07-03 21:54:05 -03:00
ABitUtils.cs	Split main project into core,graphics and chocolarm4 subproject (#29)	2018-02-20 17:09:23 -03:00
AOpCodeTable.cs	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)	2018-07-14 13:13:02 -03:00
AOptimizations.cs	Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)	2018-06-25 22:32:29 -03:00
AThread.cs	Fix some thread sync issues (#172)	2018-06-21 23:05:42 -03:00
ATranslatedSub.cs	[CPU] Speed up translation a little bit	2018-04-11 14:44:03 -03:00
ATranslatedSubType.cs	Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)	2018-05-26 17:50:47 -03:00
ATranslator.cs	Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)	2018-05-26 17:50:47 -03:00
ChocolArm64.csproj	Add linux-x64 to RID property to make tests works on linux (#205)	2018-06-30 12:43:04 -03:00