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ryujinx-final/Ryujinx/Cpu
2018-02-17 18:59:37 -03:00
..
Decoder CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements 2018-02-17 18:06:11 -03:00
Exceptions Fixes to memory management 2018-02-09 21:13:18 -03:00
Instruction Add FCVTAS and FCVTAU instructions 2018-02-17 18:59:37 -03:00
Memory CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements 2018-02-17 18:06:11 -03:00
State Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
Translation CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements 2018-02-17 18:06:11 -03:00
ABitUtils.cs aloha 2018-02-04 20:08:20 -03:00
AOpCodeTable.cs Add FCVTAS and FCVTAU instructions 2018-02-17 18:59:37 -03:00
AOptimizations.cs Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions 2018-02-09 00:26:20 -03:00
AThread.cs Add some tests (#18) 2018-02-15 21:04:38 -03:00
ATranslatedSub.cs aloha 2018-02-04 20:08:20 -03:00
ATranslator.cs aloha 2018-02-04 20:08:20 -03:00