0
0
Fork 0
This repository has been archived on 2024-10-12. You can view files and clone it, but cannot push or open issues or pull requests.
ryujinx-final/ARMeilleure/Translation/PTC
Wunk 45ce540b9b
ARMeilleure: Add gfni acceleration (#3669)
* ARMeilleure: Add `GFNI` detection

This is intended for utilizing the `gf2p8affineqb` instruction

* ARMeilleure: Add `gf2p8affineqb`

Not using the VEX or EVEX-form of this instruction is intentional. There
are `GFNI`-chips that do not support AVX(so no VEX encoding) such as
Tremont(Lakefield) chips as well as Jasper Lake.

13df339fe7/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt (L1297-L1299)

13df339fe7/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt (L1252-L1254)

* ARMeilleure: Add `gfni` acceleration of `Rbit_V`

Passes all `Rbit_V*` unit tests on my `i9-11900k`

* ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V`

Also added a fast-path for when the shift amount is greater than the
size of the element.

* ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V`

* ARMeilleure: Increment InternalVersion

* ARMeilleure: Fix Intrinsic and Assembler Table alignment

`gf2p8affineqb` is the longest instruction name I know of. It shouldn't
get any wider than this.

* ARMeilleure: Remove SSE2+SHA requirement for GFNI

* ARMeilleure Add `X86GetGf2p8LogicalShiftLeft`

Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction.

* ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`
2022-10-02 11:17:19 +02:00
..
EncodingCache.cs PPTC vs. giant ExeFS. (#2168) 2021-04-13 03:24:36 +02:00
Ptc.cs ARMeilleure: Add gfni acceleration (#3669) 2022-10-02 11:17:19 +02:00
PtcFormatter.cs PPTC meets ExeFS Patching. (#1865) 2021-05-13 20:05:15 +02:00
PtcLoadingState.cs Fix inconsistencies in progress reporting (#2129) 2021-03-22 19:40:07 +01:00
PtcProfiler.cs Enable CPU JIT cache invalidation (#2965) 2022-02-18 02:53:18 +01:00
PtcState.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00