c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
57 lines
No EOL
1.4 KiB
C#
57 lines
No EOL
1.4 KiB
C#
using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCode32MemMult : OpCode32, IOpCode32MemMult
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{
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public int Rn { get; private set; }
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public int RegisterMask { get; private set; }
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public int Offset { get; private set; }
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public int PostOffset { get; private set; }
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public bool IsLoad { get; private set; }
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public OpCode32MemMult(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Rn = (opCode >> 16) & 0xf;
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bool isLoad = (opCode & (1 << 20)) != 0;
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bool w = (opCode & (1 << 21)) != 0;
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bool u = (opCode & (1 << 23)) != 0;
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bool p = (opCode & (1 << 24)) != 0;
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RegisterMask = opCode & 0xffff;
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int regsSize = 0;
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for (int index = 0; index < 16; index++)
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{
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regsSize += (RegisterMask >> index) & 1;
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}
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regsSize *= 4;
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if (!u)
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{
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Offset -= regsSize;
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}
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if (u == p)
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{
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Offset += 4;
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}
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if (w)
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{
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PostOffset = u ? regsSize : -regsSize;
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}
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else
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{
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PostOffset = 0;
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}
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IsLoad = isLoad;
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}
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}
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} |