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riperiperi 9ef94c8292 ARMeilleure: Move TPIDR_EL0 and TPIDRRO_EL0 to NativeContext (#4661) ... * ARMeilleure: Move TPIDR_EL0 and TPIDRRO_EL0 to NativeContext Some games access these system registers several tens of thousands of times in a second from many different threads. While this isn't really crippling, it is a lot of wasted time spent in a reverse pinvoke transition. Example games are Pokemon Scarlet/Violet and BOTW. These games have a lot of different potential bottlenecks so it's unlikely you will see a consistent improvement, but it definitely disappears from the cpu profile. * Remove unreachable code. * Add ulong conversion for offsets * Nit		2023-04-11 08:55:04 +02:00
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Aarch32Mode.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
ExceptionCallback.cs	Refactor CPU interface to allow the implementation of other CPU emulators (#3362)	2022-05-31 16:29:35 -03:00
ExecutionContext.cs	ARMeilleure: Move TPIDR_EL0 and TPIDRRO_EL0 to NativeContext (#4661)	2023-04-11 08:55:04 +02:00
ExecutionMode.cs	PPTC & Pool Enhancements. (#1968)	2021-02-22 03:23:48 +01:00
FPCR.cs	Fpsr and Fpcr freed. (#3701)	2022-09-20 18:55:13 -03:00
FPException.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
FPRoundingMode.cs	A64: Add fast path for Fcvtas_Gp/S/V, Fcvtau_Gp/S/V and Frinta_S/V in… (#3712)	2022-10-19 00:21:33 +00:00
FPSCR.cs	Fpsr and Fpcr freed. (#3701)	2022-09-20 18:55:13 -03:00
FPSR.cs	Fpsr and Fpcr freed. (#3701)	2022-09-20 18:55:13 -03:00
FPState.cs	Fpsr and Fpcr freed. (#3701)	2022-09-20 18:55:13 -03:00
FPType.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
ICounter.cs	Refactor CPU interface to allow the implementation of other CPU emulators (#3362)	2022-05-31 16:29:35 -03:00
NativeContext.cs	ARMeilleure: Move TPIDR_EL0 and TPIDRRO_EL0 to NativeContext (#4661)	2023-04-11 08:55:04 +02:00
PState.cs	Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)	2022-09-13 19:51:40 -03:00
RegisterAlias.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
RegisterConsts.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
V128.cs	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00