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gdkchan 8e119a1e96 Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)		2022-09-13 19:51:40 -03:00
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Aarch32Mode.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
ExceptionCallback.cs	Refactor CPU interface to allow the implementation of other CPU emulators (#3362)	2022-05-31 16:29:35 -03:00
ExecutionContext.cs	Refactor CPU interface to allow the implementation of other CPU emulators (#3362)	2022-05-31 16:29:35 -03:00
ExecutionMode.cs	PPTC & Pool Enhancements. (#1968)	2021-02-22 03:23:48 +01:00
FPCR.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
FPException.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
FPRoundingMode.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
FPSR.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
FPState.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
FPType.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
ICounter.cs	Refactor CPU interface to allow the implementation of other CPU emulators (#3362)	2022-05-31 16:29:35 -03:00
NativeContext.cs	Refactor CPU interface to allow the implementation of other CPU emulators (#3362)	2022-05-31 16:29:35 -03:00
PState.cs	Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)	2022-09-13 19:51:40 -03:00
RegisterAlias.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
RegisterConsts.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
V128.cs	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00