22b2cb39af
* Turn `MemoryOperand` into a struct
* Remove `IntrinsicOperation`
* Remove `PhiNode`
* Remove `Node`
* Turn `Operand` into a struct
* Turn `Operation` into a struct
* Clean up pool management methods
* Add `Arena` allocator
* Move `OperationHelper` to `Operation.Factory`
* Move `OperandHelper` to `Operand.Factory`
* Optimize `Operation` a bit
* Fix `Arena` initialization
* Rename `NativeList<T>` to `ArenaList<T>`
* Reduce `Operand` size from 88 to 56 bytes
* Reduce `Operation` size from 56 to 40 bytes
* Add optimistic interning of Register & Constant operands
* Optimize `RegisterUsage` pass a bit
* Optimize `RemoveUnusedNodes` pass a bit
Iterating in reverse-order allows killing dependency chains in a single
pass.
* Fix PPTC symbols
* Optimize `BasicBlock` a bit
Reduce allocations from `_successor` & `DominanceFrontiers`
* Fix `Operation` resize
* Make `Arena` expandable
Change the arena allocator to be expandable by allocating in pages, with
some of them being pooled. Currently 32 pages are pooled. An LRU removal
mechanism should probably be added to it.
Apparently MHR can allocate bitmaps large enough to exceed the 16MB
limit for the type.
* Move `Arena` & `ArenaList` to `Common`
* Remove `ThreadStaticPool` & co
* Add `PhiOperation`
* Reduce `Operand` size from 56 from 48 bytes
* Add linear-probing to `Operand` intern table
* Optimize `HybridAllocator` a bit
* Add `Allocators` class
* Tune `ArenaAllocator` sizes
* Add page removal mechanism to `ArenaAllocator`
Remove pages which have not been used for more than 5s after each reset.
I am on fence if this would be better using a Gen2 callback object like
the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right
now if a large translation happens, the pages will be freed only after a
reset. This reset may not happen for a while because no new translation
is hit, but the arena base sizes are rather small.
* Fix `OOM` when allocating larger than page size in `ArenaAllocator`
Tweak resizing mechanism for Operand.Uses and Assignemnts.
* Optimize `Optimizer` a bit
* Optimize `Operand.Add<T>/Remove<T>` a bit
* Clean up `PreAllocator`
* Fix phi insertion order
Reduce codegen diffs.
* Fix code alignment
* Use new heuristics for degree of parallelism
* Suppress warnings
* Address gdkchan's feedback
Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that
`Operand.Value` should usually not be modified directly.
* Add fast path to `ArenaAllocator`
* Assembly for `ArenaAllocator.Allocate(ulong)`:
.L0:
mov rax, [rcx+0x18]
lea r8, [rax+rdx]
cmp r8, [rcx+0x10]
ja short .L2
.L1:
mov rdx, [rcx+8]
add rax, [rdx+8]
mov [rcx+0x18], r8
ret
.L2:
jmp ArenaAllocator.AllocateSlow(UInt64)
A few variable/field had to be changed to ulong so that RyuJIT avoids
emitting zero-extends.
* Implement a new heuristic to free pooled pages.
If an arena is used often, it is more likely that its pages will be
needed, so the pages are kept for longer (e.g: during PPTC rebuild or
burst sof compilations). If is not used often, then it is more likely
that its pages will not be needed (e.g: after PPTC rebuild or bursts
of compilations).
* Address riperiperi's feedback
* Use `EqualityComparer<T>` in `IntrusiveList<T>`
Avoids a potential GC hole in `Equals(T, T)`.
785 lines
25 KiB
C#
785 lines
25 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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using Func2I = Func<Operand, Operand, Operand>;
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static partial class InstEmit
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{
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public static void Cmeq_S(ArmEmitterContext context)
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareEqual(op1, op2), scalar: true);
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}
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public static void Cmeq_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m;
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if (op is OpCodeSimdReg binOp)
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{
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m = GetVec(binOp.Rm);
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}
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else
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{
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m = context.VectorZero();
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}
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Intrinsic cmpInst = X86PcmpeqInstruction[op.Size];
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Operand res = context.AddIntrinsic(cmpInst, n, m);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareEqual(op1, op2), scalar: false);
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}
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}
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public static void Cmge_S(ArmEmitterContext context)
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareGreaterOrEqual(op1, op2), scalar: true);
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}
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public static void Cmge_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse42)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m;
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if (op is OpCodeSimdReg binOp)
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{
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m = GetVec(binOp.Rm);
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}
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else
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{
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m = context.VectorZero();
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}
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Intrinsic cmpInst = X86PcmpgtInstruction[op.Size];
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Operand res = context.AddIntrinsic(cmpInst, m, n);
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Operand mask = X86GetAllElements(context, -1L);
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res = context.AddIntrinsic(Intrinsic.X86Pandn, res, mask);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareGreaterOrEqual(op1, op2), scalar: false);
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}
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}
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public static void Cmgt_S(ArmEmitterContext context)
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareGreater(op1, op2), scalar: true);
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}
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public static void Cmgt_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse42)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m;
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if (op is OpCodeSimdReg binOp)
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{
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m = GetVec(binOp.Rm);
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}
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else
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{
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m = context.VectorZero();
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}
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Intrinsic cmpInst = X86PcmpgtInstruction[op.Size];
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Operand res = context.AddIntrinsic(cmpInst, n, m);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareGreater(op1, op2), scalar: false);
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}
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}
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public static void Cmhi_S(ArmEmitterContext context)
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareGreaterUI(op1, op2), scalar: true);
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}
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public static void Cmhi_V(ArmEmitterContext context)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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if (Optimizations.UseSse41 && op.Size < 3)
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{
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Intrinsic maxInst = X86PmaxuInstruction[op.Size];
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Operand res = context.AddIntrinsic(maxInst, m, n);
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Intrinsic cmpInst = X86PcmpeqInstruction[op.Size];
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res = context.AddIntrinsic(cmpInst, res, m);
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Operand mask = X86GetAllElements(context, -1L);
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res = context.AddIntrinsic(Intrinsic.X86Pandn, res, mask);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareGreaterUI(op1, op2), scalar: false);
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}
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}
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public static void Cmhs_S(ArmEmitterContext context)
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareGreaterOrEqualUI(op1, op2), scalar: true);
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}
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public static void Cmhs_V(ArmEmitterContext context)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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if (Optimizations.UseSse41 && op.Size < 3)
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{
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Intrinsic maxInst = X86PmaxuInstruction[op.Size];
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Operand res = context.AddIntrinsic(maxInst, n, m);
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Intrinsic cmpInst = X86PcmpeqInstruction[op.Size];
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res = context.AddIntrinsic(cmpInst, res, n);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareGreaterOrEqualUI(op1, op2), scalar: false);
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}
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}
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public static void Cmle_S(ArmEmitterContext context)
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareLessOrEqual(op1, op2), scalar: true);
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}
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public static void Cmle_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse42)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Intrinsic cmpInst = X86PcmpgtInstruction[op.Size];
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Operand res = context.AddIntrinsic(cmpInst, n, context.VectorZero());
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Operand mask = X86GetAllElements(context, -1L);
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res = context.AddIntrinsic(Intrinsic.X86Pandn, res, mask);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareLessOrEqual(op1, op2), scalar: false);
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}
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}
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public static void Cmlt_S(ArmEmitterContext context)
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareLess(op1, op2), scalar: true);
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}
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public static void Cmlt_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse42)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Intrinsic cmpInst = X86PcmpgtInstruction[op.Size];
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Operand res = context.AddIntrinsic(cmpInst, context.VectorZero(), n);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitCmpOp(context, (op1, op2) => context.ICompareLess(op1, op2), scalar: false);
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}
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}
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public static void Cmtst_S(ArmEmitterContext context)
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{
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EmitCmtstOp(context, scalar: true);
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}
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public static void Cmtst_V(ArmEmitterContext context)
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{
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EmitCmtstOp(context, scalar: false);
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}
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public static void Facge_S(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.GreaterThanOrEqual, scalar: true, absolute: true);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareGE), scalar: true, absolute: true);
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}
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}
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public static void Facge_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.GreaterThanOrEqual, scalar: false, absolute: true);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareGE), scalar: false, absolute: true);
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}
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}
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public static void Facgt_S(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.GreaterThan, scalar: true, absolute: true);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareGT), scalar: true, absolute: true);
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}
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}
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public static void Facgt_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.GreaterThan, scalar: false, absolute: true);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareGT), scalar: false, absolute: true);
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}
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}
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public static void Fccmp_S(ArmEmitterContext context)
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{
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EmitFccmpOrFccmpe(context, signalNaNs: false);
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}
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public static void Fccmpe_S(ArmEmitterContext context)
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{
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EmitFccmpOrFccmpe(context, signalNaNs: true);
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}
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public static void Fcmeq_S(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.Equal, scalar: true);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareEQ), scalar: true);
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}
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}
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public static void Fcmeq_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.Equal, scalar: false);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareEQ), scalar: false);
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}
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}
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public static void Fcmge_S(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.GreaterThanOrEqual, scalar: true);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareGE), scalar: true);
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}
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}
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public static void Fcmge_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.GreaterThanOrEqual, scalar: false);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareGE), scalar: false);
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}
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}
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public static void Fcmgt_S(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.GreaterThan, scalar: true);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareGT), scalar: true);
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}
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}
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public static void Fcmgt_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.GreaterThan, scalar: false);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareGT), scalar: false);
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}
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}
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public static void Fcmle_S(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.LessThanOrEqual, scalar: true);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareLE), scalar: true);
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}
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}
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public static void Fcmle_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.LessThanOrEqual, scalar: false);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareLE), scalar: false);
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}
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}
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public static void Fcmlt_S(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.LessThan, scalar: true);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareLT), scalar: true);
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}
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}
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public static void Fcmlt_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF(context, CmpCondition.LessThan, scalar: false);
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}
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else
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{
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EmitCmpOpF(context, nameof(SoftFloat32.FPCompareLT), scalar: false);
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}
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}
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public static void Fcmp_S(ArmEmitterContext context)
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{
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EmitFcmpOrFcmpe(context, signalNaNs: false);
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}
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public static void Fcmpe_S(ArmEmitterContext context)
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{
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EmitFcmpOrFcmpe(context, signalNaNs: true);
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}
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private static void EmitFccmpOrFccmpe(ArmEmitterContext context, bool signalNaNs)
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{
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OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp;
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Operand lblTrue = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblTrue, InstEmitFlowHelper.GetCondTrue(context, op.Cond));
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EmitSetNzcv(context, op.Nzcv);
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context.Branch(lblEnd);
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context.MarkLabel(lblTrue);
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EmitFcmpOrFcmpe(context, signalNaNs);
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context.MarkLabel(lblEnd);
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}
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private static void EmitSetNzcv(ArmEmitterContext context, int nzcv)
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{
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Operand Extract(int value, int bit)
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{
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if (bit != 0)
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{
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value >>= bit;
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}
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value &= 1;
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return Const(value);
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}
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SetFlag(context, PState.VFlag, Extract(nzcv, 0));
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SetFlag(context, PState.CFlag, Extract(nzcv, 1));
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SetFlag(context, PState.ZFlag, Extract(nzcv, 2));
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SetFlag(context, PState.NFlag, Extract(nzcv, 3));
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}
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private static void EmitFcmpOrFcmpe(ArmEmitterContext context, bool signalNaNs)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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bool cmpWithZero = !(op is OpCodeSimdFcond) ? op.Bit3 : false;
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if (Optimizations.FastFP && (signalNaNs ? Optimizations.UseAvx : Optimizations.UseSse2))
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{
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Operand n = GetVec(op.Rn);
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Operand m = cmpWithZero ? context.VectorZero() : GetVec(op.Rm);
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CmpCondition cmpOrdered = signalNaNs ? CmpCondition.OrderedS : CmpCondition.OrderedQ;
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Operand lblNaN = Label();
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Operand lblEnd = Label();
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if (op.Size == 0)
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{
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Operand ordMask = context.AddIntrinsic(Intrinsic.X86Cmpss, n, m, Const((int)cmpOrdered));
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Operand isOrdered = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, ordMask);
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context.BranchIfFalse(lblNaN, isOrdered);
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Operand nCopy = context.Copy(n);
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Operand mCopy = cmpWithZero ? context.VectorZero() : context.Copy(m);
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Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comissge, nCopy, mCopy);
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Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisseq, nCopy, mCopy);
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Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisslt, nCopy, mCopy);
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SetFlag(context, PState.VFlag, Const(0));
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SetFlag(context, PState.CFlag, cf);
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SetFlag(context, PState.ZFlag, zf);
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SetFlag(context, PState.NFlag, nf);
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}
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else /* if (op.Size == 1) */
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{
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Operand ordMask = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, m, Const((int)cmpOrdered));
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Operand isOrdered = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, ordMask);
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context.BranchIfFalse(lblNaN, isOrdered);
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Operand nCopy = context.Copy(n);
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Operand mCopy = cmpWithZero ? context.VectorZero() : context.Copy(m);
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Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comisdge, nCopy, mCopy);
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Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisdeq, nCopy, mCopy);
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Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisdlt, nCopy, mCopy);
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SetFlag(context, PState.VFlag, Const(0));
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SetFlag(context, PState.CFlag, cf);
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SetFlag(context, PState.ZFlag, zf);
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SetFlag(context, PState.NFlag, nf);
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}
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context.Branch(lblEnd);
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context.MarkLabel(lblNaN);
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SetFlag(context, PState.VFlag, Const(1));
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SetFlag(context, PState.CFlag, Const(1));
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SetFlag(context, PState.ZFlag, Const(0));
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SetFlag(context, PState.NFlag, Const(0));
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context.MarkLabel(lblEnd);
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}
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else
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{
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OperandType type = op.Size != 0 ? OperandType.FP64 : OperandType.FP32;
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Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
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Operand me;
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if (cmpWithZero)
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{
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me = op.Size == 0 ? ConstF(0f) : ConstF(0d);
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}
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else
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{
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me = context.VectorExtract(type, GetVec(op.Rm), 0);
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}
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Operand nzcv = EmitSoftFloatCall(context, nameof(SoftFloat32.FPCompare), ne, me, Const(signalNaNs));
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EmitSetNzcv(context, nzcv);
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}
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}
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private static void EmitSetNzcv(ArmEmitterContext context, Operand nzcv)
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|
{
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Operand Extract(Operand value, int bit)
|
|
{
|
|
if (bit != 0)
|
|
{
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value = context.ShiftRightUI(value, Const(bit));
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}
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value = context.BitwiseAnd(value, Const(1));
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return value;
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}
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SetFlag(context, PState.VFlag, Extract(nzcv, 0));
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SetFlag(context, PState.CFlag, Extract(nzcv, 1));
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SetFlag(context, PState.ZFlag, Extract(nzcv, 2));
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SetFlag(context, PState.NFlag, Extract(nzcv, 3));
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}
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private static void EmitCmpOp(ArmEmitterContext context, Func2I emitCmp, bool scalar)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand res = context.VectorZero();
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int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
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ulong szMask = ulong.MaxValue >> (64 - (8 << op.Size));
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
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Operand me;
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if (op is OpCodeSimdReg binOp)
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{
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me = EmitVectorExtractSx(context, binOp.Rm, index, op.Size);
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}
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else
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{
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me = Const(0L);
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}
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Operand isTrue = emitCmp(ne, me);
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Operand mask = context.ConditionalSelect(isTrue, Const(szMask), Const(0L));
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res = EmitVectorInsert(context, res, mask, index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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private static void EmitCmtstOp(ArmEmitterContext context, bool scalar)
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|
{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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|
Operand res = context.VectorZero();
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|
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|
int elems = !scalar ? op.GetBytesCount() >> op.Size : 1;
|
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|
|
ulong szMask = ulong.MaxValue >> (64 - (8 << op.Size));
|
|
|
|
for (int index = 0; index < elems; index++)
|
|
{
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
|
|
Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
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|
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|
Operand test = context.BitwiseAnd(ne, me);
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|
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|
Operand isTrue = context.ICompareNotEqual(test, Const(0L));
|
|
|
|
Operand mask = context.ConditionalSelect(isTrue, Const(szMask), Const(0L));
|
|
|
|
res = EmitVectorInsert(context, res, mask, index, op.Size);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
|
|
private static void EmitCmpOpF(ArmEmitterContext context, string name, bool scalar, bool absolute = false)
|
|
{
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
|
|
|
Operand res = context.VectorZero();
|
|
|
|
int sizeF = op.Size & 1;
|
|
|
|
OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
|
|
|
|
int elems = !scalar ? op.GetBytesCount() >> sizeF + 2 : 1;
|
|
|
|
for (int index = 0; index < elems; index++)
|
|
{
|
|
Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
|
|
Operand me;
|
|
|
|
if (op is OpCodeSimdReg binOp)
|
|
{
|
|
me = context.VectorExtract(type, GetVec(binOp.Rm), index);
|
|
}
|
|
else
|
|
{
|
|
me = sizeF == 0 ? ConstF(0f) : ConstF(0d);
|
|
}
|
|
|
|
if (absolute)
|
|
{
|
|
ne = EmitUnaryMathCall(context, nameof(Math.Abs), ne);
|
|
me = EmitUnaryMathCall(context, nameof(Math.Abs), me);
|
|
}
|
|
|
|
Operand e = EmitSoftFloatCall(context, name, ne, me);
|
|
|
|
res = context.VectorInsert(res, e, index);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
|
|
private static void EmitSse2OrAvxCmpOpF(ArmEmitterContext context, CmpCondition cond, bool scalar, bool absolute = false)
|
|
{
|
|
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
|
|
|
Operand n = GetVec(op.Rn);
|
|
Operand m = op is OpCodeSimdReg binOp ? GetVec(binOp.Rm) : context.VectorZero();
|
|
|
|
int sizeF = op.Size & 1;
|
|
|
|
if (sizeF == 0)
|
|
{
|
|
if (absolute)
|
|
{
|
|
Operand mask = scalar ? X86GetScalar(context, int.MaxValue) : X86GetAllElements(context, int.MaxValue);
|
|
|
|
n = context.AddIntrinsic(Intrinsic.X86Andps, n, mask);
|
|
m = context.AddIntrinsic(Intrinsic.X86Andps, m, mask);
|
|
}
|
|
|
|
Intrinsic inst = scalar ? Intrinsic.X86Cmpss : Intrinsic.X86Cmpps;
|
|
|
|
Operand res = context.AddIntrinsic(inst, n, m, Const((int)cond));
|
|
|
|
if (scalar)
|
|
{
|
|
res = context.VectorZeroUpper96(res);
|
|
}
|
|
else if (op.RegisterSize == RegisterSize.Simd64)
|
|
{
|
|
res = context.VectorZeroUpper64(res);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
else /* if (sizeF == 1) */
|
|
{
|
|
if (absolute)
|
|
{
|
|
Operand mask = scalar ? X86GetScalar(context, long.MaxValue) : X86GetAllElements(context, long.MaxValue);
|
|
|
|
n = context.AddIntrinsic(Intrinsic.X86Andpd, n, mask);
|
|
m = context.AddIntrinsic(Intrinsic.X86Andpd, m, mask);
|
|
}
|
|
|
|
Intrinsic inst = scalar ? Intrinsic.X86Cmpsd : Intrinsic.X86Cmppd;
|
|
|
|
Operand res = context.AddIntrinsic(inst, n, m, Const((int)cond));
|
|
|
|
if (scalar)
|
|
{
|
|
res = context.VectorZeroUpper64(res);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
}
|
|
}
|