894459fcd7
* Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs * Update ASoftFallback.cs * Update ASoftFloat.cs * Update AOpCodeSimdRegElemF.cs * Update CpuTestSimdIns.cs * Update CpuTestSimdRegElem.cs * Create CpuTestSimdRegElemF.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Superseded Fmul_Se Test. Nit. * Address PR feedback. * Address PR feedback. * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update AInstEmitSimdShift.cs
110 lines
4 KiB
C#
110 lines
4 KiB
C#
#define SimdRegElem
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using ChocolArm64.State;
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using NUnit.Framework;
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using System.Runtime.Intrinsics;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdRegElem")] // Tested: second half of 2018.
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public sealed class CpuTestSimdRegElem : CpuTest
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{
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#if SimdRegElem
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#region "ValueSource (Types)"
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private static ulong[] _2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _Mla_Mls_Mul_Ve_4H_8H_()
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{
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return new uint[]
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{
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0x2F400000u, // MLA V0.4H, V0.4H, V0.H[0]
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0x2F404000u, // MLS V0.4H, V0.4H, V0.H[0]
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0x0F408000u // MUL V0.4H, V0.4H, V0.H[0]
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};
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}
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private static uint[] _Mla_Mls_Mul_Ve_2S_4S_()
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{
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return new uint[]
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{
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0x2F800000u, // MLA V0.2S, V0.2S, V0.S[0]
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0x2F804000u, // MLS V0.2S, V0.2S, V0.S[0]
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0x0F808000u // MUL V0.2S, V0.2S, V0.S[0]
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};
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}
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#endregion
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private const int RndCnt = 2;
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[Test, Pairwise]
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public void Mla_Mls_Mul_Ve_4H_8H([ValueSource("_Mla_Mls_Mul_Ve_4H_8H_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(2u, 0u)] uint Rm,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong A,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong B,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index,
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[Values(0b0u, 0b1u)] uint Q) // <4H, 8H>
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{
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uint H = (Index >> 2) & 1;
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uint L = (Index >> 1) & 1;
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uint M = Index & 1;
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Opcodes |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcodes |= (L << 21) | (M << 20) | (H << 11);
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Opcodes |= ((Q & 1) << 30);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
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Vector128<float> V2 = MakeVectorE0E1(B, B * H);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Mla_Mls_Mul_Ve_2S_4S([ValueSource("_Mla_Mls_Mul_Ve_2S_4S_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(2u, 0u)] uint Rm,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong A,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong B,
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[Values(0u, 1u, 2u, 3u)] uint Index,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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{
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uint H = (Index >> 1) & 1;
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uint L = Index & 1;
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Opcodes |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcodes |= (L << 21) | (H << 11);
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Opcodes |= ((Q & 1) << 30);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
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Vector128<float> V2 = MakeVectorE0E1(B, B * H);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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