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sharmander e901b7850c CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776) ... * Start implementation * Draft * Updated opcode. Needs verification. * Clean up code. * Update implementation and tests. * Update implemenation + tests * Get RM from FPSCR + Do not use emit/addintrinsic * Remove "fast" path, as recommended by gdk. * Variable DELETED. * Update ARMeilleure/Decoders/OpCodeTable.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Move method * stringing things together :) Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>		2020-12-16 20:27:15 -03:00
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CpuTest.cs	Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). (#1630)	2020-12-07 10:37:07 +01:00
CpuTest32.cs	shader cache: Fix Linux boot issues (#1709)	2020-11-17 22:40:19 +01:00
CpuTestAlu.cs	Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)	2019-06-12 09:03:31 -03:00
CpuTestAlu32.cs	Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)	2020-03-01 07:51:55 +11:00
CpuTestAluBinary.cs	Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)	2020-07-13 20:48:14 +10:00
CpuTestAluBinary32.cs	Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)	2020-07-13 20:48:14 +10:00
CpuTestAluImm.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestAluRs.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestAluRs32.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
CpuTestAluRx.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestBf32.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
CpuTestBfm.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestCcmpImm.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestCcmpReg.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestCsel.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestMisc.cs	Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)	2020-07-13 21:08:47 +10:00
CpuTestMisc32.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
CpuTestMov.cs	Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)	2019-06-12 09:03:31 -03:00
CpuTestMul.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestMul32.cs	Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)	2020-03-01 07:51:55 +11:00
CpuTestSimd.cs	CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Now HardwareCapabilities uses CpuId. (#1650)	2020-11-18 19:35:54 +01:00
CpuTestSimd32.cs	CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394)	2020-07-17 10:57:49 -03:00
CpuTestSimdCrypto.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdCrypto32.cs	Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)	2020-03-14 10:29:58 +11:00
CpuTestSimdCvt.cs	Implemented fast paths for: (#846)	2019-12-29 22:22:47 -03:00
CpuTestSimdCvt32.cs	CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)	2020-12-16 20:27:15 -03:00
CpuTestSimdExt.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdFcond.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdFmov.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdImm.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdIns.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdLogical32.cs	Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)	2020-07-19 15:11:58 -03:00
CpuTestSimdMemory32.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
CpuTestSimdMov32.cs	Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303)	2020-06-24 10:43:44 +10:00
CpuTestSimdReg.cs	Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)	2020-07-13 21:08:47 +10:00
CpuTestSimdReg32.cs	CPU: Implement VFMA (Vector) (#1762)	2020-12-15 00:01:52 -03:00
CpuTestSimdRegElem.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdRegElem32.cs	Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)	2020-03-11 11:49:27 +11:00
CpuTestSimdRegElemF.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdShImm.cs	CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)	2020-08-31 20:48:21 -03:00
CpuTestSimdShImm32.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
CpuTestSimdTbl.cs	Add Tbx Inst. (fast & slow paths), with Tests. (#782)	2019-10-04 11:43:20 -03:00
CpuTestSystem.cs	Add Mrs & Msr (Nzcv) Inst., with Tests. (#819)	2019-11-14 13:08:07 +11:00