Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
* Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths).
No test provided (i.e. draft).
* Ptc InternalVersion = 1577
2020-10-13 20:41:33 +00:00
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namespace ARMeilleure.Decoders
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{
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class OpCode32SimdShImmLong : OpCode32Simd
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{
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2020-10-21 12:13:44 +00:00
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public int Shift { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode);
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Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
* Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths).
No test provided (i.e. draft).
* Ptc InternalVersion = 1577
2020-10-13 20:41:33 +00:00
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public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Q = false;
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RegisterSize = RegisterSize.Simd64;
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int imm6 = (opCode >> 16) & 0x3f;
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if ((imm6 & 0x20) == 0b100000)
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{
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Size = 2;
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Shift = imm6 - 32;
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}
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else if ((imm6 & 0x30) == 0b010000)
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{
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Size = 1;
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Shift = imm6 - 16;
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}
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else if ((imm6 & 0x38) == 0b001000)
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{
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Size = 0;
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Shift = imm6 - 8;
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}
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else
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{
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Instruction = InstDescriptor.Undefined;
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}
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if (GetType() == typeof(OpCode32SimdShImmLong) && DecoderHelper.VectorArgumentsInvalid(true, Vd))
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{
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Instruction = InstDescriptor.Undefined;
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}
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}
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}
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}
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