From 302c1d2861a6c730a0c8c19622ea58ac16e1d4f1 Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Sat, 21 Apr 2018 21:15:04 +0200 Subject: [PATCH] Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. (#96) * Update AOpCodeTable.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update Instructions.cs * Revert "Started to work in improving the sync primitives" --- ChocolArm64/AOpCodeTable.cs | 2 +- Ryujinx.Tests/Cpu/CpuTestSimd.cs | 92 +++++++++++++-- Ryujinx.Tests/Cpu/CpuTestSimdReg.cs | 144 +++++++++++++++-------- Ryujinx.Tests/Cpu/Tester/Instructions.cs | 82 +++++++++++++ Ryujinx.Tests/Cpu/Tester/Pseudocode.cs | 50 ++++++++ 5 files changed, 314 insertions(+), 56 deletions(-) diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index 154affec..4dc15754 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -138,7 +138,7 @@ namespace ChocolArm64 Set("01011110111xxxxx100001xxxxxxxxxx", AInstEmit.Add_S, typeof(AOpCodeSimdReg)); Set("0>001110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Add_V, typeof(AOpCodeSimdReg)); Set("0x001110<<1xxxxx010000xxxxxxxxxx", AInstEmit.Addhn_V, typeof(AOpCodeSimdReg)); - Set("01011110xx110001101110xxxxxxxxxx", AInstEmit.Addp_S, typeof(AOpCodeSimd)); + Set("0101111011110001101110xxxxxxxxxx", AInstEmit.Addp_S, typeof(AOpCodeSimd)); Set("0>001110<<1xxxxx101111xxxxxxxxxx", AInstEmit.Addp_V, typeof(AOpCodeSimdReg)); Set("000011100x110001101110xxxxxxxxxx", AInstEmit.Addv_V, typeof(AOpCodeSimd)); Set("01001110<<110001101110xxxxxxxxxx", AInstEmit.Addv_V, typeof(AOpCodeSimd)); diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs index 9107a8f8..5fa3a72d 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -20,12 +20,19 @@ namespace Ryujinx.Tests.Cpu } #region "ValueSource" - private static ulong[] _D_() + private static ulong[] _1D_() { return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; } + private static ulong[] _8B4H_() + { + return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, + 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul }; + } + private static ulong[] _8B4H2S_() { return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, @@ -34,7 +41,7 @@ namespace Ryujinx.Tests.Cpu 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; } - private static ulong[] _16B8H4S2D_() + private static ulong[] _8B4H2S1D_() { return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, @@ -45,7 +52,7 @@ namespace Ryujinx.Tests.Cpu #endregion [Test, Description("ABS , ")] - public void Abs_S_D([ValueSource("_D_")] [Random(1)] ulong A) + public void Abs_S_D([ValueSource("_1D_")] [Random(1)] ulong A) { uint Opcode = 0x5EE0B820; // ABS D0, D1 Bits Op = new Bits(Opcode); @@ -81,8 +88,8 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ABS ., .")] - public void Abs_V_16B_8H_4S_2D([ValueSource("_16B8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_16B8H4S2D_")] [Random(1)] ulong A1, + public void Abs_V_16B_8H_4S_2D([ValueSource("_8B4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong A1, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { uint Opcode = 0x4E20B820; // ABS V0.16B, V1.16B @@ -103,8 +110,77 @@ namespace Ryujinx.Tests.Cpu }); } + [Test, Pairwise, Description("ADDP , .")] + public void Addp_S_2DD([ValueSource("_1D_")] [Random(1)] ulong A0, + [ValueSource("_1D_")] [Random(1)] ulong A1) + { + uint Opcode = 0x5EF1B820; // ADDP D0, V1.2D + Bits Op = new Bits(Opcode); + + AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() }; + AVec V1 = new AVec { X0 = A0, X1 = A1 }; + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + AArch64.Vpart(1, 0, new Bits(A0)); + AArch64.Vpart(1, 1, new Bits(A1)); + SimdFp.Addp_S(Op[23, 22], Op[9, 5], Op[4, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64())); + Assert.That(ThreadState.V0.X1, Is.Zero); + }); + } + + [Test, Description("ADDV , .")] + public void Addv_V_8BB_4HH([ValueSource("_8B4H_")] [Random(1)] ulong A, + [Values(0b00u, 0b01u)] uint size) // <8B, 4H> + { + uint Opcode = 0x0E31B820; // ADDV B0, V1.8B + Opcode |= ((size & 3) << 22); + Bits Op = new Bits(Opcode); + + AVec V0 = new AVec { X0 = TestContext.CurrentContext.Random.NextULong(), + X1 = TestContext.CurrentContext.Random.NextULong() }; + AVec V1 = new AVec { X0 = A }; + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + AArch64.Vpart(0, 0, new Bits(TestContext.CurrentContext.Random.NextULong())); + AArch64.V(1, new Bits(A)); + SimdFp.Addv_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); + + Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64())); + Assert.That(ThreadState.V0.X1, Is.Zero); + } + + [Test, Pairwise, Description("ADDV , .")] + public void Addv_V_16BB_8HH_4SS([ValueSource("_8B4H2S_")] [Random(1)] ulong A0, + [ValueSource("_8B4H2S_")] [Random(1)] ulong A1, + [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S> + { + uint Opcode = 0x4E31B820; // ADDV B0, V1.16B + Opcode |= ((size & 3) << 22); + Bits Op = new Bits(Opcode); + + AVec V0 = new AVec { X0 = TestContext.CurrentContext.Random.NextULong(), + X1 = TestContext.CurrentContext.Random.NextULong() }; + AVec V1 = new AVec { X0 = A0, X1 = A1 }; + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + AArch64.Vpart(0, 0, new Bits(TestContext.CurrentContext.Random.NextULong())); + AArch64.Vpart(1, 0, new Bits(A0)); + AArch64.Vpart(1, 1, new Bits(A1)); + SimdFp.Addv_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64())); + Assert.That(ThreadState.V0.X1, Is.Zero); + }); + } + [Test, Description("NEG , ")] - public void Neg_S_D([ValueSource("_D_")] [Random(1)] ulong A) + public void Neg_S_D([ValueSource("_1D_")] [Random(1)] ulong A) { uint Opcode = 0x7EE0B820; // NEG D0, D1 Bits Op = new Bits(Opcode); @@ -140,8 +216,8 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("NEG ., .")] - public void Neg_V_16B_8H_4S_2D([ValueSource("_16B8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_16B8H4S2D_")] [Random(1)] ulong A1, + public void Neg_V_16B_8H_4S_2D([ValueSource("_8B4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong A1, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { uint Opcode = 0x6E20B820; // NEG V0.16B, V1.16B diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs index 04cef60f..8c13c33a 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs @@ -20,7 +20,7 @@ namespace Ryujinx.Tests.Cpu } #region "ValueSource" - private static ulong[] _D_() + private static ulong[] _1D_() { return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; @@ -34,7 +34,7 @@ namespace Ryujinx.Tests.Cpu 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; } - private static ulong[] _16B8H4S2D_() + private static ulong[] _8B4H2S1D_() { return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, @@ -43,7 +43,7 @@ namespace Ryujinx.Tests.Cpu 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; } - private static ulong[] _8H4S2D_() + private static ulong[] _4H2S1D_() { return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, @@ -53,8 +53,8 @@ namespace Ryujinx.Tests.Cpu #endregion [Test, Description("ADD , , ")] - public void Add_S_D([ValueSource("_D_")] [Random(1)] ulong A, - [ValueSource("_D_")] [Random(1)] ulong B) + public void Add_S_D([ValueSource("_1D_")] [Random(1)] ulong A, + [ValueSource("_1D_")] [Random(1)] ulong B) { uint Opcode = 0x5EE28420; // ADD D0, D1, D2 Bits Op = new Bits(Opcode); @@ -95,10 +95,10 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADD ., ., .")] - public void Add_V_16B_8H_4S_2D([ValueSource("_16B8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_16B8H4S2D_")] [Random(1)] ulong A1, - [ValueSource("_16B8H4S2D_")] [Random(1)] ulong B0, - [ValueSource("_16B8H4S2D_")] [Random(1)] ulong B1, + public void Add_V_16B_8H_4S_2D([ValueSource("_8B4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong B1, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { uint Opcode = 0x4E228420; // ADD V0.16B, V1.16B, V2.16B @@ -123,10 +123,10 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADDHN{2} ., ., .")] - public void Addhn_V_8H8B_4S4H_2D2S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong A1, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B1, + public void Addhn_V_8H8B_4S4H_2D2S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B1, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S> { uint Opcode = 0x0E224020; // ADDHN V0.8B, V1.8H, V2.8H @@ -152,10 +152,10 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADDHN{2} ., ., .")] - public void Addhn_V_8H16B_4S8H_2D4S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong A1, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B1, + public void Addhn_V_8H16B_4S8H_2D4S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B1, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S> { uint Opcode = 0x4E224020; // ADDHN2 V0.16B, V1.8H, V2.8H @@ -181,11 +181,61 @@ namespace Ryujinx.Tests.Cpu }); } + [Test, Description("ADDP ., ., .")] + public void Addp_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A, + [ValueSource("_8B4H2S_")] [Random(1)] ulong B, + [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> + { + uint Opcode = 0x0E22BC20; // ADDP V0.8B, V1.8B, V2.8B + Opcode |= ((size & 3) << 22); + Bits Op = new Bits(Opcode); + + AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() }; + AVec V1 = new AVec { X0 = A }; + AVec V2 = new AVec { X0 = B }; + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); + + AArch64.V(1, new Bits(A)); + AArch64.V(2, new Bits(B)); + SimdFp.Addp_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); + + Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64())); + Assert.That(ThreadState.V0.X1, Is.Zero); + } + + [Test, Pairwise, Description("ADDP ., ., .")] + public void Addp_V_16B_8H_4S_2D([ValueSource("_8B4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong B1, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> + { + uint Opcode = 0x4E22BC20; // ADDP V0.16B, V1.16B, V2.16B + Opcode |= ((size & 3) << 22); + Bits Op = new Bits(Opcode); + + AVec V1 = new AVec { X0 = A0, X1 = A1 }; + AVec V2 = new AVec { X0 = B0, X1 = B1 }; + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + AArch64.Vpart(1, 0, new Bits(A0)); + AArch64.Vpart(1, 1, new Bits(A1)); + AArch64.Vpart(2, 0, new Bits(B0)); + AArch64.Vpart(2, 1, new Bits(B1)); + SimdFp.Addp_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); + Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); + }); + } + [Test, Pairwise, Description("RADDHN{2} ., ., .")] - public void Raddhn_V_8H8B_4S4H_2D2S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong A1, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B1, + public void Raddhn_V_8H8B_4S4H_2D2S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B1, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S> { uint Opcode = 0x2E224020; // RADDHN V0.8B, V1.8H, V2.8H @@ -211,10 +261,10 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RADDHN{2} ., ., .")] - public void Raddhn_V_8H16B_4S8H_2D4S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong A1, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B1, + public void Raddhn_V_8H16B_4S8H_2D4S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B1, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S> { uint Opcode = 0x6E224020; // RADDHN2 V0.16B, V1.8H, V2.8H @@ -241,10 +291,10 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RSUBHN{2} ., ., .")] - public void Rsubhn_V_8H8B_4S4H_2D2S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong A1, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B1, + public void Rsubhn_V_8H8B_4S4H_2D2S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B1, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S> { uint Opcode = 0x2E226020; // RSUBHN V0.8B, V1.8H, V2.8H @@ -270,10 +320,10 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RSUBHN{2} ., ., .")] - public void Rsubhn_V_8H16B_4S8H_2D4S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong A1, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B1, + public void Rsubhn_V_8H16B_4S8H_2D4S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B1, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S> { uint Opcode = 0x6E226020; // RSUBHN2 V0.16B, V1.8H, V2.8H @@ -300,8 +350,8 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SUB , , ")] - public void Sub_S_D([ValueSource("_D_")] [Random(1)] ulong A, - [ValueSource("_D_")] [Random(1)] ulong B) + public void Sub_S_D([ValueSource("_1D_")] [Random(1)] ulong A, + [ValueSource("_1D_")] [Random(1)] ulong B) { uint Opcode = 0x7EE28420; // SUB D0, D1, D2 Bits Op = new Bits(Opcode); @@ -342,10 +392,10 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUB ., ., .")] - public void Sub_V_16B_8H_4S_2D([ValueSource("_16B8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_16B8H4S2D_")] [Random(1)] ulong A1, - [ValueSource("_16B8H4S2D_")] [Random(1)] ulong B0, - [ValueSource("_16B8H4S2D_")] [Random(1)] ulong B1, + public void Sub_V_16B_8H_4S_2D([ValueSource("_8B4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_8B4H2S1D_")] [Random(1)] ulong B1, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { uint Opcode = 0x6E228420; // SUB V0.16B, V1.16B, V2.16B @@ -370,10 +420,10 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUBHN{2} ., ., .")] - public void Subhn_V_8H8B_4S4H_2D2S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong A1, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B1, + public void Subhn_V_8H8B_4S4H_2D2S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B1, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S> { uint Opcode = 0x0E226020; // SUBHN V0.8B, V1.8H, V2.8H @@ -399,10 +449,10 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUBHN{2} ., ., .")] - public void Subhn_V_8H16B_4S8H_2D4S([ValueSource("_8H4S2D_")] [Random(1)] ulong A0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong A1, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B0, - [ValueSource("_8H4S2D_")] [Random(1)] ulong B1, + public void Subhn_V_8H16B_4S8H_2D4S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong A1, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B0, + [ValueSource("_4H2S1D_")] [Random(1)] ulong B1, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S> { uint Opcode = 0x4E226020; // SUBHN2 V0.16B, V1.8H, V2.8H diff --git a/Ryujinx.Tests/Cpu/Tester/Instructions.cs b/Ryujinx.Tests/Cpu/Tester/Instructions.cs index 2ca76ffd..e866a9a0 100644 --- a/Ryujinx.Tests/Cpu/Tester/Instructions.cs +++ b/Ryujinx.Tests/Cpu/Tester/Instructions.cs @@ -1763,6 +1763,53 @@ namespace Ryujinx.Tests.Cpu.Tester V(d, result); } + // https://meriac.github.io/archex/A64_v83A_ISA/addp_advsimd_pair.xml + public static void Addp_S(Bits size, Bits Rn, Bits Rd) + { + /* Decode Scalar */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + + /* if size != '11' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = esize * 2; + // int elements = 2; + + ReduceOp op = ReduceOp.ReduceOp_ADD; + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits operand = V(datasize, n); + + V(d, Reduce(op, operand, esize)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/addv_advsimd.xml + public static void Addv_V(bool Q, Bits size, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + + /* if size:Q == '100' then ReservedValue(); */ + /* if size == '11' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = (Q ? 128 : 64); + // int elements = datasize / esize; + + ReduceOp op = ReduceOp.ReduceOp_ADD; + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits operand = V(datasize, n); + + V(d, Reduce(op, operand, esize)); + } + // https://meriac.github.io/archex/A64_v83A_ISA/neg_advsimd.xml#NEG_asisdmisc_R public static void Neg_S(Bits size, Bits Rn, Bits Rd) { @@ -1995,6 +2042,41 @@ namespace Ryujinx.Tests.Cpu.Tester Vpart(d, part, result); } + // https://meriac.github.io/archex/A64_v83A_ISA/addp_advsimd_vec.xml + public static void Addp_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + /* Decode Vector */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size:Q == '110' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = (Q ? 128 : 64); + int elements = datasize / esize; + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(datasize); + Bits operand1 = V(datasize, n); + Bits operand2 = V(datasize, m); + Bits concat = Bits.Concat(operand2, operand1); + Bits element1; + Bits element2; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = Elem(concat, 2 * e, esize); + element2 = Elem(concat, (2 * e) + 1, esize); + + Elem(result, e, esize, element1 + element2); + } + + V(d, result); + } + // https://meriac.github.io/archex/A64_v83A_ISA/raddhn_advsimd.xml public static void Raddhn_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) { diff --git a/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs b/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs index 21c3935c..cfe8aa3d 100644 --- a/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs +++ b/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs @@ -442,6 +442,56 @@ namespace Ryujinx.Tests.Cpu.Tester // #ShiftType public enum ShiftType {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}; #endregion + +#region "instrs/vector/reduce/reduceop/" + public static Bits Reduce(ReduceOp op, Bits input, int esize) + { + int N = input.Count; + + int half; + Bits hi; + Bits lo; + Bits result = new Bits(esize); + + if (N == esize) + { + return new Bits(input); + } + + half = N / 2; + hi = Reduce(op, input[N - 1, half], esize); + lo = Reduce(op, input[half - 1, 0], esize); + + switch (op) + { + case ReduceOp.ReduceOp_FMINNUM: + /* result = FPMinNum(lo, hi, FPCR); */ + break; + case ReduceOp.ReduceOp_FMAXNUM: + /* result = FPMaxNum(lo, hi, FPCR); */ + break; + case ReduceOp.ReduceOp_FMIN: + /* result = FPMin(lo, hi, FPCR); */ + break; + case ReduceOp.ReduceOp_FMAX: + /* result = FPMax(lo, hi, FPCR); */ + break; + case ReduceOp.ReduceOp_FADD: + /* result = FPAdd(lo, hi, FPCR); */ + break; + default: + case ReduceOp.ReduceOp_ADD: + result = lo + hi; + break; + } + + return result; + } + + public enum ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, + ReduceOp_FMIN, ReduceOp_FMAX, + ReduceOp_FADD, ReduceOp_ADD}; +#endregion } internal static class Shared